RV_TIMER Simulation Results

Tuesday May 16 2023 07:02:31 UTC

GitHub Revision: `50278df8b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1341560578

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	41.068m	171.643ms	192	200	96.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.630s	78.959us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.620s	86.947us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.590s	1.380ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.700s	95.200us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.600s	35.083us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.620s	86.947us	20	20	100.00
		rv_timer_csr_aliasing	0.700s	95.200us	5	5	100.00
V1		TOTAL			247	255	96.86
V2	random_reset	rv_timer_random_reset	29.551m	247.211ms	50	50	100.00
V2	disabled	rv_timer_disabled	4.941m	886.063ms	50	50	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	25.445m	2.579s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	25.445m	2.579s	50	50	100.00
V2	stress	rv_timer_stress_all	1.677h	3.949s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.630s	50.070us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.060s	324.228us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.060s	324.228us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.630s	78.959us	5	5	100.00
		rv_timer_csr_rw	0.620s	86.947us	20	20	100.00
		rv_timer_csr_aliasing	0.700s	95.200us	5	5	100.00
		rv_timer_same_csr_outstanding	0.830s	68.291us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.630s	78.959us	5	5	100.00
		rv_timer_csr_rw	0.620s	86.947us	20	20	100.00
		rv_timer_csr_aliasing	0.700s	95.200us	5	5	100.00
		rv_timer_same_csr_outstanding	0.830s	68.291us	20	20	100.00
V2		TOTAL			290	290	100.00
V2S	tl_intg_err	rv_timer_sec_cm	0.830s	58.564us	5	5	100.00
		rv_timer_tl_intg_err	1.430s	264.555us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.430s	264.555us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	22.421m	399.331ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			612	620	98.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	7	100.00
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.38	98.73	100.00	--	100.00	100.00	99.66

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 8 failures:

Test rv_timer_random has 8 failures.

6.rv_timer_random.1544703404
Line 218, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

66.rv_timer_random.56579013
Line 220, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/66.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.