9601d3bbdd| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 33.300m | 570.689ms | 199 | 200 | 99.50 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.580s | 18.310us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.590s | 24.358us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.490s | 1.449ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.790s | 32.959us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.590s | 179.913us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.590s | 24.358us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.790s | 32.959us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 254 | 255 | 99.61 | |||
| V2 | random_reset | rv_timer_random_reset | 19.764m | 380.880ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 6.480m | 939.383ms | 45 | 50 | 90.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 20.618m | 709.482ms | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 20.618m | 709.482ms | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.367h | 832.924ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.620s | 11.880us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.470s | 377.114us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.470s | 377.114us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.580s | 18.310us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.590s | 24.358us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.790s | 32.959us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.790s | 20.663us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.580s | 18.310us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.590s | 24.358us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.790s | 32.959us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.790s | 20.663us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 285 | 290 | 98.28 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.860s | 214.676us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.420s | 122.708us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.420s | 122.708us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 30.087m | 582.878ms | 50 | 50 | 100.00 |
| V3 | TOTAL | 50 | 50 | 100.00 | |||
| TOTAL | 614 | 620 | 99.03 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 1 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.61 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.55 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
3.rv_timer_disabled.49345517658179346822416588340624004725891221503170962363250134794399246113700
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rv_timer_disabled.17729383788227565120778381470693223382718017858346116076923222788346651124877
Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/12.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
196.rv_timer_random.102410926691002486065776089140998034254964751626287626977767755461291297389833
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/196.rv_timer_random/latest/run.log
Job ID: smart:a22d6213-abec-436d-b681-2adb04222bad