0cb61fc7e7| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 52.536m | 395.735ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.580s | 28.656us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.660s | 38.085us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.690s | 829.934us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.810s | 38.841us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.640s | 71.776us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.660s | 38.085us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.810s | 38.841us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 33.853m | 73.907ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 5.719m | 852.512ms | 49 | 50 | 98.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 17.327m | 841.893ms | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 17.327m | 841.893ms | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 50.082m | 2.796s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.610s | 15.659us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.390s | 816.200us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.390s | 816.200us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.580s | 28.656us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.660s | 38.085us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.810s | 38.841us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.790s | 230.983us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.580s | 28.656us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.660s | 38.085us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.810s | 38.841us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.790s | 230.983us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 289 | 290 | 99.66 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.920s | 249.998us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.390s | 147.312us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.390s | 147.312us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 25.186m | 406.589ms | 15 | 50 | 30.00 |
| V3 | TOTAL | 15 | 50 | 30.00 | |||
| TOTAL | 584 | 620 | 94.19 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.59 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.43 |
UVM_ERROR (cip_base_vseq.sv:829) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
0.rv_timer_stress_all_with_rand_reset.54758619912022004162707794321908593426120862282415833271785597370868027262360
Line 746, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 124239538315 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10020 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 124239538315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.7491985754674336411809153619519061544004665885720325655201555794522483389652
Line 848, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 121964372493 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 121964372493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 33 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
7.rv_timer_disabled.1836340487368702091024451951758378171707525530204592321724159162965560759059
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---