Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65729893	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	66707474	1		T1	118096		T2	107		T3	5148

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	131589889	1		T1	236005		T2	187		T3	10154
values[0x0]	403208	1		T1	17		T2	6		T3	25
values[0x1]	444270	1		T1	24		T2	4		T3	30

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52502179	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	79935188	1		T1	141719		T2	123		T3	6170

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	388397	1		T1	9117		T5	1950		T8	2295
valid_sources[0x01]	387090	1		T1	9261		T5	2037		T8	2229
valid_sources[0x02]	385885	1		T1	9003		T5	1832		T8	2293
valid_sources[0x03]	1033273	1		T1	9454		T5	1918		T8	2289
valid_sources[0x04]	386442	1		T1	9217		T5	1758		T8	2391
valid_sources[0x05]	385079	1		T1	9082		T5	1849		T8	2335
valid_sources[0x06]	387561	1		T1	9103		T5	1861		T8	2388
valid_sources[0x07]	385350	1		T1	9336		T5	1768		T8	2262
valid_sources[0x08]	387223	1		T1	9225		T5	1935		T8	2306
valid_sources[0x09]	388055	1		T1	9388		T5	1744		T8	2141
valid_sources[0x0a]	386839	1		T1	9141		T2	1		T5	1857
valid_sources[0x0b]	564453	1		T1	9113		T2	2		T5	1725
valid_sources[0x0c]	451766	1		T1	9320		T2	2		T5	1818
valid_sources[0x0d]	385012	1		T1	9093		T5	1947		T8	2229
valid_sources[0x0e]	386983	1		T1	9209		T5	1791		T8	2403
valid_sources[0x0f]	386379	1		T1	9159		T5	1688		T8	2347
valid_sources[0x10]	387978	1		T1	9213		T5	1690		T8	2481
valid_sources[0x11]	387960	1		T1	9239		T2	3		T5	1781
valid_sources[0x12]	387399	1		T1	9326		T2	2		T5	1691
valid_sources[0x13]	384868	1		T1	9342		T2	1		T5	1707
valid_sources[0x14]	5993762	1		T1	9158		T5	1976		T8	2255
valid_sources[0x15]	390253	1		T1	9361		T2	1		T5	1803
valid_sources[0x16]	384434	1		T1	9084		T2	1		T5	1746
valid_sources[0x17]	386872	1		T1	9148		T5	1710		T8	2113
valid_sources[0x18]	387598	1		T1	9183		T5	1841		T8	2265
valid_sources[0x19]	385768	1		T1	9266		T5	1927		T8	2259
valid_sources[0x1a]	388595	1		T1	9117		T2	1		T5	1819
valid_sources[0x1b]	386365	1		T1	9267		T5	1948		T8	2367
valid_sources[0x1c]	459246	1		T1	9250		T5	1855		T8	2305
valid_sources[0x1d]	385177	1		T1	9253		T5	1702		T8	2495
valid_sources[0x1e]	386101	1		T1	9234		T5	1917		T8	2226
valid_sources[0x1f]	407279	1		T1	9067		T2	2		T5	1813
valid_sources[0x20]	386263	1		T1	9235		T5	1825		T8	2354
valid_sources[0x21]	391060	1		T1	9168		T2	2		T5	1923
valid_sources[0x22]	386326	1		T1	9154		T2	2		T5	1744
valid_sources[0x23]	386405	1		T1	9363		T5	1722		T8	2182
valid_sources[0x24]	385454	1		T1	9236		T5	1745		T8	2312
valid_sources[0x25]	411098	1		T1	9177		T5	1660		T8	2272
valid_sources[0x26]	384462	1		T1	9204		T2	1		T5	1933
valid_sources[0x27]	384571	1		T1	9102		T2	2		T5	1887
valid_sources[0x28]	451152	1		T1	9150		T5	1871		T8	2287
valid_sources[0x29]	388415	1		T1	9075		T5	1870		T8	2130
valid_sources[0x2a]	385444	1		T1	9278		T5	1632		T8	2308
valid_sources[0x2b]	568598	1		T1	9268		T5	1630		T8	2533
valid_sources[0x2c]	385957	1		T1	9324		T5	1774		T8	2406
valid_sources[0x2d]	390612	1		T1	9150		T5	1793		T8	2321
valid_sources[0x2e]	385393	1		T1	9375		T5	1791		T8	2341
valid_sources[0x2f]	387461	1		T1	9380		T2	2		T5	1677
valid_sources[0x30]	392856	1		T1	9297		T2	1		T5	1965
valid_sources[0x31]	690804	1		T1	9081		T5	1719		T8	2491
valid_sources[0x32]	1219839	1		T1	9175		T5	2136		T8	2311
valid_sources[0x33]	538266	1		T1	9163		T2	2		T5	1901
valid_sources[0x34]	391900	1		T1	9209		T5	1899		T8	2492
valid_sources[0x35]	388618	1		T1	9362		T2	4		T5	1828
valid_sources[0x36]	688571	1		T1	9325		T5	1914		T8	2082
valid_sources[0x37]	382309	1		T1	9315		T5	1899		T8	2287
valid_sources[0x38]	510908	1		T1	9351		T5	1828		T8	2425
valid_sources[0x39]	386769	1		T1	9047		T2	1		T5	1752
valid_sources[0x3a]	1363647	1		T1	9163		T5	1832		T8	2272
valid_sources[0x3b]	2488286	1		T1	9267		T5	1867		T8	2280
valid_sources[0x3c]	386709	1		T1	9140		T5	1657		T8	2282
valid_sources[0x3d]	405071	1		T1	9322		T5	1837		T8	2182
valid_sources[0x3e]	387604	1		T1	9321		T5	1696		T8	2416
valid_sources[0x3f]	387695	1		T1	9241		T2	4		T5	1887
valid_sources[0x40]	388174	1		T1	9196		T5	1848		T8	2343
valid_sources[0x41]	386639	1		T1	9237		T5	1716		T8	2352
valid_sources[0x42]	384695	1		T1	9038		T2	6		T5	1843
valid_sources[0x43]	396327	1		T1	9208		T2	3		T5	1971
valid_sources[0x44]	385097	1		T1	9186		T5	1961		T8	2248
valid_sources[0x45]	387047	1		T1	9377		T5	1902		T8	2337
valid_sources[0x46]	413078	1		T1	9077		T5	1682		T8	2267
valid_sources[0x47]	390565	1		T1	9363		T2	2		T5	1819
valid_sources[0x48]	386823	1		T1	9240		T5	1808		T8	2258
valid_sources[0x49]	389379	1		T1	9228		T5	1860		T8	2353
valid_sources[0x4a]	386026	1		T1	9307		T2	3		T5	1970
valid_sources[0x4b]	389679	1		T1	9155		T2	1		T5	1857
valid_sources[0x4c]	435400	1		T1	9205		T5	1955		T8	2410
valid_sources[0x4d]	386182	1		T1	9209		T5	1910		T8	2265
valid_sources[0x4e]	385712	1		T1	8913		T2	2		T5	1793
valid_sources[0x4f]	385393	1		T1	9299		T5	1752		T8	2253
valid_sources[0x50]	387344	1		T1	9253		T5	1884		T8	2547
valid_sources[0x51]	385279	1		T1	9244		T5	1780		T8	2400
valid_sources[0x52]	386113	1		T1	9237		T5	1870		T8	2188
valid_sources[0x53]	386551	1		T1	9071		T5	1783		T8	2358
valid_sources[0x54]	386980	1		T1	9188		T5	1864		T8	2154
valid_sources[0x55]	387391	1		T1	9328		T2	1		T5	1736
valid_sources[0x56]	448134	1		T1	9187		T2	2		T5	1910
valid_sources[0x57]	392935	1		T1	9174		T5	1847		T8	2452
valid_sources[0x58]	386609	1		T1	9084		T2	1		T5	1651
valid_sources[0x59]	385305	1		T1	9248		T5	1694		T8	2263
valid_sources[0x5a]	661670	1		T1	9281		T2	1		T5	2015
valid_sources[0x5b]	387026	1		T1	9174		T5	1777		T8	2294
valid_sources[0x5c]	387243	1		T1	9119		T5	1890		T8	2349
valid_sources[0x5d]	386924	1		T1	9275		T2	4		T5	1748
valid_sources[0x5e]	407600	1		T1	9425		T5	1808		T8	2509
valid_sources[0x5f]	386068	1		T1	9232		T2	1		T5	1747
valid_sources[0x60]	386527	1		T1	9250		T2	1		T5	1725
valid_sources[0x61]	386832	1		T1	9254		T5	2032		T8	2419
valid_sources[0x62]	700607	1		T1	9339		T2	1		T5	1937
valid_sources[0x63]	389574	1		T1	9238		T2	2		T5	1759
valid_sources[0x64]	384549	1		T1	8997		T5	1826		T8	2253
valid_sources[0x65]	389020	1		T1	9308		T5	1978		T8	2355
valid_sources[0x66]	540542	1		T1	9182		T2	4		T5	1763
valid_sources[0x67]	400476	1		T1	9226		T5	2019		T8	2448
valid_sources[0x68]	388534	1		T1	9096		T2	1		T5	1980
valid_sources[0x69]	386921	1		T1	9155		T2	1		T5	1813
valid_sources[0x6a]	1054157	1		T1	9162		T5	1620		T8	2336
valid_sources[0x6b]	388850	1		T1	9294		T2	3		T5	1800
valid_sources[0x6c]	387027	1		T1	9242		T2	1		T5	1997
valid_sources[0x6d]	384921	1		T1	9129		T5	1866		T8	2366
valid_sources[0x6e]	412957	1		T1	9239		T5	1858		T8	2209
valid_sources[0x6f]	388386	1		T1	9212		T2	1		T5	1872
valid_sources[0x70]	387194	1		T1	9020		T5	1746		T8	2273
valid_sources[0x71]	382845	1		T1	9354		T5	1740		T8	2430
valid_sources[0x72]	387178	1		T1	9259		T5	1792		T8	2403
valid_sources[0x73]	2782109	1		T1	9291		T5	1797		T8	2260
valid_sources[0x74]	385761	1		T1	9218		T5	1716		T8	2420
valid_sources[0x75]	398707	1		T1	9228		T5	1835		T8	2343
valid_sources[0x76]	388055	1		T1	9126		T2	1		T5	1858
valid_sources[0x77]	386106	1		T1	9126		T5	1991		T8	2101
valid_sources[0x78]	386972	1		T1	9378		T5	1750		T8	2283
valid_sources[0x79]	386075	1		T1	9210		T5	1983		T8	2397
valid_sources[0x7a]	386477	1		T1	9405		T2	3		T5	1722
valid_sources[0x7b]	388698	1		T1	9189		T5	1925		T8	2324
valid_sources[0x7c]	593532	1		T1	9460		T5	1960		T8	2378
valid_sources[0x7d]	619304	1		T1	9264		T5	1837		T8	2358
valid_sources[0x7e]	385526	1		T1	9267		T5	2060		T8	2434
valid_sources[0x7f]	1681713	1		T1	9100		T5	1868		T8	2393
valid_sources[0x80]	387103	1		T1	9242		T2	2		T5	1825

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65921557

1

T1

118094

T2

98

T3

5102

values[0x0]

all_enables

biggest_size

394075

1

T1

10

T2

6

T3

20

values[0x1]

all_enables

biggest_size

391842

1

T1

17

T2

3

T3

26