Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1368475	0	0
cfg0_rd_A	2147483647	2233	0	0
compare_lower0_0_rd_A	2147483647	2161	0	0
compare_upper0_0_rd_A	2147483647	2308	0	0
ctrl_rd_A	2147483647	2095	0	0
intr_enable0_rd_A	2147483647	2831	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1368475	0	0
T15	752673	227524	0	0
T16	0	137016	0	0
T17	0	118029	0	0
T30	0	6	0	0
T35	0	175425	0	0
T36	0	216665	0	0
T37	0	301573	0	0
T38	0	136961	0	0
T39	0	41718	0	0
T40	0	793	0	0
T41	122925	0	0	0
T42	151696	0	0	0
T43	264073	0	0	0
T44	110614	0	0	0
T45	315556	0	0	0
T46	285316	0	0	0
T47	659925	0	0	0
T48	410866	0	0	0
T49	398058	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2233	0	0
T17	419252	620	0	0
T30	0	84	0	0
T34	0	467	0	0
T40	0	3	0	0
T50	0	6	0	0
T51	0	18	0	0
T52	0	5	0	0
T53	0	8	0	0
T54	0	43	0	0
T55	0	16	0	0
T56	674109	0	0	0
T57	168859	0	0	0
T58	153996	0	0	0
T59	15172	0	0	0
T60	701578	0	0	0
T61	161536	0	0	0
T62	139672	0	0	0
T63	518277	0	0	0
T64	199732	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2161	0	0
T17	419252	719	0	0
T30	0	54	0	0
T34	0	398	0	0
T40	0	19	0	0
T51	0	16	0	0
T53	0	19	0	0
T54	0	18	0	0
T55	0	12	0	0
T56	674109	0	0	0
T57	168859	0	0	0
T58	153996	0	0	0
T59	15172	0	0	0
T60	701578	0	0	0
T61	161536	0	0	0
T62	139672	0	0	0
T63	518277	0	0	0
T64	199732	0	0	0
T65	0	8	0	0
T66	0	8	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2308	0	0
T17	419252	694	0	0
T30	0	73	0	0
T34	0	512	0	0
T40	0	13	0	0
T51	0	11	0	0
T53	0	5	0	0
T54	0	25	0	0
T55	0	10	0	0
T56	674109	0	0	0
T57	168859	0	0	0
T58	153996	0	0	0
T59	15172	0	0	0
T60	701578	0	0	0
T61	161536	0	0	0
T62	139672	0	0	0
T63	518277	0	0	0
T64	199732	0	0	0
T65	0	19	0	0
T66	0	1	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2095	0	0
T17	419252	636	0	0
T30	0	79	0	0
T34	0	418	0	0
T40	0	2	0	0
T50	0	3	0	0
T51	0	18	0	0
T53	0	13	0	0
T54	0	57	0	0
T56	674109	0	0	0
T57	168859	0	0	0
T58	153996	0	0	0
T59	15172	0	0	0
T60	701578	0	0	0
T61	161536	0	0	0
T62	139672	0	0	0
T63	518277	0	0	0
T64	199732	0	0	0
T65	0	6	0	0
T66	0	2	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2831	0	0
T10	182766	92	0	0
T11	7597	0	0	0
T12	108979	0	0	0
T13	163186	0	0	0
T17	0	727	0	0
T22	857001	0	0	0
T23	227694	0	0	0
T34	0	407	0	0
T61	0	74	0	0
T67	0	87	0	0
T68	0	40	0	0
T69	0	17	0	0
T70	0	54	0	0
T71	0	18	0	0
T72	0	21	0	0
T73	876245	0	0	0
T74	844345	0	0	0
T75	175457	0	0	0
T76	128520	0	0	0