Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66030094	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	66787958	1		T1	28		T2	15395		T3	586907

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	132178099	1		T1	48		T2	30736		T3	117307
values[0x0]	305377	1		T1	6		T2	9		T3	55
values[0x1]	334576	1		T1	3		T2	11		T3	49

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52747851	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	80070201	1		T1	32		T2	18516		T3	704168

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	410846	1		T2	34		T3	4163		T5	9
valid_sources[0x01]	413233	1		T2	188		T3	4788		T5	10
valid_sources[0x02]	1930121	1		T2	175		T3	4693		T5	5
valid_sources[0x03]	410112	1		T2	115		T3	5088		T5	7
valid_sources[0x04]	419379	1		T2	147		T3	4374		T5	15
valid_sources[0x05]	446747	1		T2	155		T3	3993		T5	5
valid_sources[0x06]	418329	1		T2	195		T3	4334		T5	5
valid_sources[0x07]	414764	1		T2	80		T3	4713		T5	12
valid_sources[0x08]	414589	1		T2	135		T3	4085		T5	8
valid_sources[0x09]	412482	1		T2	131		T3	4312		T5	7
valid_sources[0x0a]	411057	1		T2	175		T3	4775		T5	9
valid_sources[0x0b]	1127955	1		T2	84		T3	4496		T5	11
valid_sources[0x0c]	412038	1		T1	2		T2	104		T3	4453
valid_sources[0x0d]	412349	1		T2	40		T3	4476		T5	2
valid_sources[0x0e]	414100	1		T2	73		T3	4813		T5	15
valid_sources[0x0f]	416745	1		T2	74		T3	4632		T5	10
valid_sources[0x10]	413947	1		T2	100		T3	4577		T5	7
valid_sources[0x11]	414343	1		T2	159		T3	4910		T5	4
valid_sources[0x12]	472861	1		T2	288		T3	4322		T5	10
valid_sources[0x13]	409397	1		T2	55		T3	4606		T5	8
valid_sources[0x14]	412580	1		T2	110		T3	4954		T5	10
valid_sources[0x15]	801389	1		T1	2		T2	136		T3	4653
valid_sources[0x16]	410131	1		T1	1		T2	85		T3	4341
valid_sources[0x17]	410469	1		T2	58		T3	4737		T5	13
valid_sources[0x18]	414419	1		T2	69		T3	4527		T5	11
valid_sources[0x19]	412196	1		T2	93		T3	5315		T5	8
valid_sources[0x1a]	413018	1		T2	71		T3	4569		T5	7
valid_sources[0x1b]	412613	1		T2	167		T3	4291		T5	9
valid_sources[0x1c]	412788	1		T2	125		T3	4736		T5	14
valid_sources[0x1d]	412100	1		T2	103		T3	4482		T5	6
valid_sources[0x1e]	416395	1		T2	103		T3	4842		T5	7
valid_sources[0x1f]	418702	1		T1	1		T2	101		T3	4405
valid_sources[0x20]	4900407	1		T2	242		T3	4661		T5	10
valid_sources[0x21]	418307	1		T2	206		T3	4409		T5	8
valid_sources[0x22]	425347	1		T2	72		T3	4806		T5	7
valid_sources[0x23]	411011	1		T2	158		T3	4427		T5	4
valid_sources[0x24]	412837	1		T2	97		T3	4591		T5	4
valid_sources[0x25]	412568	1		T2	110		T3	3933		T5	8
valid_sources[0x26]	411406	1		T1	2		T2	178		T3	4926
valid_sources[0x27]	409724	1		T2	122		T3	4556		T5	9
valid_sources[0x28]	409986	1		T2	121		T3	4910		T5	10
valid_sources[0x29]	415388	1		T2	111		T3	4685		T5	5
valid_sources[0x2a]	470712	1		T1	1		T2	113		T3	5022
valid_sources[0x2b]	1127377	1		T2	115		T3	5069		T5	11
valid_sources[0x2c]	413248	1		T2	200		T3	4682		T5	9
valid_sources[0x2d]	415095	1		T2	100		T3	4687		T5	10
valid_sources[0x2e]	412767	1		T2	133		T3	4598		T5	10
valid_sources[0x2f]	415785	1		T2	106		T3	4837		T5	3
valid_sources[0x30]	408035	1		T2	196		T3	4454		T5	8
valid_sources[0x31]	420163	1		T2	178		T3	4044		T5	7
valid_sources[0x32]	930412	1		T2	120		T3	4601		T5	3
valid_sources[0x33]	416172	1		T2	74		T3	4718		T5	9
valid_sources[0x34]	680346	1		T2	116		T3	4828		T5	1
valid_sources[0x35]	417802	1		T2	70		T3	5060		T5	13
valid_sources[0x36]	410149	1		T2	118		T3	4600		T5	9
valid_sources[0x37]	437954	1		T2	183		T3	5009		T5	7
valid_sources[0x38]	413004	1		T2	119		T3	4358		T5	7
valid_sources[0x39]	410965	1		T2	111		T3	4467		T5	13
valid_sources[0x3a]	409164	1		T1	1		T2	112		T3	4439
valid_sources[0x3b]	412500	1		T1	1		T2	115		T3	4340
valid_sources[0x3c]	410323	1		T1	1		T2	157		T3	4341
valid_sources[0x3d]	420340	1		T2	172		T3	4791		T5	9
valid_sources[0x3e]	415103	1		T2	201		T3	4546		T5	8
valid_sources[0x3f]	409324	1		T2	181		T3	4730		T5	10
valid_sources[0x40]	411556	1		T2	151		T3	4772		T5	8
valid_sources[0x41]	533535	1		T1	1		T2	44		T3	4627
valid_sources[0x42]	410962	1		T2	120		T3	4882		T5	7
valid_sources[0x43]	417171	1		T2	126		T3	4660		T5	5
valid_sources[0x44]	411148	1		T2	152		T3	4694		T5	11
valid_sources[0x45]	464807	1		T2	160		T3	4441		T5	5
valid_sources[0x46]	413133	1		T2	113		T3	4694		T5	7
valid_sources[0x47]	417500	1		T2	102		T3	4536		T5	9
valid_sources[0x48]	412193	1		T2	64		T3	4222		T5	7
valid_sources[0x49]	411287	1		T2	87		T3	4278		T5	8
valid_sources[0x4a]	421419	1		T2	65		T3	4107		T5	10
valid_sources[0x4b]	413172	1		T2	64		T3	4407		T5	11
valid_sources[0x4c]	411474	1		T2	128		T3	4230		T5	11
valid_sources[0x4d]	415184	1		T2	86		T3	4283		T5	7
valid_sources[0x4e]	412009	1		T2	157		T3	4295		T5	13
valid_sources[0x4f]	413393	1		T2	181		T3	4627		T5	10
valid_sources[0x50]	411493	1		T2	85		T3	4226		T5	9
valid_sources[0x51]	409772	1		T1	1		T2	158		T3	4719
valid_sources[0x52]	413025	1		T2	99		T3	4501		T5	11
valid_sources[0x53]	412188	1		T2	119		T3	4730		T5	8
valid_sources[0x54]	413911	1		T2	97		T3	4154		T5	13
valid_sources[0x55]	413539	1		T2	129		T3	4995		T5	4
valid_sources[0x56]	414774	1		T2	151		T3	4256		T5	9
valid_sources[0x57]	421288	1		T1	2		T2	190		T3	4347
valid_sources[0x58]	410480	1		T2	83		T3	4250		T5	9
valid_sources[0x59]	411539	1		T2	204		T3	4819		T5	8
valid_sources[0x5a]	410739	1		T2	100		T3	4187		T5	12
valid_sources[0x5b]	413391	1		T1	1		T2	86		T3	5461
valid_sources[0x5c]	411622	1		T2	76		T3	4626		T5	12
valid_sources[0x5d]	415114	1		T2	91		T3	4501		T5	12
valid_sources[0x5e]	1667893	1		T2	134		T3	4409		T5	8
valid_sources[0x5f]	413903	1		T1	1		T2	189		T3	4582
valid_sources[0x60]	416851	1		T2	152		T3	4784		T5	12
valid_sources[0x61]	411689	1		T2	89		T3	4362		T5	6
valid_sources[0x62]	414722	1		T2	116		T3	4884		T5	7
valid_sources[0x63]	412341	1		T2	93		T3	4865		T5	13
valid_sources[0x64]	527744	1		T1	1		T2	73		T3	4479
valid_sources[0x65]	552515	1		T2	79		T3	4450		T5	12
valid_sources[0x66]	412797	1		T2	109		T3	4781		T5	11
valid_sources[0x67]	410730	1		T2	99		T3	4615		T5	6
valid_sources[0x68]	411237	1		T2	98		T3	4094		T5	7
valid_sources[0x69]	413534	1		T2	80		T3	4236		T5	2
valid_sources[0x6a]	410540	1		T2	133		T3	4683		T5	4
valid_sources[0x6b]	414373	1		T2	130		T3	4474		T5	6
valid_sources[0x6c]	409810	1		T1	1		T2	130		T3	4108
valid_sources[0x6d]	556446	1		T2	109		T3	4839		T5	7
valid_sources[0x6e]	411393	1		T2	127		T3	4373		T5	17
valid_sources[0x6f]	414193	1		T2	101		T3	4597		T5	13
valid_sources[0x70]	414732	1		T2	164		T3	4412		T5	11
valid_sources[0x71]	419067	1		T2	101		T3	4580		T5	8
valid_sources[0x72]	1185269	1		T2	91		T3	4749		T5	10
valid_sources[0x73]	409784	1		T2	67		T3	5074		T5	9
valid_sources[0x74]	1085288	1		T2	85		T3	4070		T5	10
valid_sources[0x75]	854784	1		T2	140		T3	4344		T5	6
valid_sources[0x76]	411686	1		T2	97		T3	5118		T5	5
valid_sources[0x77]	699224	1		T2	157		T3	4716		T5	8
valid_sources[0x78]	412653	1		T2	55		T3	4247		T5	9
valid_sources[0x79]	462529	1		T1	3		T2	107		T3	5096
valid_sources[0x7a]	414330	1		T2	119		T3	4275		T5	8
valid_sources[0x7b]	437712	1		T2	136		T3	4164		T5	13
valid_sources[0x7c]	410723	1		T1	1		T2	137		T3	4507
valid_sources[0x7d]	757189	1		T1	1		T2	102		T3	4916
valid_sources[0x7e]	414807	1		T2	95		T3	4817		T5	3
valid_sources[0x7f]	431028	1		T2	181		T3	4710		T5	15
valid_sources[0x80]	413856	1		T2	108		T3	4661		T5	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

66195780

1

T1

23

T2

15382

T3

586829

values[0x0]

all_enables

biggest_size

297452

1

T1

3

T2

5

T3

42

values[0x1]

all_enables

biggest_size

294726

1

T1

2

T2

8

T3

36