Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1002412	0	0
cfg0_rd_A	2147483647	6635	0	0
compare_lower0_0_rd_A	2147483647	7383	0	0
compare_upper0_0_rd_A	2147483647	6106	0	0
ctrl_rd_A	2147483647	6397	0	0
intr_enable0_rd_A	2147483647	8928	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1002412	0	0
T11	120956	247723	0	0
T12	0	105273	0	0
T13	0	73365	0	0
T31	0	151	0	0
T32	0	41	0	0
T35	0	109700	0	0
T36	0	160138	0	0
T37	0	204476	0	0
T38	0	88255	0	0
T39	0	617	0	0
T40	846712	0	0	0
T41	614412	0	0	0
T42	451237	0	0	0
T43	354571	0	0	0
T44	179446	0	0	0
T45	125524	0	0	0
T46	336744	0	0	0
T47	863571	0	0	0
T48	315034	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6635	0	0
T11	120956	2365	0	0
T35	0	1081	0	0
T37	0	2220	0	0
T40	846712	0	0	0
T41	614412	0	0	0
T42	451237	0	0	0
T43	354571	0	0	0
T44	179446	0	0	0
T45	125524	0	0	0
T46	336744	0	0	0
T47	863571	0	0	0
T48	315034	0	0	0
T49	0	7	0	0
T50	0	19	0	0
T51	0	12	0	0
T52	0	3	0	0
T53	0	23	0	0
T54	0	56	0	0
T55	0	15	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7383	0	0
T11	120956	2895	0	0
T35	0	1223	0	0
T37	0	2380	0	0
T40	846712	0	0	0
T41	614412	0	0	0
T42	451237	0	0	0
T43	354571	0	0	0
T44	179446	0	0	0
T45	125524	0	0	0
T46	336744	0	0	0
T47	863571	0	0	0
T48	315034	0	0	0
T49	0	15	0	0
T50	0	13	0	0
T51	0	3	0	0
T53	0	15	0	0
T54	0	50	0	0
T55	0	15	0	0
T56	0	35	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6106	0	0
T11	120956	2513	0	0
T35	0	915	0	0
T37	0	1847	0	0
T40	846712	0	0	0
T41	614412	0	0	0
T42	451237	0	0	0
T43	354571	0	0	0
T44	179446	0	0	0
T45	125524	0	0	0
T46	336744	0	0	0
T47	863571	0	0	0
T48	315034	0	0	0
T49	0	11	0	0
T50	0	37	0	0
T51	0	9	0	0
T52	0	4	0	0
T53	0	13	0	0
T54	0	40	0	0
T56	0	26	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6397	0	0
T11	120956	2493	0	0
T35	0	1103	0	0
T37	0	1952	0	0
T40	846712	0	0	0
T41	614412	0	0	0
T42	451237	0	0	0
T43	354571	0	0	0
T44	179446	0	0	0
T45	125524	0	0	0
T46	336744	0	0	0
T47	863571	0	0	0
T48	315034	0	0	0
T49	0	10	0	0
T50	0	10	0	0
T51	0	4	0	0
T53	0	5	0	0
T54	0	40	0	0
T55	0	7	0	0
T56	0	10	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8928	0	0
T9	433952	13	0	0
T10	440083	0	0	0
T11	0	3100	0	0
T43	0	146	0	0
T57	0	40	0	0
T58	0	31	0	0
T59	0	13	0	0
T60	0	51	0	0
T61	0	41	0	0
T62	0	74	0	0
T63	0	58	0	0
T64	622044	0	0	0
T65	781615	0	0	0
T66	440556	0	0	0
T67	614177	0	0	0
T68	415422	0	0	0
T69	377325	0	0	0
T70	218945	0	0	0
T71	909225	0	0	0