Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62084181	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	63300925	1		T1	866		T2	11313		T3	6704

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	124346114	1		T1	1669		T2	22695		T3	13126
values[0x0]	493927	1		T1	3		T2	14		T3	16
values[0x1]	545065	1		T1	10		T2	14		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49583175	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	75801931	1		T1	1036		T2	13532		T3	7994

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	368319	1		T1	7		T2	58		T4	1333
valid_sources[0x01]	370619	1		T1	3		T2	93		T4	1434
valid_sources[0x02]	368175	1		T1	6		T2	86		T4	1389
valid_sources[0x03]	370199	1		T1	6		T2	109		T4	1422
valid_sources[0x04]	372090	1		T1	8		T2	123		T4	1404
valid_sources[0x05]	369321	1		T1	5		T2	122		T4	1393
valid_sources[0x06]	374771	1		T1	3		T2	96		T4	1412
valid_sources[0x07]	364872	1		T1	6		T2	161		T4	1463
valid_sources[0x08]	368321	1		T1	3		T2	97		T4	1437
valid_sources[0x09]	370782	1		T1	7		T2	92		T4	1362
valid_sources[0x0a]	387749	1		T1	6		T2	76		T4	1399
valid_sources[0x0b]	368781	1		T1	8		T2	77		T4	1400
valid_sources[0x0c]	826610	1		T1	9		T2	82		T4	1335
valid_sources[0x0d]	369430	1		T1	13		T2	104		T4	1456
valid_sources[0x0e]	370058	1		T1	4		T2	158		T4	1538
valid_sources[0x0f]	368608	1		T1	3		T2	101		T4	1423
valid_sources[0x10]	368687	1		T1	3		T2	105		T4	1439
valid_sources[0x11]	369390	1		T1	6		T2	124		T4	1413
valid_sources[0x12]	480440	1		T1	11		T2	128		T4	1396
valid_sources[0x13]	368870	1		T1	5		T2	110		T4	1355
valid_sources[0x14]	370928	1		T1	5		T2	81		T4	1399
valid_sources[0x15]	370718	1		T1	15		T2	125		T4	1423
valid_sources[0x16]	368502	1		T1	5		T2	103		T4	1471
valid_sources[0x17]	472429	1		T1	9		T2	69		T4	1404
valid_sources[0x18]	368268	1		T1	8		T2	41		T4	1333
valid_sources[0x19]	370036	1		T1	1		T2	90		T4	1404
valid_sources[0x1a]	368774	1		T1	6		T2	93		T4	1423
valid_sources[0x1b]	939898	1		T1	2		T2	51		T4	1339
valid_sources[0x1c]	370082	1		T1	6		T2	82		T4	1336
valid_sources[0x1d]	370109	1		T1	5		T2	76		T4	1361
valid_sources[0x1e]	370982	1		T1	6		T2	77		T4	1428
valid_sources[0x1f]	367697	1		T1	6		T2	94		T4	1424
valid_sources[0x20]	367174	1		T1	1		T2	114		T4	1387
valid_sources[0x21]	368802	1		T1	2		T2	98		T4	1344
valid_sources[0x22]	368803	1		T1	9		T2	82		T4	1369
valid_sources[0x23]	367891	1		T1	5		T2	84		T4	1449
valid_sources[0x24]	368737	1		T1	6		T2	107		T4	1342
valid_sources[0x25]	368981	1		T1	3		T2	89		T4	1330
valid_sources[0x26]	370138	1		T1	9		T2	91		T4	1370
valid_sources[0x27]	370013	1		T1	5		T2	56		T4	1352
valid_sources[0x28]	368109	1		T2	37		T4	1361		T5	430
valid_sources[0x29]	393536	1		T1	11		T2	78		T4	1448
valid_sources[0x2a]	370998	1		T1	7		T2	104		T4	1400
valid_sources[0x2b]	368680	1		T1	10		T2	53		T4	1369
valid_sources[0x2c]	2745428	1		T1	5		T2	123		T4	1422
valid_sources[0x2d]	378787	1		T1	5		T2	82		T4	1355
valid_sources[0x2e]	368924	1		T1	14		T2	32		T4	1455
valid_sources[0x2f]	369465	1		T1	3		T2	185		T4	1405
valid_sources[0x30]	397355	1		T1	5		T2	94		T4	1446
valid_sources[0x31]	369425	1		T1	8		T2	101		T4	1385
valid_sources[0x32]	370548	1		T1	5		T2	98		T4	1372
valid_sources[0x33]	708751	1		T1	10		T2	83		T4	1440
valid_sources[0x34]	371342	1		T1	12		T2	91		T4	1363
valid_sources[0x35]	369369	1		T1	4		T2	86		T4	1377
valid_sources[0x36]	369030	1		T1	5		T2	39		T4	1385
valid_sources[0x37]	371151	1		T1	14		T2	146		T4	1394
valid_sources[0x38]	370491	1		T1	5		T2	41		T4	1381
valid_sources[0x39]	371474	1		T1	4		T2	145		T4	1407
valid_sources[0x3a]	377980	1		T1	5		T2	114		T4	1374
valid_sources[0x3b]	370595	1		T1	7		T2	83		T4	1462
valid_sources[0x3c]	366457	1		T1	7		T2	95		T4	1420
valid_sources[0x3d]	370415	1		T2	103		T4	1439		T5	366
valid_sources[0x3e]	371893	1		T1	6		T2	56		T4	1363
valid_sources[0x3f]	370185	1		T1	2		T2	50		T4	1406
valid_sources[0x40]	382193	1		T1	2		T2	49		T3	13152
valid_sources[0x41]	369208	1		T1	4		T2	84		T4	1383
valid_sources[0x42]	371704	1		T1	7		T2	123		T4	1353
valid_sources[0x43]	373898	1		T1	3		T2	149		T4	1348
valid_sources[0x44]	369812	1		T1	5		T2	57		T4	1342
valid_sources[0x45]	370123	1		T1	7		T2	88		T4	1457
valid_sources[0x46]	371004	1		T1	10		T2	67		T4	1380
valid_sources[0x47]	372032	1		T1	3		T2	73		T4	1369
valid_sources[0x48]	420406	1		T1	12		T2	52		T4	1435
valid_sources[0x49]	370324	1		T1	13		T2	77		T4	1391
valid_sources[0x4a]	368923	1		T1	4		T2	85		T4	1393
valid_sources[0x4b]	369556	1		T1	10		T2	32		T4	1438
valid_sources[0x4c]	370243	1		T1	14		T2	109		T4	1291
valid_sources[0x4d]	371163	1		T1	14		T2	85		T4	1473
valid_sources[0x4e]	370915	1		T1	4		T2	85		T4	1434
valid_sources[0x4f]	2797165	1		T1	6		T2	51		T4	1380
valid_sources[0x50]	371462	1		T1	7		T2	165		T4	1307
valid_sources[0x51]	369758	1		T1	5		T2	92		T4	1460
valid_sources[0x52]	371341	1		T1	3		T2	81		T4	1418
valid_sources[0x53]	368485	1		T1	8		T2	91		T4	1364
valid_sources[0x54]	661354	1		T1	14		T2	96		T4	1391
valid_sources[0x55]	370336	1		T1	11		T2	68		T4	1395
valid_sources[0x56]	370794	1		T1	5		T2	123		T4	1395
valid_sources[0x57]	369674	1		T1	11		T2	69		T4	1346
valid_sources[0x58]	516759	1		T1	1		T2	110		T4	1435
valid_sources[0x59]	414065	1		T1	10		T2	86		T4	1418
valid_sources[0x5a]	369534	1		T1	4		T2	66		T4	1400
valid_sources[0x5b]	367637	1		T1	9		T2	92		T4	1361
valid_sources[0x5c]	371855	1		T1	6		T2	65		T4	1357
valid_sources[0x5d]	369332	1		T1	2		T2	27		T4	1423
valid_sources[0x5e]	380027	1		T1	10		T2	49		T4	1435
valid_sources[0x5f]	368452	1		T1	4		T2	111		T4	1474
valid_sources[0x60]	2091375	1		T1	4		T2	137		T4	1327
valid_sources[0x61]	2357534	1		T1	9		T2	43		T4	1383
valid_sources[0x62]	741054	1		T1	7		T2	86		T4	1468
valid_sources[0x63]	427822	1		T1	9		T2	69		T4	1486
valid_sources[0x64]	368343	1		T1	9		T2	79		T4	1356
valid_sources[0x65]	368460	1		T1	5		T2	124		T4	1378
valid_sources[0x66]	371181	1		T1	3		T2	132		T4	1368
valid_sources[0x67]	368721	1		T2	90		T4	1354		T5	381
valid_sources[0x68]	369403	1		T1	9		T2	60		T4	1408
valid_sources[0x69]	369717	1		T1	4		T2	60		T4	1433
valid_sources[0x6a]	369308	1		T1	7		T2	54		T4	1462
valid_sources[0x6b]	369634	1		T1	6		T2	96		T4	1399
valid_sources[0x6c]	369680	1		T1	8		T2	101		T4	1454
valid_sources[0x6d]	370886	1		T1	5		T2	108		T4	1452
valid_sources[0x6e]	368204	1		T1	1		T2	41		T4	1354
valid_sources[0x6f]	372569	1		T1	6		T2	60		T4	1404
valid_sources[0x70]	369416	1		T1	1		T2	90		T4	1339
valid_sources[0x71]	366306	1		T1	4		T2	136		T4	1470
valid_sources[0x72]	370781	1		T1	4		T2	54		T4	1399
valid_sources[0x73]	369445	1		T1	1		T2	69		T4	1470
valid_sources[0x74]	367164	1		T1	5		T2	69		T4	1426
valid_sources[0x75]	377295	1		T1	13		T2	80		T4	1376
valid_sources[0x76]	370422	1		T1	11		T2	129		T4	1447
valid_sources[0x77]	369340	1		T1	18		T2	46		T4	1434
valid_sources[0x78]	367293	1		T1	10		T2	65		T4	1445
valid_sources[0x79]	366403	1		T1	3		T2	74		T4	1420
valid_sources[0x7a]	395324	1		T1	1		T2	99		T4	1418
valid_sources[0x7b]	371692	1		T1	10		T2	77		T4	1349
valid_sources[0x7c]	369150	1		T1	15		T2	79		T4	1420
valid_sources[0x7d]	370791	1		T1	7		T2	77		T4	1412
valid_sources[0x7e]	368575	1		T1	13		T2	86		T4	1320
valid_sources[0x7f]	369456	1		T1	8		T2	104		T4	1382
valid_sources[0x80]	369246	1		T1	3		T2	133		T4	1425

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62333281

1

T1

857

T2

11296

T3

6682

values[0x0]

all_enables

biggest_size

484562

1

T1

3

T2

12

T3

14

values[0x1]

all_enables

biggest_size

483082

1

T1

6

T2

5

T3

8