Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1677281	0	0
cfg0_rd_A	2147483647	3395	0	0
compare_lower0_0_rd_A	2147483647	3452	0	0
compare_upper0_0_rd_A	2147483647	3022	0	0
ctrl_rd_A	2147483647	3121	0	0
intr_enable0_rd_A	2147483647	4352	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1677281	0	0
T7	403392	95961	0	0
T8	313381	0	0	0
T9	341323	0	0	0
T10	334307	0	0	0
T11	233584	0	0	0
T12	343603	146871	0	0
T13	0	163364	0	0
T34	0	149855	0	0
T35	0	53135	0	0
T36	0	82760	0	0
T37	0	365667	0	0
T38	0	48811	0	0
T39	0	223242	0	0
T40	0	113754	0	0
T41	5754	0	0	0
T42	128259	0	0	0
T43	909971	0	0	0
T44	683071	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3395	0	0
T13	646514	1664	0	0
T29	0	34	0	0
T30	0	97	0	0
T35	0	586	0	0
T45	0	17	0	0
T46	0	23	0	0
T47	0	10	0	0
T48	0	169	0	0
T49	0	17	0	0
T50	0	4	0	0
T51	751868	0	0	0
T52	134598	0	0	0
T53	762893	0	0	0
T54	289375	0	0	0
T55	954666	0	0	0
T56	190192	0	0	0
T57	502345	0	0	0
T58	140153	0	0	0
T59	452678	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3452	0	0
T13	646514	1917	0	0
T29	0	63	0	0
T30	0	71	0	0
T35	0	647	0	0
T45	0	15	0	0
T46	0	39	0	0
T47	0	9	0	0
T48	0	123	0	0
T49	0	56	0	0
T50	0	21	0	0
T51	751868	0	0	0
T52	134598	0	0	0
T53	762893	0	0	0
T54	289375	0	0	0
T55	954666	0	0	0
T56	190192	0	0	0
T57	502345	0	0	0
T58	140153	0	0	0
T59	452678	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3022	0	0
T13	646514	1543	0	0
T29	0	47	0	0
T30	0	86	0	0
T35	0	632	0	0
T46	0	34	0	0
T47	0	6	0	0
T48	0	91	0	0
T49	0	50	0	0
T50	0	8	0	0
T51	751868	0	0	0
T52	134598	0	0	0
T53	762893	0	0	0
T54	289375	0	0	0
T55	954666	0	0	0
T56	190192	0	0	0
T57	502345	0	0	0
T58	140153	0	0	0
T59	452678	0	0	0
T60	0	8	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3121	0	0
T13	646514	1627	0	0
T29	0	29	0	0
T30	0	79	0	0
T35	0	539	0	0
T45	0	14	0	0
T47	0	9	0	0
T48	0	116	0	0
T49	0	63	0	0
T50	0	2	0	0
T51	751868	0	0	0
T52	134598	0	0	0
T53	762893	0	0	0
T54	289375	0	0	0
T55	954666	0	0	0
T56	190192	0	0	0
T57	502345	0	0	0
T58	140153	0	0	0
T59	452678	0	0	0
T60	0	3	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4352	0	0
T13	0	2090	0	0
T20	495846	22	0	0
T21	176426	0	0	0
T22	574670	0	0	0
T23	265906	31	0	0
T24	397926	0	0	0
T25	177180	0	0	0
T26	249979	0	0	0
T27	202222	0	0	0
T35	0	625	0	0
T61	0	83	0	0
T62	0	36	0	0
T63	0	2	0	0
T64	0	22	0	0
T65	0	8	0	0
T66	0	27	0	0
T67	222029	0	0	0
T68	241850	0	0	0