Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2065875	0	0
cfg0_rd_A	2147483647	2476	0	0
compare_lower0_0_rd_A	2147483647	2545	0	0
compare_upper0_0_rd_A	2147483647	2529	0	0
ctrl_rd_A	2147483647	2593	0	0
intr_enable0_rd_A	2147483647	3241	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2065875	0	0
T11	149411	44041	0	0
T12	0	25413	0	0
T13	0	417253	0	0
T34	0	197597	0	0
T35	0	24609	0	0
T36	0	647770	0	0
T37	0	40736	0	0
T38	0	411708	0	0
T39	0	79032	0	0
T40	0	74807	0	0
T41	248668	0	0	0
T42	681871	0	0	0
T43	545848	0	0	0
T44	112346	0	0	0
T45	490599	0	0	0
T46	150220	0	0	0
T47	193015	0	0	0
T48	106996	0	0	0
T49	488848	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2476	0	0
T12	992506	227	0	0
T13	142938	0	0	0
T27	0	43	0	0
T29	0	22	0	0
T30	0	40	0	0
T35	0	115	0	0
T50	0	14	0	0
T51	0	10	0	0
T52	0	654	0	0
T53	0	23	0	0
T54	0	126	0	0
T55	389775	0	0	0
T56	282547	0	0	0
T57	703247	0	0	0
T58	166084	0	0	0
T59	156242	0	0	0
T60	114134	0	0	0
T61	595210	0	0	0
T62	149839	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2545	0	0
T12	992506	297	0	0
T13	142938	0	0	0
T27	0	28	0	0
T29	0	13	0	0
T30	0	33	0	0
T35	0	125	0	0
T50	0	8	0	0
T51	0	9	0	0
T52	0	638	0	0
T53	0	12	0	0
T55	389775	0	0	0
T56	282547	0	0	0
T57	703247	0	0	0
T58	166084	0	0	0
T59	156242	0	0	0
T60	114134	0	0	0
T61	595210	0	0	0
T62	149839	0	0	0
T63	0	14	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2529	0	0
T12	992506	188	0	0
T13	142938	0	0	0
T27	0	9	0	0
T29	0	13	0	0
T30	0	34	0	0
T35	0	181	0	0
T50	0	3	0	0
T51	0	3	0	0
T52	0	698	0	0
T53	0	13	0	0
T54	0	157	0	0
T55	389775	0	0	0
T56	282547	0	0	0
T57	703247	0	0	0
T58	166084	0	0	0
T59	156242	0	0	0
T60	114134	0	0	0
T61	595210	0	0	0
T62	149839	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2593	0	0
T12	992506	209	0	0
T13	142938	0	0	0
T27	0	25	0	0
T29	0	13	0	0
T30	0	32	0	0
T35	0	105	0	0
T50	0	29	0	0
T51	0	3	0	0
T52	0	708	0	0
T53	0	14	0	0
T55	389775	0	0	0
T56	282547	0	0	0
T57	703247	0	0	0
T58	166084	0	0	0
T59	156242	0	0	0
T60	114134	0	0	0
T61	595210	0	0	0
T62	149839	0	0	0
T63	0	19	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3241	0	0
T12	992506	286	0	0
T13	142938	0	0	0
T35	0	205	0	0
T55	389775	0	0	0
T56	282547	0	0	0
T57	703247	0	0	0
T58	166084	0	0	0
T59	156242	0	0	0
T60	114134	0	0	0
T61	595210	0	0	0
T62	149839	0	0	0
T64	0	92	0	0
T65	0	94	0	0
T66	0	63	0	0
T67	0	24	0	0
T68	0	24	0	0
T69	0	56	0	0
T70	0	41	0	0
T71	0	85	0	0