Line Coverage for Module :
rv_timer
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 57 | 1 | 1 | 100.00 |
CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 63 | 1 | 1 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
CONT_ASSIGN | 73 | 1 | 1 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer.sv' or '../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
66 |
1 |
1 |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
132 |
1 |
1 |
Cond Coverage for Module :
rv_timer
| Total | Covered | Percent |
Conditions | 12 | 10 | 83.33 |
Logical | 12 | 10 | 83.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 66
EXPRESSION (reg2hw.compare_upper0_0.qe | reg2hw.compare_lower0_0.qe)
-------------1------------ -------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 73
EXPRESSION (intr_timer_state_de | mtimecmp_update[0][0])
---------1--------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 74
EXPRESSION (intr_timer_state_d & ((~mtimecmp_update[0][0])))
---------1-------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 132
SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Not Covered | |
Toggle Coverage for Module :
rv_timer
| Total | Covered | Percent |
Totals |
27 |
27 |
100.00 |
Total Bits |
334 |
334 |
100.00 |
Total Bits 0->1 |
167 |
167 |
100.00 |
Total Bits 1->0 |
167 |
167 |
100.00 |
| | | |
Ports |
27 |
27 |
100.00 |
Port Bits |
334 |
334 |
100.00 |
Port Bits 0->1 |
167 |
167 |
100.00 |
Port Bits 1->0 |
167 |
167 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T6,T8,T9 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T1,T2,T6 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_source[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T11,T12,T13 |
Yes |
T11,T12,T13 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_source[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T8,T14,T15 |
Yes |
T8,T14,T15 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T8,T14,T15 |
Yes |
T8,T14,T15 |
OUTPUT |
intr_timer_expired_hart0_timer0_o |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
*Tests covering at least one bit in the range
Assert Coverage for Module :
rv_timer
Assertion Details
AlertsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
102077 |
102077 |
0 |
0 |
T2 |
179006 |
179005 |
0 |
0 |
T3 |
134318 |
134317 |
0 |
0 |
T4 |
209383 |
209382 |
0 |
0 |
T5 |
530588 |
530579 |
0 |
0 |
T6 |
106301 |
106300 |
0 |
0 |
T7 |
507839 |
507762 |
0 |
0 |
T8 |
3798 |
2945 |
0 |
0 |
T9 |
990732 |
990714 |
0 |
0 |
T10 |
582609 |
582600 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
100 |
0 |
0 |
T8 |
3798 |
10 |
0 |
0 |
T9 |
990732 |
0 |
0 |
0 |
T10 |
582609 |
0 |
0 |
0 |
T14 |
0 |
20 |
0 |
0 |
T15 |
0 |
30 |
0 |
0 |
T16 |
0 |
20 |
0 |
0 |
T17 |
0 |
20 |
0 |
0 |
T18 |
12771 |
0 |
0 |
0 |
T19 |
478903 |
0 |
0 |
0 |
T20 |
115346 |
0 |
0 |
0 |
T21 |
101576 |
0 |
0 |
0 |
T22 |
22569 |
0 |
0 |
0 |
T23 |
354774 |
0 |
0 |
0 |
T24 |
284676 |
0 |
0 |
0 |
IntrTimerExpiredHart0Timer0Known
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
102077 |
102077 |
0 |
0 |
T2 |
179006 |
179005 |
0 |
0 |
T3 |
134318 |
134317 |
0 |
0 |
T4 |
209383 |
209382 |
0 |
0 |
T5 |
530588 |
530579 |
0 |
0 |
T6 |
106301 |
106300 |
0 |
0 |
T7 |
507839 |
507762 |
0 |
0 |
T8 |
3798 |
2945 |
0 |
0 |
T9 |
990732 |
990714 |
0 |
0 |
T10 |
582609 |
582600 |
0 |
0 |
TlOAReadyKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
102077 |
102077 |
0 |
0 |
T2 |
179006 |
179005 |
0 |
0 |
T3 |
134318 |
134317 |
0 |
0 |
T4 |
209383 |
209382 |
0 |
0 |
T5 |
530588 |
530579 |
0 |
0 |
T6 |
106301 |
106300 |
0 |
0 |
T7 |
507839 |
507762 |
0 |
0 |
T8 |
3798 |
2945 |
0 |
0 |
T9 |
990732 |
990714 |
0 |
0 |
T10 |
582609 |
582600 |
0 |
0 |
TlODValidKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
102077 |
102077 |
0 |
0 |
T2 |
179006 |
179005 |
0 |
0 |
T3 |
134318 |
134317 |
0 |
0 |
T4 |
209383 |
209382 |
0 |
0 |
T5 |
530588 |
530579 |
0 |
0 |
T6 |
106301 |
106300 |
0 |
0 |
T7 |
507839 |
507762 |
0 |
0 |
T8 |
3798 |
2945 |
0 |
0 |
T9 |
990732 |
990714 |
0 |
0 |
T10 |
582609 |
582600 |
0 |
0 |