Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	126487	0	0
cfg0_rd_A	2147483647	1579	0	0
compare_lower0_0_rd_A	2147483647	1539	0	0
compare_upper0_0_rd_A	2147483647	1339	0	0
ctrl_rd_A	2147483647	1398	0	0
intr_enable0_rd_A	2147483647	2393	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	126487	0	0
T1	101290	2942	0	0
T2	437042	0	0	0
T3	5744	0	0	0
T4	7414	0	0	0
T5	143251	0	0	0
T6	3099	0	0	0
T7	245567	0	0	0
T8	4183	0	0	0
T9	109951	0	0	0
T10	886771	0	0	0
T12	0	7469	0	0
T14	0	5521	0	0
T25	0	17235	0	0
T26	0	12306	0	0
T27	0	5808	0	0
T28	0	5971	0	0
T29	0	8701	0	0
T30	0	3300	0	0
T31	0	3965	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1579	0	0
T1	101290	31	0	0
T2	437042	0	0	0
T3	5744	0	0	0
T4	7414	0	0	0
T5	143251	0	0	0
T6	3099	0	0	0
T7	245567	0	0	0
T8	4183	0	0	0
T9	109951	0	0	0
T10	886771	0	0	0
T12	0	145	0	0
T14	0	53	0	0
T20	0	98	0	0
T23	0	4	0	0
T29	0	132	0	0
T32	0	71	0	0
T33	0	11	0	0
T34	0	200	0	0
T35	0	2	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1539	0	0
T1	101290	35	0	0
T2	437042	0	0	0
T3	5744	0	0	0
T4	7414	0	0	0
T5	143251	0	0	0
T6	3099	0	0	0
T7	245567	0	0	0
T8	4183	0	0	0
T9	109951	0	0	0
T10	886771	0	0	0
T12	0	165	0	0
T14	0	74	0	0
T20	0	73	0	0
T23	0	8	0	0
T29	0	171	0	0
T32	0	59	0	0
T33	0	25	0	0
T34	0	226	0	0
T35	0	5	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1339	0	0
T1	101290	37	0	0
T2	437042	0	0	0
T3	5744	0	0	0
T4	7414	0	0	0
T5	143251	0	0	0
T6	3099	0	0	0
T7	245567	0	0	0
T8	4183	0	0	0
T9	109951	0	0	0
T10	886771	0	0	0
T12	0	66	0	0
T14	0	32	0	0
T20	0	81	0	0
T29	0	143	0	0
T32	0	48	0	0
T33	0	8	0	0
T34	0	226	0	0
T35	0	10	0	0
T36	0	6	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1398	0	0
T1	101290	39	0	0
T2	437042	0	0	0
T3	5744	0	0	0
T4	7414	0	0	0
T5	143251	0	0	0
T6	3099	0	0	0
T7	245567	0	0	0
T8	4183	0	0	0
T9	109951	0	0	0
T10	886771	0	0	0
T12	0	87	0	0
T14	0	55	0	0
T20	0	86	0	0
T23	0	7	0	0
T29	0	105	0	0
T32	0	81	0	0
T33	0	12	0	0
T34	0	226	0	0
T35	0	4	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2393	0	0
T1	101290	100	0	0
T2	437042	0	0	0
T3	5744	0	0	0
T4	7414	0	0	0
T5	143251	0	0	0
T6	3099	0	0	0
T7	245567	0	0	0
T8	4183	0	0	0
T9	109951	0	0	0
T10	886771	0	0	0
T11	0	33	0	0
T12	0	241	0	0
T14	0	92	0	0
T29	0	240	0	0
T37	0	26	0	0
T38	0	36	0	0
T39	0	28	0	0
T40	0	79	0	0
T41	0	46	0	0