Unified Coverage Report :: Module :: rv_timer

Module : rv_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	95.83	100.00	83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.68	99.36	99.04	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_harts[0].u_core	100.00	100.00	100.00			100.00
gen_harts[0].u_intr_hw	100.00	100.00	100.00			100.00	100.00
rv_timer_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_reg	99.78	99.24	99.64	100.00		100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_timer

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

55                        // be connected manually.
56         1/1            assign active[0]  = reg2hw.ctrl[0].q;
           Tests:       T1 T2 T3 
57         1/1            assign prescaler = '{reg2hw.cfg0.prescale.q};
           Tests:       T1 T2 T3 
58         1/1            assign step      = '{reg2hw.cfg0.step.q};
           Tests:       T1 T2 T3 
59                      
60         1/1            assign hw2reg.timer_v_upper0.de = tick[0];
           Tests:       T1 T2 T3 
61         1/1            assign hw2reg.timer_v_lower0.de = tick[0];
           Tests:       T1 T2 T3 
62         1/1            assign hw2reg.timer_v_upper0.d = mtime_d[0][63:32];
           Tests:       T1 T2 T3 
63         1/1            assign hw2reg.timer_v_lower0.d = mtime_d[0][31: 0];
           Tests:       T1 T2 T3 
64         1/1            assign mtime[0] = {reg2hw.timer_v_upper0.q, reg2hw.timer_v_lower0.q};
           Tests:       T1 T2 T3 
65         1/1            assign mtimecmp = '{'{{reg2hw.compare_upper0_0.q,reg2hw.compare_lower0_0.q}}};
           Tests:       T1 T2 T3 
66         1/1            assign mtimecmp_update[0][0] = reg2hw.compare_upper0_0.qe | reg2hw.compare_lower0_0.qe;
           Tests:       T1 T2 T3 
67                      
68         1/1            assign intr_timer_expired_hart0_timer0_o = intr_out[0];
           Tests:       T1 T2 T3 
69         1/1            assign intr_timer_en            = reg2hw.intr_enable0[0].q;
           Tests:       T1 T2 T3 
70         1/1            assign intr_timer_state_q       = reg2hw.intr_state0[0].q;
           Tests:       T1 T2 T3 
71         1/1            assign intr_timer_test_q        = reg2hw.intr_test0[0].q;
           Tests:       T1 T2 T3 
72         1/1            assign intr_timer_test_qe       = reg2hw.intr_test0[0].qe;
           Tests:       T1 T11 T12 
73         1/1            assign hw2reg.intr_state0[0].de = intr_timer_state_de | mtimecmp_update[0][0];
           Tests:       T1 T2 T3 
74         1/1            assign hw2reg.intr_state0[0].d  = intr_timer_state_d & ~mtimecmp_update[0][0];
           Tests:       T1 T2 T3 
75                      
76                      
77                        for (genvar h = 0 ; h < N_HARTS ; h++) begin : gen_harts
78                          prim_intr_hw #(
79                            .Width(N_TIMERS)
80                          ) u_intr_hw (
81                            .clk_i,
82                            .rst_ni,
83                            .event_intr_i           (intr_timer_set),
84                      
85                            .reg2hw_intr_enable_q_i (intr_timer_en[h*N_TIMERS+:N_TIMERS]),
86                            .reg2hw_intr_test_q_i   (intr_timer_test_q[h*N_TIMERS+:N_TIMERS]),
87                            .reg2hw_intr_test_qe_i  (intr_timer_test_qe[h]),
88                            .reg2hw_intr_state_q_i  (intr_timer_state_q[h*N_TIMERS+:N_TIMERS]),
89                            .hw2reg_intr_state_de_o (intr_timer_state_de),
90                            .hw2reg_intr_state_d_o  (intr_timer_state_d[h*N_TIMERS+:N_TIMERS]),
91                      
92                            .intr_o                 (intr_out[h*N_TIMERS+:N_TIMERS])
93                          );
94                      
95                          timer_core #(
96                            .N (N_TIMERS)
97                          ) u_core (
98                            .clk_i,
99                            .rst_ni,
100                     
101                           .active    (active[h]),
102                           .prescaler (prescaler[h]),
103                           .step      (step[h]),
104                     
105                           .tick      (tick[h]),
106                     
107                           .mtime_d   (mtime_d[h]),
108                           .mtime     (mtime[h]),
109                           .mtimecmp  (mtimecmp[h]),
110                     
111                           .intr      (intr_timer_set[h*N_TIMERS+:N_TIMERS])
112                         );
113                       end : gen_harts
114                     
115                       // Register module
116                       logic [NumAlerts-1:0] alert_test, alerts;
117                       rv_timer_reg_top u_reg (
118                         .clk_i,
119                         .rst_ni,
120                     
121                         .tl_i,
122                         .tl_o,
123                     
124                         .reg2hw,
125                         .hw2reg,
126                     
127                         // SEC_CM: BUS.INTEGRITY
128                         .intg_err_o (alerts[0])
129                       );
130                     
131                       // Alerts
132        1/1            assign alert_test = {
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : rv_timer

	Total	Covered	Percent
Conditions	12	10	83.33
Logical	12	10	83.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (reg2hw.compare_upper0_0.qe | reg2hw.compare_lower0_0.qe)
             -------------1------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       73
 EXPRESSION (intr_timer_state_de | mtimecmp_update[0][0])
             ---------1---------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T7,T9

 LINE       74
 EXPRESSION (intr_timer_state_d & ((~mtimecmp_update[0][0])))
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T13
1	1	Covered	T1,T7,T9

 LINE       132
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Not Covered

---

Toggle Coverage for Module : rv_timer

	Total	Covered	Percent
Totals	27	27	100.00
Total Bits	334	334	100.00
Total Bits 0->1	167	167	100.00
Total Bits 1->0	167	167	100.00

Ports	27	27	100.00
Port Bits	334	334	100.00
Port Bits 0->1	167	167	100.00
Port Bits 1->0	167	167	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T1,T12,T14	Yes	T1,T12,T14	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T5,T7	Yes	T1,T5,T7	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T5	Yes	T1,T2,T5	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T4	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T7	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
intr_timer_expired_hart0_timer0_o	Yes	Yes	T7,T9,T15	Yes	T7,T9,T15	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : rv_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	2147483647	2147483647	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	100	0	0
IntrTimerExpiredHart0Timer0Known	2147483647	2147483647	0	0
TlOAReadyKnown	2147483647	2147483647	0	0
TlODValidKnown	2147483647	2147483647	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	101290	101161	0	0
T2	437042	436685	0	0
T3	5744	4022	0	0
T4	7414	5205	0	0
T5	143251	143244	0	0
T6	3099	2281	0	0
T7	245567	245557	0	0
T8	4183	3375	0	0
T9	109951	109950	0	0
T10	886771	886695	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	100	0	0
T3	5744	20	0	0
T4	7414	30	0	0
T5	143251	0	0	0
T6	3099	10	0	0
T7	245567	0	0	0
T8	4183	10	0	0
T9	109951	0	0	0
T10	886771	0	0	0
T13	135519	0	0	0
T16	0	30	0	0
T17	439233	0	0	0

IntrTimerExpiredHart0Timer0Known

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	101290	101161	0	0
T2	437042	436685	0	0
T3	5744	4022	0	0
T4	7414	5205	0	0
T5	143251	143244	0	0
T6	3099	2281	0	0
T7	245567	245557	0	0
T8	4183	3375	0	0
T9	109951	109950	0	0
T10	886771	886695	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	101290	101161	0	0
T2	437042	436685	0	0
T3	5744	4022	0	0
T4	7414	5205	0	0
T5	143251	143244	0	0
T6	3099	2281	0	0
T7	245567	245557	0	0
T8	4183	3375	0	0
T9	109951	109950	0	0
T10	886771	886695	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	101290	101161	0	0
T2	437042	436685	0	0
T3	5744	4022	0	0
T4	7414	5205	0	0
T5	143251	143244	0	0
T6	3099	2281	0	0
T7	245567	245557	0	0
T8	4183	3375	0	0
T9	109951	109950	0	0
T10	886771	886695	0	0