Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	119893	0	0
cfg0_rd_A	2147483647	1860	0	0
compare_lower0_0_rd_A	2147483647	1618	0	0
compare_upper0_0_rd_A	2147483647	1756	0	0
ctrl_rd_A	2147483647	1488	0	0
intr_enable0_rd_A	2147483647	2965	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	119893	0	0
T12	220830	5832	0	0
T13	420624	0	0	0
T14	365345	11354	0	0
T15	0	11091	0	0
T18	6713	0	0	0
T25	0	2707	0	0
T26	0	4587	0	0
T27	0	4090	0	0
T28	0	6530	0	0
T29	0	9132	0	0
T30	0	6068	0	0
T31	0	8751	0	0
T32	110332	0	0	0
T33	962051	0	0	0
T34	162869	0	0	0
T35	194648	0	0	0
T36	809799	0	0	0
T37	617299	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1860	0	0
T12	220830	86	0	0
T13	420624	0	0	0
T14	365345	0	0	0
T18	6713	0	0	0
T20	0	55	0	0
T25	0	44	0	0
T28	0	51	0	0
T29	0	153	0	0
T32	110332	0	0	0
T33	962051	0	0	0
T34	162869	0	0	0
T35	194648	0	0	0
T36	809799	0	0	0
T37	617299	0	0	0
T38	0	86	0	0
T39	0	2	0	0
T40	0	15	0	0
T41	0	445	0	0
T42	0	141	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1618	0	0
T12	220830	72	0	0
T13	420624	0	0	0
T14	365345	0	0	0
T18	6713	0	0	0
T20	0	38	0	0
T25	0	60	0	0
T28	0	89	0	0
T29	0	145	0	0
T32	110332	0	0	0
T33	962051	0	0	0
T34	162869	0	0	0
T35	194648	0	0	0
T36	809799	0	0	0
T37	617299	0	0	0
T38	0	110	0	0
T39	0	3	0	0
T40	0	8	0	0
T41	0	400	0	0
T43	0	41	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1756	0	0
T12	220830	96	0	0
T13	420624	0	0	0
T14	365345	0	0	0
T18	6713	0	0	0
T20	0	36	0	0
T25	0	22	0	0
T28	0	85	0	0
T29	0	171	0	0
T32	110332	0	0	0
T33	962051	0	0	0
T34	162869	0	0	0
T35	194648	0	0	0
T36	809799	0	0	0
T37	617299	0	0	0
T38	0	118	0	0
T40	0	10	0	0
T41	0	477	0	0
T42	0	90	0	0
T43	0	18	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1488	0	0
T12	220830	44	0	0
T13	420624	0	0	0
T14	365345	0	0	0
T18	6713	0	0	0
T20	0	42	0	0
T25	0	56	0	0
T28	0	63	0	0
T29	0	128	0	0
T32	110332	0	0	0
T33	962051	0	0	0
T34	162869	0	0	0
T35	194648	0	0	0
T36	809799	0	0	0
T37	617299	0	0	0
T38	0	83	0	0
T40	0	2	0	0
T41	0	405	0	0
T42	0	70	0	0
T43	0	9	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2965	0	0
T11	3286	22	0	0
T12	220830	215	0	0
T16	5563	0	0	0
T17	3322	0	0	0
T25	0	57	0	0
T28	0	172	0	0
T29	0	234	0	0
T38	0	155	0	0
T44	0	21	0	0
T45	0	83	0	0
T46	0	23	0	0
T47	0	51	0	0
T48	390836	0	0	0
T49	431245	0	0	0
T50	101535	0	0	0
T51	361362	0	0	0
T52	117161	0	0	0
T53	13632	0	0	0