Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
129135288 |
1 |
|
T1 |
1377 |
|
T2 |
202385 |
|
T3 |
13401 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
65001574 |
1 |
|
T1 |
1204 |
|
T2 |
167363 |
|
T3 |
6 |
auto[1] |
64133714 |
1 |
|
T1 |
173 |
|
T2 |
35022 |
|
T3 |
13395 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
129126848 |
1 |
|
T1 |
1359 |
|
T2 |
202348 |
|
T3 |
13399 |
auto[1] |
8440 |
1 |
|
T1 |
18 |
|
T2 |
37 |
|
T3 |
2 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
64997382 |
1 |
|
T1 |
1191 |
|
T2 |
167354 |
|
T3 |
6 |
all_values[0] |
auto[0] |
auto[1] |
4192 |
1 |
|
T1 |
13 |
|
T2 |
9 |
|
T4 |
5 |
all_values[0] |
auto[1] |
auto[0] |
64129466 |
1 |
|
T1 |
168 |
|
T2 |
34994 |
|
T3 |
13393 |
all_values[0] |
auto[1] |
auto[1] |
4248 |
1 |
|
T1 |
5 |
|
T2 |
28 |
|
T3 |
2 |