| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.61 | 99.36 | 98.73 | 100.00 | 100.00 | 100.00 | 99.55 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74.04 | 74.04 | 96.50 | 96.50 | 74.84 | 74.84 | 63.31 | 63.31 | 96.55 | 96.55 | 93.55 | 93.55 | 19.48 | 19.48 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/22.rv_timer_cfg_update_on_fly.2876678722 | ||
| 81.75 | 7.71 | 96.50 | 0.00 | 85.67 | 10.83 | 95.35 | 32.04 | 96.55 | 0.00 | 93.55 | 0.00 | 22.88 | 3.40 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/4.rv_timer_cfg_update_on_fly.3572812109 | ||
| 85.78 | 4.03 | 99.04 | 2.55 | 95.86 | 10.19 | 96.64 | 1.29 | 98.28 | 1.72 | 96.77 | 3.23 | 28.09 | 5.21 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all_with_rand_reset.4255416841 | ||
| 86.96 | 1.18 | 99.36 | 0.32 | 96.82 | 0.96 | 99.74 | 3.10 | 100.00 | 1.72 | 97.10 | 0.32 | 28.77 | 0.68 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/2.rv_timer_sec_cm.3686136886 | ||
| 87.72 | 0.76 | 99.36 | 0.00 | 96.82 | 0.00 | 99.74 | 0.00 | 100.00 | 0.00 | 97.10 | 0.00 | 33.30 | 4.53 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/24.rv_timer_stress_all.2670918439 | ||
| 88.42 | 0.70 | 99.36 | 0.00 | 96.82 | 0.00 | 99.74 | 0.00 | 100.00 | 0.00 | 97.10 | 0.00 | 37.49 | 4.19 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/5.rv_timer_random.1476514725 | ||
| 89.06 | 0.64 | 99.36 | 0.00 | 96.82 | 0.00 | 99.74 | 0.00 | 100.00 | 0.00 | 97.10 | 0.00 | 41.34 | 3.85 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all.2178505435 | ||
| 89.64 | 0.59 | 99.36 | 0.00 | 96.82 | 0.00 | 99.74 | 0.00 | 100.00 | 0.00 | 97.10 | 0.00 | 44.85 | 3.51 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all.3166691865 | ||
| 90.17 | 0.53 | 99.36 | 0.00 | 96.82 | 0.00 | 99.74 | 0.00 | 100.00 | 0.00 | 97.10 | 0.00 | 48.02 | 3.17 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all.3650386653 | ||
| 90.70 | 0.53 | 99.36 | 0.00 | 96.82 | 0.00 | 99.74 | 0.00 | 100.00 | 0.00 | 97.10 | 0.00 | 51.19 | 3.17 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all.3810912501 | ||
| 91.17 | 0.47 | 99.36 | 0.00 | 97.13 | 0.32 | 100.00 | 0.26 | 100.00 | 0.00 | 99.35 | 2.26 | 51.19 | 0.00 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4117767556 | ||
| 91.64 | 0.47 | 99.36 | 0.00 | 97.45 | 0.32 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 53.68 | 2.49 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/1.rv_timer_random.3573493399 | ||
| 92.08 | 0.43 | 99.36 | 0.00 | 97.45 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 56.29 | 2.60 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all.2185426799 | ||
| 92.49 | 0.42 | 99.36 | 0.00 | 97.45 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 58.78 | 2.49 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all.3961258810 | ||
| 92.85 | 0.36 | 99.36 | 0.00 | 97.45 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 60.93 | 2.15 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/33.rv_timer_random.1883923884 | ||
| 93.17 | 0.32 | 99.36 | 0.00 | 97.45 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 62.85 | 1.93 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/6.rv_timer_stress_all.1196681231 | ||
| 93.48 | 0.31 | 99.36 | 0.00 | 98.41 | 0.96 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 63.76 | 0.91 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1767961650 | ||
| 93.78 | 0.30 | 99.36 | 0.00 | 98.41 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 65.57 | 1.81 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all.619824984 | ||
| 94.05 | 0.26 | 99.36 | 0.00 | 98.41 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 67.16 | 1.59 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all.2189854612 | ||
| 94.27 | 0.23 | 99.36 | 0.00 | 98.41 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 68.52 | 1.36 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all.700538117 | ||
| 94.48 | 0.21 | 99.36 | 0.00 | 98.41 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 69.76 | 1.25 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all.1178919619 | ||
| 94.69 | 0.21 | 99.36 | 0.00 | 98.41 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 71.01 | 1.25 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all.2878713718 | ||
| 94.90 | 0.21 | 99.36 | 0.00 | 98.41 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 72.25 | 1.25 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all.2062753041 | ||
| 95.08 | 0.19 | 99.36 | 0.00 | 98.73 | 0.32 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 73.05 | 0.79 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/4.rv_timer_random_reset.2877320515 | ||
| 95.25 | 0.17 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 74.07 | 1.02 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/15.rv_timer_random.894186137 | ||
| 95.42 | 0.17 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 75.08 | 1.02 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/25.rv_timer_random.3076784470 | ||
| 95.59 | 0.17 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 76.10 | 1.02 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all.1118125631 | ||
| 95.74 | 0.15 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 77.01 | 0.91 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/33.rv_timer_random_reset.3573704117 | ||
| 95.89 | 0.15 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 77.92 | 0.91 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all.3021787738 | ||
| 96.03 | 0.13 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 78.71 | 0.79 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all.1701145087 | ||
| 96.14 | 0.11 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 79.39 | 0.68 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/143.rv_timer_random.3075039199 | ||
| 96.25 | 0.11 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 80.07 | 0.68 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/191.rv_timer_random.32701539 | ||
| 96.37 | 0.11 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 80.75 | 0.68 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/192.rv_timer_random.412845919 | ||
| 96.48 | 0.11 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 81.43 | 0.68 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/24.rv_timer_random.3427133759 | ||
| 96.57 | 0.09 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 81.99 | 0.57 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/106.rv_timer_random.3503848252 | ||
| 96.67 | 0.09 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 82.56 | 0.57 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/116.rv_timer_random.3630526839 | ||
| 96.76 | 0.09 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 83.13 | 0.57 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/144.rv_timer_random.877749558 | ||
| 96.86 | 0.09 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 83.69 | 0.57 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/152.rv_timer_random.2027185115 | ||
| 96.95 | 0.09 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 84.26 | 0.57 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/189.rv_timer_random.3863743495 | ||
| 97.04 | 0.09 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 84.82 | 0.57 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/194.rv_timer_random.3875576009 | ||
| 97.14 | 0.09 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 85.39 | 0.57 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all.3082922607 | ||
| 97.23 | 0.09 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 85.96 | 0.57 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/3.rv_timer_cfg_update_on_fly.880833308 | ||
| 97.33 | 0.09 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 86.52 | 0.57 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all.3727672420 | ||
| 97.42 | 0.09 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 87.09 | 0.57 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/43.rv_timer_random.3810929311 | ||
| 97.52 | 0.09 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 87.66 | 0.57 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/46.rv_timer_random.3657116099 | ||
| 97.61 | 0.09 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 88.22 | 0.57 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/99.rv_timer_random.2777879706 | ||
| 97.69 | 0.08 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 88.67 | 0.45 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/176.rv_timer_random.701678920 | ||
| 97.76 | 0.08 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 89.13 | 0.45 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/29.rv_timer_random.888209348 | ||
| 97.84 | 0.08 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 89.58 | 0.45 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/47.rv_timer_cfg_update_on_fly.933897455 | ||
| 97.89 | 0.06 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 89.92 | 0.34 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/132.rv_timer_random.127464222 | ||
| 97.95 | 0.06 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 90.26 | 0.34 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/147.rv_timer_random.1891615317 | ||
| 98.01 | 0.06 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 90.60 | 0.34 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/153.rv_timer_random.3826790988 | ||
| 98.06 | 0.06 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 90.94 | 0.34 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/21.rv_timer_cfg_update_on_fly.85209096 | ||
| 98.12 | 0.06 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 91.28 | 0.34 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/29.rv_timer_cfg_update_on_fly.2434659095 | ||
| 98.18 | 0.06 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 91.62 | 0.34 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/41.rv_timer_random.4065495504 | ||
| 98.23 | 0.06 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 91.96 | 0.34 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all.1231688908 | ||
| 98.29 | 0.06 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.35 | 0.00 | 92.30 | 0.34 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/79.rv_timer_random.1778696784 | ||
| 98.34 | 0.05 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.68 | 0.32 | 92.30 | 0.00 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3220560161 | ||
| 98.40 | 0.05 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.32 | 92.30 | 0.00 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.4044692917 | ||
| 98.44 | 0.04 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 92.53 | 0.23 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/10.rv_timer_random.544119808 | ||
| 98.47 | 0.04 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 92.75 | 0.23 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/117.rv_timer_random.2401745396 | ||
| 98.51 | 0.04 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 92.98 | 0.23 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/123.rv_timer_random.4183144754 | ||
| 98.55 | 0.04 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 93.20 | 0.23 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/126.rv_timer_random.556503581 | ||
| 98.59 | 0.04 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 93.43 | 0.23 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/130.rv_timer_random.3628121146 | ||
| 98.62 | 0.04 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 93.66 | 0.23 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/140.rv_timer_random.1574077625 | ||
| 98.66 | 0.04 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 93.88 | 0.23 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/163.rv_timer_random.2979435991 | ||
| 98.70 | 0.04 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 94.11 | 0.23 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/178.rv_timer_random.3157673165 | ||
| 98.74 | 0.04 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 94.34 | 0.23 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/181.rv_timer_random.3405329199 | ||
| 98.78 | 0.04 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 94.56 | 0.23 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/20.rv_timer_random.2517998421 | ||
| 98.81 | 0.04 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 94.79 | 0.23 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/25.rv_timer_cfg_update_on_fly.2609866914 | ||
| 98.85 | 0.04 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.02 | 0.23 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all.3049070418 | ||
| 98.89 | 0.04 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.24 | 0.23 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/31.rv_timer_random_reset.2187988575 | ||
| 98.93 | 0.04 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.47 | 0.23 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/34.rv_timer_random.1993765912 | ||
| 98.96 | 0.04 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.70 | 0.23 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/48.rv_timer_random.2593263946 | ||
| 99.00 | 0.04 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.92 | 0.23 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/71.rv_timer_random.1005895598 | ||
| 99.04 | 0.04 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 96.15 | 0.23 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/84.rv_timer_random.3472719189 | ||
| 99.08 | 0.04 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 96.38 | 0.23 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/87.rv_timer_random.733942777 | ||
| 99.10 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 96.49 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1127488666 | ||
| 99.12 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 96.60 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/100.rv_timer_random.2495319944 | ||
| 99.13 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 96.72 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/102.rv_timer_random.4011447421 | ||
| 99.15 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 96.83 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/105.rv_timer_random.1659218186 | ||
| 99.17 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 96.94 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/11.rv_timer_cfg_update_on_fly.2154140809 | ||
| 99.19 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 97.06 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/110.rv_timer_random.237408903 | ||
| 99.21 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 97.17 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/113.rv_timer_random.905488593 | ||
| 99.23 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 97.28 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/119.rv_timer_random.2618486032 | ||
| 99.25 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 97.40 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/13.rv_timer_cfg_update_on_fly.2893575938 | ||
| 99.27 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 97.51 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/142.rv_timer_random.1820822499 | ||
| 99.29 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 97.62 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/145.rv_timer_random.1513821713 | ||
| 99.30 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 97.73 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/158.rv_timer_random.2562478417 | ||
| 99.32 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 97.85 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/166.rv_timer_random.2631475026 | ||
| 99.34 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 97.96 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/168.rv_timer_random.3115953053 | ||
| 99.36 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 98.07 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/173.rv_timer_random.2713476540 | ||
| 99.38 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 98.19 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/174.rv_timer_random.471840541 | ||
| 99.40 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 98.30 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/18.rv_timer_random.1294499963 | ||
| 99.42 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 98.41 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/18.rv_timer_random_reset.2815567962 | ||
| 99.44 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 98.53 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all.1495978947 | ||
| 99.46 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 98.64 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/28.rv_timer_cfg_update_on_fly.1391304112 | ||
| 99.47 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 98.75 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/30.rv_timer_random_reset.1977829642 | ||
| 99.49 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 98.87 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/34.rv_timer_cfg_update_on_fly.1353828632 | ||
| 99.51 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 98.98 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/39.rv_timer_cfg_update_on_fly.4022977571 | ||
| 99.53 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.09 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/46.rv_timer_cfg_update_on_fly.2490738708 | ||
| 99.55 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.21 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/62.rv_timer_random.1000786259 | ||
| 99.57 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.32 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/67.rv_timer_random.1524253352 | ||
| 99.59 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.43 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all.3077883261 | ||
| 99.61 | 0.02 | 99.36 | 0.00 | 98.73 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 99.55 | 0.11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/76.rv_timer_random.3637785440 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2127750832 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2700911381 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.653603852 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2651529872 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_rw.1676045219 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_intr_test.3865676593 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_errors.1045465891 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1023579301 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_aliasing.691151165 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2636604625 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1145009624 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_rw.1564191430 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_intr_test.1962985551 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3813894016 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_errors.876093461 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3712494273 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.748385323 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_rw.2322304116 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_intr_test.587148704 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4036806065 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.3690367957 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1146425048 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_rw.288895762 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_intr_test.69395507 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1348286544 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.3508591057 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4257305762 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3566260297 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.4182541921 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.72692418 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.890559904 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.3518955083 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2111068518 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.788570966 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.336639722 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.1621328030 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2452304416 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.3587401196 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.167656699 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1944889322 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.3811902479 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.1348822537 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3662634843 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.3259820031 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1478292250 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.723185074 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.1421753914 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.2304040139 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.263354542 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.972304115 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3499226 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.624066573 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.3253758813 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.832446948 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.285239759 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.4098412456 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.721018936 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.2253443215 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.846285654 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.4068343461 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.2496169579 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3883845334 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3723958919 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.2369732569 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.2813517549 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1229959336 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.1188410214 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.752187297 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.745953422 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.2205410606 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.1465757348 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1344282182 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.1780613999 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.888811178 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3505095459 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3920014134 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3605828898 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3586497436 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_rw.685227705 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_intr_test.2816069276 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.491539633 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_errors.2072909016 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.1367407706 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.1727210330 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.2486040094 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.3519129241 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.3351965120 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.3340157255 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.2894487666 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.3916490371 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.3746991874 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.3643589120 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3909249606 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1597878962 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2057450490 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.421576295 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_rw.257049322 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_intr_test.3533629483 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.416765590 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_errors.2993416904 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2489457387 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.1060342618 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.2805628206 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.702555336 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.2518945836 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.1542526371 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.4023468992 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.573097853 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.1779736712 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.211077699 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.4287303217 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_aliasing.75151469 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1151304397 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3082584843 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3819930864 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_rw.3046828153 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_intr_test.31166812 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1274054 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_errors.1018656103 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_intg_err.394475948 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.2031670465 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.990120832 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.3690234029 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.1041634403 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.617675982 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.3788293763 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.53104563 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.2924030591 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.861653 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.1572995519 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1306392627 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_rw.3930790627 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_intr_test.4130954531 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2714523479 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_errors.1018950098 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_intg_err.341242565 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.931226786 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_rw.905581153 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_intr_test.2288900161 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.4217002520 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_errors.283595655 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1753685335 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1780532857 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_rw.505537906 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_intr_test.824709262 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1810427228 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_errors.665706978 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_intg_err.379124746 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.890569516 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_rw.4089075132 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_intr_test.2786315457 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3060912077 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_errors.2407784809 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_intg_err.926175026 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2485846010 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_rw.3665061293 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_intr_test.752722113 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1147977586 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.3661986180 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2851260707 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/0.rv_timer_cfg_update_on_fly.1123230552 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/0.rv_timer_disabled.2488306905 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/0.rv_timer_random.2889264825 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/0.rv_timer_random_reset.2715355744 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/0.rv_timer_sec_cm.3462699690 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all.820819933 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/1.rv_timer_cfg_update_on_fly.1878267049 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/1.rv_timer_disabled.4052734625 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/1.rv_timer_random_reset.3851891359 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/1.rv_timer_sec_cm.1092261619 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all.3881734357 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/10.rv_timer_cfg_update_on_fly.166467064 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/10.rv_timer_disabled.1033077290 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/10.rv_timer_random_reset.1590260069 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all_with_rand_reset.650276863 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/101.rv_timer_random.901749189 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/103.rv_timer_random.2398919296 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/104.rv_timer_random.3050037072 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/107.rv_timer_random.4036934721 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/108.rv_timer_random.2065026049 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/109.rv_timer_random.213123313 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/11.rv_timer_disabled.1501648694 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/11.rv_timer_random.2303687891 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/11.rv_timer_random_reset.3928376823 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/111.rv_timer_random.3434109230 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/112.rv_timer_random.674892065 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/114.rv_timer_random.710022837 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/115.rv_timer_random.3252895823 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/118.rv_timer_random.1747810120 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/12.rv_timer_cfg_update_on_fly.1677990882 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/12.rv_timer_disabled.1180848510 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/12.rv_timer_random.2848069591 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/12.rv_timer_random_reset.2905056362 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all.565313747 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/120.rv_timer_random.2652541058 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/121.rv_timer_random.3636056027 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/122.rv_timer_random.1993673872 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/124.rv_timer_random.1385717105 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/125.rv_timer_random.2056640050 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/127.rv_timer_random.3104806906 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/128.rv_timer_random.1928677589 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/129.rv_timer_random.1487097021 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/13.rv_timer_disabled.1335223696 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/13.rv_timer_random.3322177601 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/13.rv_timer_random_reset.675673595 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all.3281140066 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/131.rv_timer_random.1078721381 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/133.rv_timer_random.1036933588 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/134.rv_timer_random.2116169473 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/135.rv_timer_random.2325750207 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/136.rv_timer_random.2902086404 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/137.rv_timer_random.1370530624 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/138.rv_timer_random.2760275110 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/139.rv_timer_random.1695840463 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/14.rv_timer_cfg_update_on_fly.2054812086 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/14.rv_timer_disabled.2863654824 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/14.rv_timer_random.240059000 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/14.rv_timer_random_reset.2361838259 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/14.rv_timer_stress_all.1526436575 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/141.rv_timer_random.3788108297 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/146.rv_timer_random.2391387263 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/148.rv_timer_random.2707414159 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/149.rv_timer_random.568992140 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/15.rv_timer_cfg_update_on_fly.141536761 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/15.rv_timer_disabled.2952821855 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/15.rv_timer_random_reset.1511266929 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all.3704010315 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/150.rv_timer_random.147498207 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/151.rv_timer_random.3257085603 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/154.rv_timer_random.578204895 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/155.rv_timer_random.678432118 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/156.rv_timer_random.1104771614 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/157.rv_timer_random.2585061498 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/159.rv_timer_random.3072575131 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/16.rv_timer_cfg_update_on_fly.2665490053 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/16.rv_timer_disabled.3859128613 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/16.rv_timer_random.2360574871 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/16.rv_timer_random_reset.1957949844 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all.700177082 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/160.rv_timer_random.184650193 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/161.rv_timer_random.4002623286 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/162.rv_timer_random.3342661826 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/164.rv_timer_random.401307163 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/165.rv_timer_random.3737885853 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/167.rv_timer_random.1648240360 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/169.rv_timer_random.1593229485 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/17.rv_timer_cfg_update_on_fly.841936508 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/17.rv_timer_disabled.3000659021 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/17.rv_timer_random.3965123582 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/17.rv_timer_random_reset.3405886828 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/170.rv_timer_random.1769979196 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/171.rv_timer_random.3288363081 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/172.rv_timer_random.1999220453 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/175.rv_timer_random.1375839368 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/177.rv_timer_random.252723642 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/179.rv_timer_random.2564446253 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/18.rv_timer_cfg_update_on_fly.1916894550 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/18.rv_timer_stress_all.2851708237 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/180.rv_timer_random.4201125752 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/182.rv_timer_random.3540862958 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/183.rv_timer_random.1339799127 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/184.rv_timer_random.593174457 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/185.rv_timer_random.360431844 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/186.rv_timer_random.4290884419 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/187.rv_timer_random.4251734093 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/188.rv_timer_random.3988442413 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/19.rv_timer_cfg_update_on_fly.942155816 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/19.rv_timer_disabled.1600071881 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/19.rv_timer_random.1171425895 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/19.rv_timer_random_reset.4135829808 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all.2515728840 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/190.rv_timer_random.1729277406 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/193.rv_timer_random.2968374444 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/195.rv_timer_random.43764325 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/196.rv_timer_random.1316458081 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/197.rv_timer_random.3382400247 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/198.rv_timer_random.1481561670 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/199.rv_timer_random.2216162335 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/2.rv_timer_cfg_update_on_fly.3603993191 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/2.rv_timer_disabled.261465740 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/2.rv_timer_random.1265688867 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/2.rv_timer_random_reset.3568326990 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/20.rv_timer_cfg_update_on_fly.3141310933 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/20.rv_timer_disabled.1574770200 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/20.rv_timer_random_reset.4075200490 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all.3847516939 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/21.rv_timer_disabled.2633285369 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/21.rv_timer_random.3971360299 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/21.rv_timer_random_reset.713732425 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all.2550293809 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all_with_rand_reset.518252265 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/22.rv_timer_disabled.1269276409 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/22.rv_timer_random.3431898039 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/22.rv_timer_random_reset.1199897948 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/23.rv_timer_cfg_update_on_fly.2454402966 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/23.rv_timer_disabled.1981251902 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/23.rv_timer_random.1041594290 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/23.rv_timer_random_reset.2060268757 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/24.rv_timer_cfg_update_on_fly.55332271 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/24.rv_timer_disabled.2071948671 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/24.rv_timer_random_reset.55316633 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/25.rv_timer_disabled.2393873840 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/25.rv_timer_random_reset.3694511725 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all_with_rand_reset.3351755061 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/26.rv_timer_cfg_update_on_fly.3049957435 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/26.rv_timer_disabled.3026933831 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/26.rv_timer_random.3043688204 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/26.rv_timer_random_reset.1553544560 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/27.rv_timer_cfg_update_on_fly.417098105 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/27.rv_timer_disabled.3977101704 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/27.rv_timer_random.1255345652 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/27.rv_timer_random_reset.2192869895 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all.23349687 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all_with_rand_reset.94934972 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/28.rv_timer_disabled.3539227364 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/28.rv_timer_random.784129672 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/28.rv_timer_random_reset.2781474288 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all.1348761381 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/29.rv_timer_disabled.3887372639 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/29.rv_timer_random_reset.1405585440 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/3.rv_timer_disabled.3742811683 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/3.rv_timer_random.3846385907 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/3.rv_timer_random_reset.3525595679 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/3.rv_timer_sec_cm.1623843731 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/30.rv_timer_cfg_update_on_fly.3029083709 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/30.rv_timer_disabled.2990751401 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/30.rv_timer_random.3316647230 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all.798834060 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all_with_rand_reset.3795516888 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/31.rv_timer_cfg_update_on_fly.1093579025 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/31.rv_timer_disabled.3678774601 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/31.rv_timer_random.2101089669 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all_with_rand_reset.1211482596 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/32.rv_timer_cfg_update_on_fly.2607363580 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/32.rv_timer_disabled.698890411 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/32.rv_timer_random.4016689879 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/32.rv_timer_random_reset.3243830356 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all_with_rand_reset.3052513617 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/33.rv_timer_cfg_update_on_fly.1446096664 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/33.rv_timer_disabled.4034480098 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/34.rv_timer_disabled.1268475736 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/34.rv_timer_random_reset.508215625 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all.794601621 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all_with_rand_reset.3377757138 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/35.rv_timer_cfg_update_on_fly.3115497652 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/35.rv_timer_disabled.4158595036 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/35.rv_timer_random.2742820982 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/35.rv_timer_random_reset.1879011561 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/36.rv_timer_cfg_update_on_fly.776028477 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/36.rv_timer_disabled.560567079 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/36.rv_timer_random.2103862628 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/36.rv_timer_random_reset.1752194762 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all.1153252989 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/37.rv_timer_cfg_update_on_fly.3494761676 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/37.rv_timer_disabled.933365891 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/37.rv_timer_random.1818098300 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/37.rv_timer_random_reset.2512050981 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/38.rv_timer_cfg_update_on_fly.2762375844 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/38.rv_timer_disabled.2454835644 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/38.rv_timer_random.2617061763 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/38.rv_timer_random_reset.496169970 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/39.rv_timer_disabled.1705922041 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/39.rv_timer_random.1435727729 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/39.rv_timer_random_reset.3836692030 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/4.rv_timer_disabled.531377911 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/4.rv_timer_random.1165134102 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/4.rv_timer_sec_cm.2350121497 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/40.rv_timer_cfg_update_on_fly.3504261347 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/40.rv_timer_disabled.3669417931 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/40.rv_timer_random.36044113 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/40.rv_timer_random_reset.1580280037 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all.660446029 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/41.rv_timer_cfg_update_on_fly.1839648169 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/41.rv_timer_disabled.701933858 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all.950736489 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/42.rv_timer_cfg_update_on_fly.3630077233 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/42.rv_timer_disabled.3485653437 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/42.rv_timer_random.25189563 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/42.rv_timer_random_reset.1471902809 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all.3674564325 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/43.rv_timer_cfg_update_on_fly.117722070 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/43.rv_timer_disabled.3769060912 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/43.rv_timer_random_reset.2181397192 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all.2365334875 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/44.rv_timer_cfg_update_on_fly.3399966695 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/44.rv_timer_disabled.3051958191 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/44.rv_timer_random.4052077189 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/44.rv_timer_random_reset.2804543168 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all.2111160214 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all_with_rand_reset.2931806860 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/45.rv_timer_cfg_update_on_fly.2239040815 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/45.rv_timer_disabled.3558020319 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/45.rv_timer_random.12192896 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/45.rv_timer_random_reset.2889438690 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/46.rv_timer_disabled.1981895176 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/46.rv_timer_random_reset.127404069 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all.2001863014 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/47.rv_timer_disabled.980468314 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/47.rv_timer_random.4001963842 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/47.rv_timer_random_reset.2331075588 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/47.rv_timer_stress_all.2756744185 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/48.rv_timer_cfg_update_on_fly.1839413126 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/48.rv_timer_disabled.1596372809 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/48.rv_timer_random_reset.2209813519 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/49.rv_timer_cfg_update_on_fly.3947060079 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/49.rv_timer_disabled.891776368 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/49.rv_timer_random.2215134291 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/49.rv_timer_random_reset.2622122044 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all.2292062139 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/5.rv_timer_cfg_update_on_fly.1722517712 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/5.rv_timer_disabled.791132965 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/5.rv_timer_random_reset.688670569 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all.152300836 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/50.rv_timer_random.1829710086 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/51.rv_timer_random.2121655695 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/52.rv_timer_random.2280589484 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/53.rv_timer_random.3195937467 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/54.rv_timer_random.3450652848 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/55.rv_timer_random.3420924839 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/56.rv_timer_random.433088195 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/57.rv_timer_random.1372247435 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/58.rv_timer_random.3266175172 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/59.rv_timer_random.403513622 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/6.rv_timer_cfg_update_on_fly.59614233 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/6.rv_timer_disabled.1414675099 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/6.rv_timer_random.2382346647 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/6.rv_timer_random_reset.2590988925 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/60.rv_timer_random.2879732539 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/61.rv_timer_random.2892767678 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/63.rv_timer_random.937300530 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/64.rv_timer_random.2005823250 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/65.rv_timer_random.2587043185 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/66.rv_timer_random.2172840884 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/68.rv_timer_random.4190467838 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/69.rv_timer_random.17831543 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/7.rv_timer_cfg_update_on_fly.4078376778 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/7.rv_timer_disabled.3337780693 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/7.rv_timer_random.1167604792 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/7.rv_timer_random_reset.3139828455 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/70.rv_timer_random.4026498874 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/72.rv_timer_random.3517092147 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/73.rv_timer_random.3782440230 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/74.rv_timer_random.1672222995 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/75.rv_timer_random.2506398275 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/77.rv_timer_random.647213846 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/78.rv_timer_random.1148596412 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/8.rv_timer_cfg_update_on_fly.1265272231 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/8.rv_timer_disabled.2114856638 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/8.rv_timer_random.2148547401 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/8.rv_timer_random_reset.3504611819 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all.2658792308 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/80.rv_timer_random.1908812144 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/81.rv_timer_random.279572280 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/82.rv_timer_random.429072654 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/83.rv_timer_random.545885873 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/85.rv_timer_random.1884701703 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/86.rv_timer_random.2911590636 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/88.rv_timer_random.3780707220 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/89.rv_timer_random.914100445 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/9.rv_timer_cfg_update_on_fly.4090026370 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/9.rv_timer_disabled.3849550854 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/9.rv_timer_random.2582933723 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/9.rv_timer_random_reset.350309166 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all.581685547 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/90.rv_timer_random.1193984822 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/91.rv_timer_random.2310305784 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/92.rv_timer_random.1435666993 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/93.rv_timer_random.145196029 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/94.rv_timer_random.2461731450 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/95.rv_timer_random.2836603984 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/96.rv_timer_random.83027052 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/97.rv_timer_random.2248847016 |
| /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/98.rv_timer_random.1355961521 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/0.rv_timer_random_reset.2715355744 | Feb 08 09:15:18 AM UTC 25 | Feb 08 09:15:22 AM UTC 25 | 76970545 ps | ||
| T2 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/0.rv_timer_sec_cm.3462699690 | Feb 08 09:15:20 AM UTC 25 | Feb 08 09:15:23 AM UTC 25 | 74587717 ps | ||
| T3 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/1.rv_timer_random_reset.3851891359 | Feb 08 09:15:20 AM UTC 25 | Feb 08 09:15:23 AM UTC 25 | 410229048 ps | ||
| T4 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/1.rv_timer_sec_cm.1092261619 | Feb 08 09:15:21 AM UTC 25 | Feb 08 09:15:24 AM UTC 25 | 64576127 ps | ||
| T5 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/22.rv_timer_cfg_update_on_fly.2876678722 | Feb 08 09:23:10 AM UTC 25 | Feb 08 09:23:47 AM UTC 25 | 52228915968 ps | ||
| T6 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/2.rv_timer_sec_cm.3686136886 | Feb 08 09:15:22 AM UTC 25 | Feb 08 09:15:25 AM UTC 25 | 93054384 ps | ||
| T7 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/3.rv_timer_random_reset.3525595679 | Feb 08 09:15:24 AM UTC 25 | Feb 08 09:15:27 AM UTC 25 | 1091543160 ps | ||
| T8 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/3.rv_timer_sec_cm.1623843731 | Feb 08 09:15:25 AM UTC 25 | Feb 08 09:15:28 AM UTC 25 | 31770259 ps | ||
| T9 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/4.rv_timer_sec_cm.2350121497 | Feb 08 09:15:36 AM UTC 25 | Feb 08 09:15:38 AM UTC 25 | 37054660 ps | ||
| T10 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/5.rv_timer_random_reset.688670569 | Feb 08 09:15:58 AM UTC 25 | Feb 08 09:16:02 AM UTC 25 | 775618944 ps | ||
| T21 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/1.rv_timer_disabled.4052734625 | Feb 08 09:15:20 AM UTC 25 | Feb 08 09:16:15 AM UTC 25 | 104343129109 ps | ||
| T28 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/7.rv_timer_random_reset.3139828455 | Feb 08 09:16:19 AM UTC 25 | Feb 08 09:16:21 AM UTC 25 | 81871802 ps | ||
| T14 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/3.rv_timer_random.3846385907 | Feb 08 09:15:22 AM UTC 25 | Feb 08 09:16:50 AM UTC 25 | 45244330956 ps | ||
| T15 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/8.rv_timer_cfg_update_on_fly.1265272231 | Feb 08 09:16:28 AM UTC 25 | Feb 08 09:16:50 AM UTC 25 | 10666030447 ps | ||
| T29 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/9.rv_timer_random_reset.350309166 | Feb 08 09:16:55 AM UTC 25 | Feb 08 09:16:58 AM UTC 25 | 154917711 ps | ||
| T25 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/5.rv_timer_disabled.791132965 | Feb 08 09:15:44 AM UTC 25 | Feb 08 09:17:04 AM UTC 25 | 166844916093 ps | ||
| T16 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/4.rv_timer_cfg_update_on_fly.3572812109 | Feb 08 09:15:28 AM UTC 25 | Feb 08 09:17:09 AM UTC 25 | 124168340386 ps | ||
| T20 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/4.rv_timer_random_reset.2877320515 | Feb 08 09:15:30 AM UTC 25 | Feb 08 09:17:09 AM UTC 25 | 26775208275 ps | ||
| T17 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/4.rv_timer_disabled.531377911 | Feb 08 09:15:26 AM UTC 25 | Feb 08 09:17:31 AM UTC 25 | 306481371001 ps | ||
| T384 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/3.rv_timer_disabled.3742811683 | Feb 08 09:15:24 AM UTC 25 | Feb 08 09:17:41 AM UTC 25 | 413199776494 ps | ||
| T385 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/10.rv_timer_random_reset.1590260069 | Feb 08 09:17:32 AM UTC 25 | Feb 08 09:17:47 AM UTC 25 | 13848330544 ps | ||
| T149 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/2.rv_timer_random_reset.3568326990 | Feb 08 09:15:21 AM UTC 25 | Feb 08 09:17:51 AM UTC 25 | 57586702393 ps | ||
| T386 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/2.rv_timer_disabled.261465740 | Feb 08 09:15:21 AM UTC 25 | Feb 08 09:17:53 AM UTC 25 | 380464908823 ps | ||
| T387 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/11.rv_timer_random_reset.3928376823 | Feb 08 09:17:53 AM UTC 25 | Feb 08 09:17:57 AM UTC 25 | 893692232 ps | ||
| T388 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/6.rv_timer_disabled.1414675099 | Feb 08 09:16:03 AM UTC 25 | Feb 08 09:17:59 AM UTC 25 | 139598363272 ps | ||
| T124 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/8.rv_timer_random_reset.3504611819 | Feb 08 09:16:50 AM UTC 25 | Feb 08 09:17:59 AM UTC 25 | 55766400084 ps | ||
| T11 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all.3881734357 | Feb 08 09:15:21 AM UTC 25 | Feb 08 09:18:09 AM UTC 25 | 131143563516 ps | ||
| T95 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/6.rv_timer_random.2382346647 | Feb 08 09:16:03 AM UTC 25 | Feb 08 09:18:23 AM UTC 25 | 63154605317 ps | ||
| T389 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all.820819933 | Feb 08 09:15:20 AM UTC 25 | Feb 08 09:18:24 AM UTC 25 | 278270861202 ps | ||
| T100 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/1.rv_timer_random.3573493399 | Feb 08 09:15:20 AM UTC 25 | Feb 08 09:18:44 AM UTC 25 | 68599303551 ps | ||
| T390 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/0.rv_timer_disabled.2488306905 | Feb 08 09:15:18 AM UTC 25 | Feb 08 09:18:49 AM UTC 25 | 763813356581 ps | ||
| T143 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/1.rv_timer_cfg_update_on_fly.1878267049 | Feb 08 09:15:20 AM UTC 25 | Feb 08 09:19:02 AM UTC 25 | 838442051024 ps | ||
| T391 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/7.rv_timer_disabled.3337780693 | Feb 08 09:16:13 AM UTC 25 | Feb 08 09:19:04 AM UTC 25 | 427128926573 ps | ||
| T392 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/9.rv_timer_disabled.3849550854 | Feb 08 09:16:55 AM UTC 25 | Feb 08 09:19:11 AM UTC 25 | 326763714642 ps | ||
| T132 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/10.rv_timer_random.544119808 | Feb 08 09:17:10 AM UTC 25 | Feb 08 09:19:27 AM UTC 25 | 61728872256 ps | ||
| T144 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/6.rv_timer_random_reset.2590988925 | Feb 08 09:16:07 AM UTC 25 | Feb 08 09:19:27 AM UTC 25 | 48684988834 ps | ||
| T393 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/8.rv_timer_disabled.2114856638 | Feb 08 09:16:26 AM UTC 25 | Feb 08 09:19:27 AM UTC 25 | 365144248113 ps | ||
| T133 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/7.rv_timer_cfg_update_on_fly.4078376778 | Feb 08 09:16:16 AM UTC 25 | Feb 08 09:19:30 AM UTC 25 | 126905819372 ps | ||
| T125 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/9.rv_timer_random.2582933723 | Feb 08 09:16:52 AM UTC 25 | Feb 08 09:19:37 AM UTC 25 | 103366199204 ps | ||
| T394 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/11.rv_timer_disabled.1501648694 | Feb 08 09:17:47 AM UTC 25 | Feb 08 09:19:46 AM UTC 25 | 37398556520 ps | ||
| T97 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/12.rv_timer_random_reset.2905056362 | Feb 08 09:18:10 AM UTC 25 | Feb 08 09:19:47 AM UTC 25 | 47565561918 ps | ||
| T395 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/13.rv_timer_disabled.1335223696 | Feb 08 09:18:25 AM UTC 25 | Feb 08 09:19:50 AM UTC 25 | 86446381691 ps | ||
| T106 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/13.rv_timer_cfg_update_on_fly.2893575938 | Feb 08 09:18:31 AM UTC 25 | Feb 08 09:23:36 AM UTC 25 | 139782796543 ps | ||
| T223 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/15.rv_timer_cfg_update_on_fly.141536761 | Feb 08 09:19:31 AM UTC 25 | Feb 08 09:19:59 AM UTC 25 | 13563214124 ps | ||
| T150 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/0.rv_timer_cfg_update_on_fly.1123230552 | Feb 08 09:15:18 AM UTC 25 | Feb 08 09:20:09 AM UTC 25 | 386689075926 ps | ||
| T138 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/6.rv_timer_cfg_update_on_fly.59614233 | Feb 08 09:16:05 AM UTC 25 | Feb 08 09:20:17 AM UTC 25 | 106750566502 ps | ||
| T142 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/15.rv_timer_random_reset.1511266929 | Feb 08 09:19:38 AM UTC 25 | Feb 08 09:20:42 AM UTC 25 | 31339905174 ps | ||
| T92 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/17.rv_timer_random.3965123582 | Feb 08 09:20:13 AM UTC 25 | Feb 08 09:20:58 AM UTC 25 | 83403892220 ps | ||
| T141 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/14.rv_timer_random.240059000 | Feb 08 09:18:50 AM UTC 25 | Feb 08 09:20:59 AM UTC 25 | 40130152399 ps | ||
| T98 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/12.rv_timer_random.2848069591 | Feb 08 09:18:00 AM UTC 25 | Feb 08 09:21:17 AM UTC 25 | 89506603590 ps | ||
| T131 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/14.rv_timer_random_reset.2361838259 | Feb 08 09:19:12 AM UTC 25 | Feb 08 09:21:20 AM UTC 25 | 178268802041 ps | ||
| T396 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/15.rv_timer_disabled.2952821855 | Feb 08 09:19:29 AM UTC 25 | Feb 08 09:21:41 AM UTC 25 | 54462564450 ps | ||
| T96 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/0.rv_timer_random.2889264825 | Feb 08 09:15:18 AM UTC 25 | Feb 08 09:21:42 AM UTC 25 | 1765490103345 ps | ||
| T117 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/12.rv_timer_cfg_update_on_fly.1677990882 | Feb 08 09:18:08 AM UTC 25 | Feb 08 09:21:56 AM UTC 25 | 118682661096 ps | ||
| T101 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/5.rv_timer_cfg_update_on_fly.1722517712 | Feb 08 09:15:47 AM UTC 25 | Feb 08 09:22:06 AM UTC 25 | 165570773291 ps | ||
| T112 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/10.rv_timer_cfg_update_on_fly.166467064 | Feb 08 09:17:15 AM UTC 25 | Feb 08 09:22:12 AM UTC 25 | 217675820705 ps | ||
| T12 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all_with_rand_reset.4255416841 | Feb 08 09:19:38 AM UTC 25 | Feb 08 09:22:33 AM UTC 25 | 86935393723 ps | ||
| T37 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/2.rv_timer_cfg_update_on_fly.3603993191 | Feb 08 09:15:21 AM UTC 25 | Feb 08 09:22:42 AM UTC 25 | 617479152906 ps | ||
| T38 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/14.rv_timer_disabled.2863654824 | Feb 08 09:19:03 AM UTC 25 | Feb 08 09:22:45 AM UTC 25 | 150909942364 ps | ||
| T39 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/16.rv_timer_disabled.3859128613 | Feb 08 09:19:50 AM UTC 25 | Feb 08 09:22:47 AM UTC 25 | 414988270949 ps | ||
| T40 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/19.rv_timer_random_reset.4135829808 | Feb 08 09:21:45 AM UTC 25 | Feb 08 09:22:48 AM UTC 25 | 79255735806 ps | ||
| T41 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/12.rv_timer_disabled.1180848510 | Feb 08 09:18:04 AM UTC 25 | Feb 08 09:22:50 AM UTC 25 | 180824883142 ps | ||
| T42 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/17.rv_timer_disabled.3000659021 | Feb 08 09:20:18 AM UTC 25 | Feb 08 09:22:50 AM UTC 25 | 764625864146 ps | ||
| T43 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/5.rv_timer_random.1476514725 | Feb 08 09:15:39 AM UTC 25 | Feb 08 09:22:59 AM UTC 25 | 541762767500 ps | ||
| T44 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/8.rv_timer_random.2148547401 | Feb 08 09:16:23 AM UTC 25 | Feb 08 09:23:01 AM UTC 25 | 563690733009 ps | ||
| T13 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all.1495978947 | Feb 08 09:15:22 AM UTC 25 | Feb 08 09:23:03 AM UTC 25 | 940323865191 ps | ||
| T113 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/18.rv_timer_random.1294499963 | Feb 08 09:21:00 AM UTC 25 | Feb 08 09:23:05 AM UTC 25 | 63353851021 ps | ||
| T136 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/16.rv_timer_random_reset.1957949844 | Feb 08 09:20:00 AM UTC 25 | Feb 08 09:23:16 AM UTC 25 | 77591117331 ps | ||
| T383 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all.2550293809 | Feb 08 09:23:02 AM UTC 25 | Feb 08 09:23:24 AM UTC 25 | 15350168707 ps | ||
| T397 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/10.rv_timer_disabled.1033077290 | Feb 08 09:17:10 AM UTC 25 | Feb 08 09:23:27 AM UTC 25 | 184626895403 ps | ||
| T102 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/13.rv_timer_random_reset.675673595 | Feb 08 09:18:43 AM UTC 25 | Feb 08 09:23:52 AM UTC 25 | 102651467596 ps | ||
| T398 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/23.rv_timer_random_reset.2060268757 | Feb 08 09:23:53 AM UTC 25 | Feb 08 09:23:55 AM UTC 25 | 108121737 ps | ||
| T382 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/14.rv_timer_stress_all.1526436575 | Feb 08 09:19:29 AM UTC 25 | Feb 08 09:23:57 AM UTC 25 | 147471818678 ps | ||
| T399 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/21.rv_timer_disabled.2633285369 | Feb 08 09:22:51 AM UTC 25 | Feb 08 09:24:14 AM UTC 25 | 58035687323 ps | ||
| T137 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/20.rv_timer_random_reset.4075200490 | Feb 08 09:22:43 AM UTC 25 | Feb 08 09:24:17 AM UTC 25 | 18415413687 ps | ||
| T140 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/4.rv_timer_random.1165134102 | Feb 08 09:15:26 AM UTC 25 | Feb 08 09:24:18 AM UTC 25 | 174568620537 ps | ||
| T99 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/18.rv_timer_stress_all.2851708237 | Feb 08 09:21:18 AM UTC 25 | Feb 08 09:24:25 AM UTC 25 | 569148749498 ps | ||
| T400 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all.3281140066 | Feb 08 09:18:49 AM UTC 25 | Feb 08 09:24:28 AM UTC 25 | 620226036850 ps | ||
| T401 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/24.rv_timer_random_reset.55316633 | Feb 08 09:24:25 AM UTC 25 | Feb 08 09:24:28 AM UTC 25 | 1130265903 ps | ||
| T108 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/15.rv_timer_random.894186137 | Feb 08 09:19:29 AM UTC 25 | Feb 08 09:24:37 AM UTC 25 | 190430110948 ps | ||
| T139 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/22.rv_timer_random_reset.1199897948 | Feb 08 09:23:17 AM UTC 25 | Feb 08 09:24:39 AM UTC 25 | 164161261357 ps | ||
| T402 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all.3704010315 | Feb 08 09:19:47 AM UTC 25 | Feb 08 09:24:44 AM UTC 25 | 266469041087 ps | ||
| T109 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/18.rv_timer_random_reset.2815567962 | Feb 08 09:21:02 AM UTC 25 | Feb 08 09:24:57 AM UTC 25 | 30330905015 ps | ||
| T403 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/24.rv_timer_disabled.2071948671 | Feb 08 09:24:18 AM UTC 25 | Feb 08 09:24:59 AM UTC 25 | 23343036093 ps | ||
| T153 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/14.rv_timer_cfg_update_on_fly.2054812086 | Feb 08 09:19:04 AM UTC 25 | Feb 08 09:24:59 AM UTC 25 | 418966691022 ps | ||
| T134 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/16.rv_timer_random.2360574871 | Feb 08 09:19:47 AM UTC 25 | Feb 08 09:25:02 AM UTC 25 | 318968602034 ps | ||
| T50 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all.152300836 | Feb 08 09:16:01 AM UTC 25 | Feb 08 09:25:02 AM UTC 25 | 534893112159 ps | ||
| T129 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/17.rv_timer_random_reset.3405886828 | Feb 08 09:20:43 AM UTC 25 | Feb 08 09:25:06 AM UTC 25 | 313993426445 ps | ||
| T404 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/36.rv_timer_disabled.560567079 | Feb 08 09:30:55 AM UTC 25 | Feb 08 09:35:19 AM UTC 25 | 155366492985 ps | ||
| T405 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/19.rv_timer_disabled.1600071881 | Feb 08 09:21:43 AM UTC 25 | Feb 08 09:25:18 AM UTC 25 | 334407932630 ps | ||
| T130 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/13.rv_timer_random.3322177601 | Feb 08 09:18:24 AM UTC 25 | Feb 08 09:25:28 AM UTC 25 | 478864561663 ps | ||
| T115 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/20.rv_timer_cfg_update_on_fly.3141310933 | Feb 08 09:22:34 AM UTC 25 | Feb 08 09:25:39 AM UTC 25 | 416535772621 ps | ||
| T406 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/23.rv_timer_disabled.1981251902 | Feb 08 09:23:37 AM UTC 25 | Feb 08 09:25:41 AM UTC 25 | 44755935012 ps | ||
| T18 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all_with_rand_reset.518252265 | Feb 08 09:23:00 AM UTC 25 | Feb 08 09:25:49 AM UTC 25 | 18032315909 ps | ||
| T407 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/26.rv_timer_disabled.3026933831 | Feb 08 09:25:00 AM UTC 25 | Feb 08 09:25:50 AM UTC 25 | 40757612596 ps | ||
| T249 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/26.rv_timer_cfg_update_on_fly.3049957435 | Feb 08 09:25:02 AM UTC 25 | Feb 08 09:26:04 AM UTC 25 | 57254437651 ps | ||
| T121 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/21.rv_timer_random.3971360299 | Feb 08 09:22:49 AM UTC 25 | Feb 08 09:26:10 AM UTC 25 | 82056390212 ps | ||
| T148 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/25.rv_timer_random_reset.3694511725 | Feb 08 09:24:40 AM UTC 25 | Feb 08 09:26:18 AM UTC 25 | 213597596505 ps | ||
| T93 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/9.rv_timer_cfg_update_on_fly.4090026370 | Feb 08 09:16:55 AM UTC 25 | Feb 08 09:26:29 AM UTC 25 | 429640266475 ps | ||
| T51 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all.581685547 | Feb 08 09:17:05 AM UTC 25 | Feb 08 09:26:43 AM UTC 25 | 1014443899267 ps | ||
| T19 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all_with_rand_reset.3351755061 | Feb 08 09:24:45 AM UTC 25 | Feb 08 09:26:53 AM UTC 25 | 15322265928 ps | ||
| T408 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/25.rv_timer_disabled.2393873840 | Feb 08 09:24:31 AM UTC 25 | Feb 08 09:27:00 AM UTC 25 | 85378008416 ps | ||
| T409 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/20.rv_timer_disabled.1574770200 | Feb 08 09:22:21 AM UTC 25 | Feb 08 09:27:01 AM UTC 25 | 511651925573 ps | ||
| T104 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/3.rv_timer_cfg_update_on_fly.880833308 | Feb 08 09:15:24 AM UTC 25 | Feb 08 09:27:13 AM UTC 25 | 1818202417797 ps | ||
| T410 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/28.rv_timer_disabled.3539227364 | Feb 08 09:26:13 AM UTC 25 | Feb 08 09:27:31 AM UTC 25 | 40653555429 ps | ||
| T411 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/22.rv_timer_disabled.1269276409 | Feb 08 09:23:06 AM UTC 25 | Feb 08 09:27:48 AM UTC 25 | 389430611137 ps | ||
| T135 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/21.rv_timer_random_reset.713732425 | Feb 08 09:22:53 AM UTC 25 | Feb 08 09:27:59 AM UTC 25 | 76662695867 ps | ||
| T412 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all.2515728840 | Feb 08 09:22:07 AM UTC 25 | Feb 08 09:28:17 AM UTC 25 | 223982566891 ps | ||
| T111 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/7.rv_timer_random.1167604792 | Feb 08 09:16:13 AM UTC 25 | Feb 08 09:28:18 AM UTC 25 | 59286690939 ps | ||
| T128 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/22.rv_timer_random.3431898039 | Feb 08 09:23:04 AM UTC 25 | Feb 08 09:28:21 AM UTC 25 | 26564868458 ps | ||
| T114 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all.700538117 | Feb 08 09:20:59 AM UTC 25 | Feb 08 09:28:26 AM UTC 25 | 1995697677015 ps | ||
| T345 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/27.rv_timer_random_reset.2192869895 | Feb 08 09:25:42 AM UTC 25 | Feb 08 09:28:30 AM UTC 25 | 33976079108 ps | ||
| T352 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/30.rv_timer_random_reset.1977829642 | Feb 08 09:27:49 AM UTC 25 | Feb 08 09:28:37 AM UTC 25 | 29947138718 ps | ||
| T147 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/26.rv_timer_random_reset.1553544560 | Feb 08 09:25:03 AM UTC 25 | Feb 08 09:28:48 AM UTC 25 | 440546303758 ps | ||
| T52 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all.700177082 | Feb 08 09:20:10 AM UTC 25 | Feb 08 09:28:57 AM UTC 25 | 830674568506 ps | ||
| T346 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/30.rv_timer_random.3316647230 | Feb 08 09:27:14 AM UTC 25 | Feb 08 09:29:01 AM UTC 25 | 288297883402 ps | ||
| T413 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/30.rv_timer_disabled.2990751401 | Feb 08 09:27:32 AM UTC 25 | Feb 08 09:29:02 AM UTC 25 | 198913191858 ps | ||
| T116 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all.3847516939 | Feb 08 09:22:48 AM UTC 25 | Feb 08 09:29:05 AM UTC 25 | 182365563525 ps | ||
| T94 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/17.rv_timer_cfg_update_on_fly.841936508 | Feb 08 09:20:28 AM UTC 25 | Feb 08 09:29:09 AM UTC 25 | 717795878625 ps | ||
| T107 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/11.rv_timer_cfg_update_on_fly.2154140809 | Feb 08 09:17:51 AM UTC 25 | Feb 08 09:29:09 AM UTC 25 | 307396341889 ps | ||
| T118 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/27.rv_timer_random.1255345652 | Feb 08 09:25:20 AM UTC 25 | Feb 08 09:29:17 AM UTC 25 | 86750392614 ps | ||
| T414 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/32.rv_timer_random_reset.3243830356 | Feb 08 09:29:03 AM UTC 25 | Feb 08 09:29:18 AM UTC 25 | 7365693554 ps | ||
| T30 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all_with_rand_reset.650276863 | Feb 08 09:17:39 AM UTC 25 | Feb 08 09:29:37 AM UTC 25 | 73695177024 ps | ||
| T308 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/19.rv_timer_cfg_update_on_fly.942155816 | Feb 08 09:21:43 AM UTC 25 | Feb 08 09:29:42 AM UTC 25 | 509181473044 ps | ||
| T325 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/31.rv_timer_random_reset.2187988575 | Feb 08 09:28:32 AM UTC 25 | Feb 08 09:29:49 AM UTC 25 | 45627366246 ps | ||
| T119 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/27.rv_timer_cfg_update_on_fly.417098105 | Feb 08 09:25:40 AM UTC 25 | Feb 08 09:30:11 AM UTC 25 | 118999150076 ps | ||
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| T415 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/27.rv_timer_disabled.3977101704 | Feb 08 09:25:28 AM UTC 25 | Feb 08 09:30:14 AM UTC 25 | 506230024050 ps | ||
| T145 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/28.rv_timer_random_reset.2781474288 | Feb 08 09:26:31 AM UTC 25 | Feb 08 09:30:25 AM UTC 25 | 89425951388 ps | ||
| T185 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/20.rv_timer_random.2517998421 | Feb 08 09:22:12 AM UTC 25 | Feb 08 09:30:26 AM UTC 25 | 1510749993506 ps | ||
| T169 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/33.rv_timer_random_reset.3573704117 | Feb 08 09:29:18 AM UTC 25 | Feb 08 09:30:27 AM UTC 25 | 32100920761 ps | ||
| T31 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all_with_rand_reset.94934972 | Feb 08 09:25:51 AM UTC 25 | Feb 08 09:30:41 AM UTC 25 | 25129381160 ps | ||
| T416 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/29.rv_timer_disabled.3887372639 | Feb 08 09:26:55 AM UTC 25 | Feb 08 09:30:41 AM UTC 25 | 446010851892 ps | ||
| T122 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/23.rv_timer_random.1041594290 | Feb 08 09:23:28 AM UTC 25 | Feb 08 09:30:41 AM UTC 25 | 314346326992 ps | ||
| T323 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/16.rv_timer_cfg_update_on_fly.2665490053 | Feb 08 09:19:54 AM UTC 25 | Feb 08 09:30:50 AM UTC 25 | 362649088686 ps | ||
| T126 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/28.rv_timer_cfg_update_on_fly.1391304112 | Feb 08 09:26:19 AM UTC 25 | Feb 08 09:30:54 AM UTC 25 | 177503588282 ps | ||
| T417 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/31.rv_timer_disabled.3678774601 | Feb 08 09:28:22 AM UTC 25 | Feb 08 09:31:00 AM UTC 25 | 134286327230 ps | ||
| T418 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all.23349687 | Feb 08 09:25:51 AM UTC 25 | Feb 08 09:31:07 AM UTC 25 | 140915087889 ps | ||
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| T419 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all.1348761381 | Feb 08 09:26:44 AM UTC 25 | Feb 08 09:31:41 AM UTC 25 | 606746174904 ps | ||
| T127 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all.565313747 | Feb 08 09:18:19 AM UTC 25 | Feb 08 09:31:49 AM UTC 25 | 167339916766 ps | ||
| T420 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/33.rv_timer_disabled.4034480098 | Feb 08 09:29:11 AM UTC 25 | Feb 08 09:31:57 AM UTC 25 | 97448801103 ps | ||
| T248 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/21.rv_timer_cfg_update_on_fly.85209096 | Feb 08 09:22:51 AM UTC 25 | Feb 08 09:32:35 AM UTC 25 | 842797702439 ps | ||
| T421 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/37.rv_timer_random_reset.2512050981 | Feb 08 09:32:36 AM UTC 25 | Feb 08 09:32:44 AM UTC 25 | 10049479016 ps | ||
| T231 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/24.rv_timer_cfg_update_on_fly.55332271 | Feb 08 09:24:19 AM UTC 25 | Feb 08 09:32:45 AM UTC 25 | 290366130760 ps | ||
| T422 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/32.rv_timer_disabled.698890411 | Feb 08 09:28:58 AM UTC 25 | Feb 08 09:33:00 AM UTC 25 | 130020516971 ps | ||
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| T210 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/36.rv_timer_random_reset.1752194762 | Feb 08 09:31:08 AM UTC 25 | Feb 08 09:33:10 AM UTC 25 | 126654435737 ps | ||
| T423 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/34.rv_timer_disabled.1268475736 | Feb 08 09:29:50 AM UTC 25 | Feb 08 09:33:23 AM UTC 25 | 112594156915 ps | ||
| T424 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/38.rv_timer_random_reset.496169970 | Feb 08 09:33:24 AM UTC 25 | Feb 08 09:33:27 AM UTC 25 | 607653045 ps | ||
| T146 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all.3049070418 | Feb 08 09:15:25 AM UTC 25 | Feb 08 09:33:30 AM UTC 25 | 434606723006 ps | ||
| T123 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/11.rv_timer_random.2303687891 | Feb 08 09:17:43 AM UTC 25 | Feb 08 09:33:46 AM UTC 25 | 328503703155 ps | ||
| T32 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all_with_rand_reset.3377757138 | Feb 08 09:30:14 AM UTC 25 | Feb 08 09:34:06 AM UTC 25 | 84033025795 ps | ||
| T53 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all.1153252989 | Feb 08 09:31:41 AM UTC 25 | Feb 08 09:34:23 AM UTC 25 | 172399829956 ps | ||
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| T425 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/37.rv_timer_disabled.933365891 | Feb 08 09:31:57 AM UTC 25 | Feb 08 09:34:23 AM UTC 25 | 107879442058 ps | ||
| T290 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/30.rv_timer_cfg_update_on_fly.3029083709 | Feb 08 09:27:32 AM UTC 25 | Feb 08 09:34:25 AM UTC 25 | 378340245368 ps | ||
| T296 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all.794601621 | Feb 08 09:30:25 AM UTC 25 | Feb 08 09:34:30 AM UTC 25 | 183750834702 ps | ||
| T110 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/26.rv_timer_random.3043688204 | Feb 08 09:24:59 AM UTC 25 | Feb 08 09:34:42 AM UTC 25 | 587667611836 ps | ||
| T256 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/40.rv_timer_cfg_update_on_fly.3504261347 | Feb 08 09:34:43 AM UTC 25 | Feb 08 09:34:51 AM UTC 25 | 5820937814 ps | ||
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| T426 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all.660446029 | Feb 08 09:35:20 AM UTC 25 | Feb 08 09:35:22 AM UTC 25 | 21397353 ps | ||
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| T427 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/38.rv_timer_disabled.2454835644 | Feb 08 09:33:10 AM UTC 25 | Feb 08 09:35:49 AM UTC 25 | 177517877801 ps | ||
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| T322 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/47.rv_timer_cfg_update_on_fly.933897455 | Feb 08 09:39:23 AM UTC 25 | Feb 08 09:46:46 AM UTC 25 | 556748455578 ps | ||
| T254 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all.3810912501 | Feb 08 09:15:36 AM UTC 25 | Feb 08 09:36:13 AM UTC 25 | 396817369127 ps | ||
| T286 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/38.rv_timer_random.2617061763 | Feb 08 09:33:01 AM UTC 25 | Feb 08 09:36:27 AM UTC 25 | 39229997614 ps | ||
| T161 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/29.rv_timer_random_reset.1405585440 | Feb 08 09:27:03 AM UTC 25 | Feb 08 09:36:50 AM UTC 25 | 458303175670 ps | ||
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| T263 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/39.rv_timer_random_reset.3836692030 | Feb 08 09:34:24 AM UTC 25 | Feb 08 09:36:57 AM UTC 25 | 118824891389 ps | ||
| T428 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/40.rv_timer_disabled.3669417931 | Feb 08 09:34:31 AM UTC 25 | Feb 08 09:36:59 AM UTC 25 | 64451372183 ps | ||
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| T429 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/35.rv_timer_disabled.4158595036 | Feb 08 09:30:28 AM UTC 25 | Feb 08 09:37:40 AM UTC 25 | 150238343099 ps | ||
| T430 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/42.rv_timer_disabled.3485653437 | Feb 08 09:36:28 AM UTC 25 | Feb 08 09:37:41 AM UTC 25 | 95303553742 ps | ||
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| T239 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/37.rv_timer_random.1818098300 | Feb 08 09:31:50 AM UTC 25 | Feb 08 09:38:03 AM UTC 25 | 265475248139 ps | ||
| T151 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/18.rv_timer_cfg_update_on_fly.1916894550 | Feb 08 09:21:02 AM UTC 25 | Feb 08 09:38:24 AM UTC 25 | 1879677080398 ps | ||
| T431 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/41.rv_timer_disabled.701933858 | Feb 08 09:35:40 AM UTC 25 | Feb 08 09:38:25 AM UTC 25 | 231725495617 ps | ||
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| T264 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/29.rv_timer_random.888209348 | Feb 08 09:26:54 AM UTC 25 | Feb 08 09:38:35 AM UTC 25 | 155938130473 ps | ||
| T214 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/33.rv_timer_random.1883923884 | Feb 08 09:29:10 AM UTC 25 | Feb 08 09:38:37 AM UTC 25 | 215073651484 ps | ||
| T432 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/39.rv_timer_disabled.1705922041 | Feb 08 09:33:49 AM UTC 25 | Feb 08 09:38:40 AM UTC 25 | 169388896216 ps | ||
| T433 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/45.rv_timer_disabled.3558020319 | Feb 08 09:38:36 AM UTC 25 | Feb 08 09:38:51 AM UTC 25 | 4265213799 ps | ||
| T186 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/34.rv_timer_cfg_update_on_fly.1353828632 | Feb 08 09:30:12 AM UTC 25 | Feb 08 09:38:56 AM UTC 25 | 731355082914 ps | ||
| T166 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/41.rv_timer_random.4065495504 | Feb 08 09:35:23 AM UTC 25 | Feb 08 09:38:56 AM UTC 25 | 302887498918 ps | ||
| T33 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all_with_rand_reset.3052513617 | Feb 08 09:29:06 AM UTC 25 | Feb 08 09:38:57 AM UTC 25 | 51503095811 ps | ||
| T287 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/34.rv_timer_random.1993765912 | Feb 08 09:29:47 AM UTC 25 | Feb 08 09:38:58 AM UTC 25 | 509114864606 ps | ||
| T170 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/36.rv_timer_cfg_update_on_fly.776028477 | Feb 08 09:31:01 AM UTC 25 | Feb 08 09:39:16 AM UTC 25 | 1117233416720 ps | ||
| T278 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all.3674564325 | Feb 08 09:36:55 AM UTC 25 | Feb 08 09:39:16 AM UTC 25 | 70327610460 ps | ||
| T434 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/46.rv_timer_disabled.1981895176 | Feb 08 09:38:57 AM UTC 25 | Feb 08 09:39:17 AM UTC 25 | 61846361297 ps | ||
| T298 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/39.rv_timer_cfg_update_on_fly.4022977571 | Feb 08 09:34:06 AM UTC 25 | Feb 08 09:39:23 AM UTC 25 | 110057530465 ps | ||
| T435 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/43.rv_timer_disabled.3769060912 | Feb 08 09:36:58 AM UTC 25 | Feb 08 09:39:25 AM UTC 25 | 315676850400 ps | ||
| T381 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/46.rv_timer_random_reset.127404069 | Feb 08 09:38:59 AM UTC 25 | Feb 08 09:39:30 AM UTC 25 | 18568737867 ps | ||
| T230 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all.1701145087 | Feb 08 09:29:09 AM UTC 25 | Feb 08 09:39:33 AM UTC 25 | 400836129976 ps | ||
| T232 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/45.rv_timer_random.12192896 | Feb 08 09:38:36 AM UTC 25 | Feb 08 09:39:44 AM UTC 25 | 33652945555 ps | ||
| T212 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/43.rv_timer_random.3810929311 | Feb 08 09:36:57 AM UTC 25 | Feb 08 09:39:59 AM UTC 25 | 227726327152 ps | ||
| T190 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/29.rv_timer_cfg_update_on_fly.2434659095 | Feb 08 09:27:01 AM UTC 25 | Feb 08 09:40:04 AM UTC 25 | 1275341392080 ps | ||
| T259 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/45.rv_timer_cfg_update_on_fly.2239040815 | Feb 08 09:38:37 AM UTC 25 | Feb 08 09:40:08 AM UTC 25 | 90857435043 ps | ||
| T279 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/44.rv_timer_random_reset.2804543168 | Feb 08 09:38:04 AM UTC 25 | Feb 08 09:40:24 AM UTC 25 | 91105235970 ps | ||
| T347 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/38.rv_timer_cfg_update_on_fly.2762375844 | Feb 08 09:33:11 AM UTC 25 | Feb 08 09:40:25 AM UTC 25 | 628683796783 ps | ||
| T436 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all.2365334875 | Feb 08 09:37:42 AM UTC 25 | Feb 08 09:40:32 AM UTC 25 | 203497779065 ps | ||
| T332 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/44.rv_timer_random.4052077189 | Feb 08 09:37:42 AM UTC 25 | Feb 08 09:40:32 AM UTC 25 | 111585790654 ps | ||
| T54 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all.619824984 | Feb 08 09:27:07 AM UTC 25 | Feb 08 09:40:36 AM UTC 25 | 996109128628 ps | ||
| T437 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/49.rv_timer_random_reset.2622122044 | Feb 08 09:40:37 AM UTC 25 | Feb 08 09:40:57 AM UTC 25 | 10873579745 ps | ||
| T178 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/45.rv_timer_random_reset.2889438690 | Feb 08 09:38:41 AM UTC 25 | Feb 08 09:41:03 AM UTC 25 | 46416197592 ps | ||
| T438 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/49.rv_timer_disabled.891776368 | Feb 08 09:40:32 AM UTC 25 | Feb 08 09:41:08 AM UTC 25 | 17857765537 ps | ||
| T306 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/36.rv_timer_random.2103862628 | Feb 08 09:30:51 AM UTC 25 | Feb 08 09:41:10 AM UTC 25 | 129283912465 ps | ||
| T233 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/40.rv_timer_random_reset.1580280037 | Feb 08 09:34:52 AM UTC 25 | Feb 08 09:41:12 AM UTC 25 | 87358377633 ps | ||
| T174 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/48.rv_timer_cfg_update_on_fly.1839413126 | Feb 08 09:40:01 AM UTC 25 | Feb 08 09:41:31 AM UTC 25 | 94767780319 ps | ||
| T193 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/19.rv_timer_random.1171425895 | Feb 08 09:21:20 AM UTC 25 | Feb 08 09:41:47 AM UTC 25 | 329148834799 ps | ||
| T333 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/34.rv_timer_random_reset.508215625 | Feb 08 09:30:13 AM UTC 25 | Feb 08 09:41:53 AM UTC 25 | 263651008010 ps | ||
| T172 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/47.rv_timer_random.4001963842 | Feb 08 09:39:17 AM UTC 25 | Feb 08 09:41:55 AM UTC 25 | 91290224812 ps | ||
| T439 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/47.rv_timer_disabled.980468314 | Feb 08 09:39:18 AM UTC 25 | Feb 08 09:42:03 AM UTC 25 | 186902143546 ps | ||
| T440 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/44.rv_timer_disabled.3051958191 | Feb 08 09:37:46 AM UTC 25 | Feb 08 09:42:11 AM UTC 25 | 301948730839 ps | ||
| T34 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all_with_rand_reset.3795516888 | Feb 08 09:27:59 AM UTC 25 | Feb 08 09:42:25 AM UTC 25 | 100863386260 ps | ||
| T301 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/48.rv_timer_random_reset.2209813519 | Feb 08 09:40:05 AM UTC 25 | Feb 08 09:42:34 AM UTC 25 | 86141427321 ps | ||
| T176 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all.1178919619 | Feb 08 09:17:41 AM UTC 25 | Feb 08 09:43:12 AM UTC 25 | 2859474288865 ps | ||
| T237 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all.3082922607 | Feb 08 09:23:25 AM UTC 25 | Feb 08 09:43:18 AM UTC 25 | 3726488307377 ps | ||
| T374 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/42.rv_timer_random_reset.1471902809 | Feb 08 09:36:51 AM UTC 25 | Feb 08 09:43:27 AM UTC 25 | 960352027110 ps | ||
| T238 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/49.rv_timer_random.2215134291 | Feb 08 09:40:26 AM UTC 25 | Feb 08 09:43:38 AM UTC 25 | 64575176437 ps | ||
| T262 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/66.rv_timer_random.2172840884 | Feb 08 09:43:28 AM UTC 25 | Feb 08 09:43:51 AM UTC 25 | 21969290187 ps | ||
| T205 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/43.rv_timer_random_reset.2181397192 | Feb 08 09:37:12 AM UTC 25 | Feb 08 09:43:57 AM UTC 25 | 47213525842 ps | ||
| T35 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all_with_rand_reset.2931806860 | Feb 08 09:38:25 AM UTC 25 | Feb 08 09:44:08 AM UTC 25 | 286609512233 ps | ||
| T56 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/31.rv_timer_random.2101089669 | Feb 08 09:28:18 AM UTC 25 | Feb 08 09:44:10 AM UTC 25 | 114227611247 ps | ||
| T57 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/47.rv_timer_random_reset.2331075588 | Feb 08 09:39:26 AM UTC 25 | Feb 08 09:44:17 AM UTC 25 | 7717631193 ps | ||
| T58 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/62.rv_timer_random.1000786259 | Feb 08 09:42:35 AM UTC 25 | Feb 08 09:44:44 AM UTC 25 | 155142782261 ps | ||
| T59 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all.798834060 | Feb 08 09:28:18 AM UTC 25 | Feb 08 09:44:56 AM UTC 25 | 581382766212 ps | ||
| T36 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all_with_rand_reset.1211482596 | Feb 08 09:28:38 AM UTC 25 | Feb 08 09:45:04 AM UTC 25 | 148981386760 ps | ||
| T60 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/48.rv_timer_disabled.1596372809 | Feb 08 09:39:53 AM UTC 25 | Feb 08 09:45:25 AM UTC 25 | 128331504975 ps | ||
| T61 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/74.rv_timer_random.1672222995 | Feb 08 09:44:46 AM UTC 25 | Feb 08 09:45:37 AM UTC 25 | 14431101684 ps | ||
| T62 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/57.rv_timer_random.1372247435 | Feb 08 09:41:56 AM UTC 25 | Feb 08 09:45:51 AM UTC 25 | 284136616047 ps | ||
| T63 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/46.rv_timer_random.3657116099 | Feb 08 09:38:57 AM UTC 25 | Feb 08 09:45:52 AM UTC 25 | 272163688381 ps | ||
| T167 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all.2292062139 | Feb 08 09:40:57 AM UTC 25 | Feb 08 09:46:01 AM UTC 25 | 40535549555 ps | ||
| T299 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/53.rv_timer_random.3195937467 | Feb 08 09:41:13 AM UTC 25 | Feb 08 09:46:15 AM UTC 25 | 593077282180 ps | ||
| T338 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/67.rv_timer_random.1524253352 | Feb 08 09:43:39 AM UTC 25 | Feb 08 09:46:18 AM UTC 25 | 40975305805 ps | ||
| T227 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/51.rv_timer_random.2121655695 | Feb 08 09:41:09 AM UTC 25 | Feb 08 09:46:21 AM UTC 25 | 483098875042 ps | ||
| T224 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/65.rv_timer_random.2587043185 | Feb 08 09:43:19 AM UTC 25 | Feb 08 09:46:23 AM UTC 25 | 58453082494 ps | ||
| T367 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/81.rv_timer_random.279572280 | Feb 08 09:46:01 AM UTC 25 | Feb 08 09:46:29 AM UTC 25 | 27579121157 ps | ||
| T156 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/48.rv_timer_random.2593263946 | Feb 08 09:39:44 AM UTC 25 | Feb 08 09:46:43 AM UTC 25 | 137084417687 ps | ||
| T55 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all.3166691865 | Feb 08 09:25:20 AM UTC 25 | Feb 08 09:47:10 AM UTC 25 | 1230123359469 ps | ||
| T152 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/56.rv_timer_random.433088195 | Feb 08 09:41:54 AM UTC 25 | Feb 08 09:47:32 AM UTC 25 | 320641597955 ps | ||
| T275 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/58.rv_timer_random.3266175172 | Feb 08 09:42:04 AM UTC 25 | Feb 08 09:47:42 AM UTC 25 | 215035228167 ps | ||
| T191 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/41.rv_timer_cfg_update_on_fly.1839648169 | Feb 08 09:35:41 AM UTC 25 | Feb 08 09:47:52 AM UTC 25 | 1075676944519 ps | ||
| T302 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/70.rv_timer_random.4026498874 | Feb 08 09:44:04 AM UTC 25 | Feb 08 09:47:56 AM UTC 25 | 121818701667 ps | ||
| T284 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/54.rv_timer_random.3450652848 | Feb 08 09:41:33 AM UTC 25 | Feb 08 09:48:33 AM UTC 25 | 111605400648 ps | ||
| T309 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/82.rv_timer_random.429072654 | Feb 08 09:46:15 AM UTC 25 | Feb 08 09:48:48 AM UTC 25 | 55333549350 ps | ||
| T304 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/55.rv_timer_random.3420924839 | Feb 08 09:41:48 AM UTC 25 | Feb 08 09:48:49 AM UTC 25 | 86089669735 ps |
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