| | | | | | | |
| tb |
99.62 |
99.36 |
98.73 |
100.00 |
|
100.00 |
100.00 |
| dut |
99.62 |
99.36 |
98.73 |
100.00 |
|
100.00 |
100.00 |
| gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
| gen_harts[0].u_core |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_harts[0].u_intr_hw |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| rv_timer_csr_assert |
100.00 |
|
|
|
|
|
100.00 |
| tlul_assert_device |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
| u_reg |
99.71 |
99.24 |
99.29 |
100.00 |
|
100.00 |
100.00 |
| u_alert_test |
100.00 |
100.00 |
|
|
|
|
|
| u_cfg0_prescale |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_cfg0_step |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_chk |
100.00 |
100.00 |
|
100.00 |
|
|
100.00 |
| u_chk |
100.00 |
|
|
100.00 |
|
|
|
| u_tlul_data_integ_dec |
100.00 |
100.00 |
|
100.00 |
|
|
|
| u_data_chk |
100.00 |
|
|
100.00 |
|
|
|
| u_compare_lower0_0 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_compare_lower0_00_qe |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_compare_upper0_0 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_compare_upper0_00_qe |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_ctrl |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_intr_enable0 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_intr_state0 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
| u_intr_test0 |
100.00 |
100.00 |
|
|
|
|
|
| u_prim_reg_we_check |
100.00 |
100.00 |
|
100.00 |
|
|
|
| u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| u_prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
| u_reg_if |
98.67 |
97.14 |
97.53 |
|
|
100.00 |
100.00 |
| u_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| u_rsp_intg_gen |
83.33 |
66.67 |
|
|
|
|
100.00 |
| u_rsp_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
| gen_data_intg.u_tlul_data_integ_enc |
100.00 |
100.00 |
|
|
|
|
|
| u_data_gen |
100.00 |
100.00 |
|
|
|
|
|
| gen_rsp_intg.u_rsp_gen |
100.00 |
100.00 |
|
|
|
|
|
| u_timer_v_lower0 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_timer_v_upper0 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|