Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0}

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 7 0 7 100.00
Crosses 6 0 6 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0}
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_intr 1 0 1 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 6 0 6 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1131 1 T11 7 T12 40 T13 27


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 582 1 T11 3 T12 20 T13 16
auto[1] 549 1 T11 4 T12 20 T13 11


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 408 1 T11 3 T12 10 T13 9
auto[1] 723 1 T11 4 T12 30 T13 18


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 635 1 T11 4 T12 17 T13 14
auto[1] 496 1 T11 3 T12 23 T13 13


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intr   cp_intr_test   cp_intr_en   cp_intr_state   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] auto[0] auto[0] auto[0] 228 1 T11 3 T12 6 T13 6
all_values[0] auto[0] auto[0] auto[1] 116 1 T12 3 T13 2 T382 2
all_values[0] auto[0] auto[1] auto[0] 180 1 T12 4 T13 3 T383 8
all_values[0] auto[0] auto[1] auto[1] 111 1 T11 1 T12 4 T13 3
all_values[0] auto[1] auto[0] auto[1] 238 1 T12 11 T13 8 T383 2
all_values[0] auto[1] auto[1] auto[1] 258 1 T11 3 T12 12 T13 5


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal