Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
2309 |
1 |
|
T1 |
9 |
|
T2 |
10 |
|
T8 |
83 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1231 |
1 |
|
T1 |
5 |
|
T2 |
2 |
|
T8 |
50 |
auto[1] |
1078 |
1 |
|
T1 |
4 |
|
T2 |
8 |
|
T8 |
33 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
826 |
1 |
|
T1 |
3 |
|
T2 |
3 |
|
T8 |
25 |
auto[1] |
1483 |
1 |
|
T1 |
6 |
|
T2 |
7 |
|
T8 |
58 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1308 |
1 |
|
T1 |
3 |
|
T2 |
6 |
|
T8 |
44 |
auto[1] |
1001 |
1 |
|
T1 |
6 |
|
T2 |
4 |
|
T8 |
39 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
466 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
17 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
232 |
1 |
|
T8 |
11 |
|
T9 |
1 |
|
T30 |
5 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
360 |
1 |
|
T1 |
2 |
|
T2 |
2 |
|
T8 |
8 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
250 |
1 |
|
T2 |
3 |
|
T8 |
8 |
|
T9 |
2 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
533 |
1 |
|
T1 |
4 |
|
T2 |
1 |
|
T8 |
22 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
468 |
1 |
|
T1 |
2 |
|
T2 |
3 |
|
T8 |
17 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |