SPI_DEVICE Simulation Results

Tuesday May 16 2023 07:02:31 UTC

GitHub Revision: `50278df8b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 1341560578

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke	1.300s	72.693us	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.540s	54.478us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.070s	130.465us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.010s	1.176ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	19.180s	908.710us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.590s	43.125us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.070s	130.465us	20	20	100.00
		spi_device_csr_aliasing	19.180s	908.710us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	13.820s	688.998us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	6.990s	402.309us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	base_random_seq	spi_device_txrx	29.920m	345.783ms	50	50	100.00
V2	fifo_full	spi_device_fifo_full	56.017m	57.069ms	50	50	100.00
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow	36.583m	326.734ms	48	50	96.00
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly	48.460m	452.359ms	50	50	100.00
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly	48.460m	452.359ms	50	50	100.00
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset	0.800s	50.496us	50	50	100.00
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset	0.970s	53.219us	50	50	100.00
V2	interrupts	spi_device_intr	1.530m	40.967ms	49	50	98.00
V2	abort	spi_device_abort	0.800s	13.926us	50	50	100.00
V2	byte_transfer_on_spi	spi_device_byte_transfer	3.500s	285.607us	50	50	100.00
V2	rx_timeout	spi_device_rx_timeout	7.490s	1.044ms	50	50	100.00
V2	bit_transfer_on_spi	spi_device_bit_transfer	3.470s	400.454us	50	50	100.00
V2	extreme_fifo_setting	spi_device_extreme_fifo_size	1.104h	325.562ms	50	50	100.00
V2	perf	spi_device_perf	55.939m	238.752ms	50	50	100.00
V2	csb_read	spi_device_csb_read	0.840s	40.754us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.110s	117.155us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.860s	43.325us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	10.190s	1.239ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.190s	1.239ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	37.100s	15.814ms	50	50	100.00
		spi_device_tpm_sts_read	1.220s	151.720us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	4.507m	118.982ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	41.330s	15.973ms	50	50	100.00
		spi_device_flash_all	5.089m	266.291ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	45.840s	16.857ms	50	50	100.00
		spi_device_flash_all	5.089m	266.291ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	45.840s	16.857ms	50	50	100.00
		spi_device_flash_all	5.089m	266.291ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.089m	266.291ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	14.140s	4.741ms	50	50	100.00
		spi_device_flash_all	5.089m	266.291ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	14.140s	4.741ms	50	50	100.00
		spi_device_flash_all	5.089m	266.291ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	14.140s	4.741ms	50	50	100.00
		spi_device_flash_all	5.089m	266.291ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	14.140s	4.741ms	50	50	100.00
		spi_device_flash_all	5.089m	266.291ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	41.400s	10.608ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	54.890s	20.815ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	54.890s	20.815ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	54.890s	20.815ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.109m	48.153ms	49	50	98.00
		spi_device_read_buffer_direct	8.220s	1.815ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	54.890s	20.815ms	50	50	100.00
		spi_device_flash_all	5.089m	266.291ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.089m	266.291ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.089m	266.291ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	12.490s	9.942ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	12.490s	9.942ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.974m	102.092ms	48	50	96.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.517m	132.636ms	47	50	94.00
V2	stress_all	spi_device_stress_all	1.069h	191.006ms	19	50	38.00
V2	alert_test	spi_device_alert_test	0.790s	124.392us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	12.959us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.910s	475.508us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.910s	475.508us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.540s	54.478us	5	5	100.00
		spi_device_csr_rw	3.070s	130.465us	20	20	100.00
		spi_device_csr_aliasing	19.180s	908.710us	5	5	100.00
		spi_device_same_csr_outstanding	4.280s	65.168us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.540s	54.478us	5	5	100.00
		spi_device_csr_rw	3.070s	130.465us	20	20	100.00
		spi_device_csr_aliasing	19.180s	908.710us	5	5	100.00
		spi_device_same_csr_outstanding	4.280s	65.168us	20	20	100.00
V2		TOTAL			1640	1680	97.62
V2S	tl_intg_err	spi_device_sec_cm	1.450s	268.614us	5	5	100.00
		spi_device_tl_intg_err	22.430s	2.099ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.430s	2.099ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1780	1820	97.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	36	36	30	83.33
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.94	99.01	96.23	98.63	92.06	97.95	96.16	98.54

Failure Buckets

UVM_ERROR (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch has 27 failures:

Test spi_device_stress_all has 27 failures.

0.spi_device_stress_all.2781685364
Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 58123078649 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x98 [10011000] vs 0x31 [110001]) addr 0xd10f098 read out mismatch
  UVM_ERROR @ 58123078649 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x77 [1110111] vs 0xa [1010]) addr 0xd10f099 read out mismatch
  UVM_ERROR @ 58123078649 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x10 [10000] vs 0xc5 [11000101]) addr 0xd10f09a read out mismatch
  UVM_ERROR @ 58123078649 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x49 [1001001] vs 0x4 [100]) addr 0xd10f09b read out mismatch
  UVM_ERROR @ 58123453652 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x1d [11101] vs 0xfb [11111011]) addr 0xd10f09c read out mismatch

2.spi_device_stress_all.2635950395
Line 218, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/2.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 45263226811 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xd [1101] vs 0xe3 [11100011]) addr 0xbf429024 read out mismatch
  UVM_ERROR @ 45263226811 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x19 [11001] vs 0xd7 [11010111]) addr 0xbf429025 read out mismatch
  UVM_ERROR @ 45263226811 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x94 [10010100] vs 0xf8 [11111000]) addr 0xbf429026 read out mismatch
  UVM_ERROR @ 45263226811 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x4 [100] vs 0xa2 [10100010]) addr 0xbf429027 read out mismatch
  UVM_ERROR @ 45350926811 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xad [10101101] vs 0xa [1010]) addr 0xbf429028 read out mismatch

... and 25 more failures.

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem. has 3 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

25.spi_device_flash_and_tpm_min_idle.4060860019
Line 221, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_WARNING @ 3952585679 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3952585679 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3952585679 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3952585679 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3952585679 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

Test spi_device_stress_all has 1 failures.

25.spi_device_stress_all.2517062871
Line 225, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/25.spi_device_stress_all/latest/run.log

  UVM_WARNING @ 12288421737 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 12288421737 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 12288421737 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 12288421737 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 12288421737 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

Test spi_device_flash_and_tpm has 1 failures.

33.spi_device_flash_and_tpm.2034173309
Line 222, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/33.spi_device_flash_and_tpm/latest/run.log

  UVM_WARNING @ 2380627215 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 2380627215 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 2380627215 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 2380627215 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 2380627215 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

UVM_ERROR (spi_device_scoreboard.sv:1071) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 2 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

21.spi_device_flash_and_tpm_min_idle.2432510902
Line 217, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 1350398655 ps: (spi_device_scoreboard.sv:1071) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 6175478655 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 2/7
  UVM_INFO @ 7295798655 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 1/3
  UVM_INFO @ 12646478655 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 2/3
  UVM_INFO @ 15092078655 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 3/7

Test spi_device_flash_and_tpm has 1 failures.

29.spi_device_flash_and_tpm.3382171319
Line 230, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/29.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 18681650382 ps: (spi_device_scoreboard.sv:1071) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 19570058070 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/9
  UVM_INFO @ 21204158183 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 8/8
  UVM_INFO @ 21949067276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:365) [spi_device_intr_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 2 failures:

Test spi_device_stress_all has 2 failures.

23.spi_device_stress_all.1278104810
Line 231, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/23.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 51773129823 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 51773229823 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 51776979823 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.rxf_empty reset value: 0x1
  UVM_ERROR @ 51778250323 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 16 [0x10])
  UVM_ERROR @ 51778379823 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16 [0x10]) Regname: spi_device_reg_block.intr_state reset value: 0x0

37.spi_device_stress_all.1127641400
Line 241, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/37.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 271093507094 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 271094028830 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 271101028788 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.rxf_empty reset value: 0x1
  UVM_ERROR @ 271102816823 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 16 [0x10])
  UVM_ERROR @ 271103507034 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16 [0x10]) Regname: spi_device_reg_block.intr_state reset value: 0x0

UVM_FATAL (spi_device_base_vseq.sv:410) [spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail has 1 failures:
- Test spi_device_stress_all has 1 failures.
  - 14.spi_device_stress_all.1775033570
    Line 225, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/14.spi_device_stress_all/latest/run.log
```
  UVM_FATAL @ 398074195487 ps: (spi_device_base_vseq.sv:410) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail
  UVM_INFO @ 398074195487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: * has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

15.spi_device_flash_and_tpm_min_idle.3861194331
Line 231, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 31870935997 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 35528839997 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 8/13
  UVM_INFO @ 38652985997 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 9/18
  UVM_INFO @ 40381852997 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 9/13
  UVM_INFO @ 44986585997 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 10/18

UVM_ERROR (spi_device_scoreboard.sv:1071) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 34.spi_device_flash_mode.4043913693
    Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/34.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 721049173 ps: (spi_device_scoreboard.sv:1071) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 1365257127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (spi_device_base_vseq.sv:410) [spi_device_fifo_underflow_overflow_vseq] wait_for_rx_avail_bytes::SramDataAvail has 1 failures:
- Test spi_device_fifo_underflow_overflow has 1 failures.
  - 39.spi_device_fifo_underflow_overflow.3449912736
    Line 219, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/39.spi_device_fifo_underflow_overflow/latest/run.log
```
  UVM_FATAL @ 154911881664 ps: (spi_device_base_vseq.sv:410) [uvm_test_top.env.virtual_sequencer.spi_device_fifo_underflow_overflow_vseq] wait_for_rx_avail_bytes::SramDataAvail
  UVM_INFO @ 154911881664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_fifo_underflow_overflow has 1 failures.
  - 41.spi_device_fifo_underflow_overflow.2905008520
    Line 221, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/41.spi_device_fifo_underflow_overflow/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.status.txf_full reset value: * has 1 failures:

Test spi_device_intr has 1 failures.

48.spi_device_intr.3973071355
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/48.spi_device_intr/latest/run.log

  UVM_ERROR @ 10825852698 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.txf_full reset value: 0x0
  UVM_INFO @ 10837977795 ps: (spi_device_intr_vseq.sv:43) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq]
  Testing RxFifoFull
  UVM_INFO @ 11381940480 ps: (spi_device_intr_vseq.sv:43) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq]
  Testing TxFifoUnderflow