---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.InterceptLevel_M	0	0	410131124	0	0	0
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.LockArbDecision_A	0	0	1572941229	0	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A	0	0	1572941229	0	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M	0	0	1572941229	0	0	0
tb.dut.u_rx_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_sram_clk_scan.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_sram_rst_scanmux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.LockArbDecision_A	0	0	1924208418	0	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A	0	0	1924208418	0	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M	0	0	1924208418	0	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	1924208418	0	0	1631
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_tx_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_txf_underflow.DstPulseCheck_A	0	0	1543171530	0	0	0
tb.dut.u_txf_underflow.SrcPulseCheck_M	0	0	325571447	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.LockArbDecision_A	0	0	410129881	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A	0	0	410129881	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M	0	0	410129881	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	410129881	0	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.DataKnown_A	0	0	410129881	0	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	410129881	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertKnownO_A	0	0	1924208418	1924072880	0	0
tb.dut.CioSdoEnOKnown	0	0	1924208418	1924072880	0	0
tb.dut.CioSdoEnOffWhenInactive	0	0	1924208418	1924072880	0	0
tb.dut.CsPulseWidth_A	0	0	1924208418	1834542114	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	1924208418	90	0	0
tb.dut.IntrReadbufFlipOKnown	0	0	1924208418	1924072880	0	0
tb.dut.IntrReadbufWatermarkOKnown	0	0	1924208418	1924072880	0	0
tb.dut.IntrRxerrOKnown	0	0	1924208418	1924072880	0	0
tb.dut.IntrRxfOKnown	0	0	1924208418	1924072880	0	0
tb.dut.IntrRxlvlOKnown	0	0	1924208418	1924072880	0	0
tb.dut.IntrRxoverflowOKnown	0	0	1924208418	1924072880	0	0
tb.dut.IntrTpmHeaderNotEmptyOKnown	0	0	1924208418	1924072880	0	0
tb.dut.IntrTxlvlOKnown	0	0	1924208418	1924072880	0	0
tb.dut.IntrTxunderflowOKnown	0	0	1924208418	1924072880	0	0
tb.dut.IntrUploadCmdfifoNotEmptyOKnown	0	0	1924208418	1924072880	0	0
tb.dut.IntrUploadPayloadNotEmptyOKnown	0	0	1924208418	1924072880	0	0
tb.dut.IntrUploadPayloadOverflowOKnown	0	0	1924208418	1924072880	0	0
tb.dut.PayloadStartIdxWidthMatch_A	0	0	1631	1631	0	0
tb.dut.SpiModeKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.TpmEnableWhenTpmCsbIdle_M	0	0	1924208418	353	0	0
tb.dut.TpmRdfifoNotFull_A	0	0	1924208418	283762	0	0
tb.dut.TpmWrPtrMatch_A	0	0	1631	1631	0	0
tb.dut.g_sram_connect[0].ReqAlwaysAccepted_A	0	0	1924208418	11836851	0	0
tb.dut.g_sram_connect[1].ReqAlwaysAccepted_A	0	0	1924208418	2528	0	0
tb.dut.g_sram_connect[2].ReqAlwaysAccepted_A	0	0	1924208418	1889	0	0
tb.dut.scanmodeKnown	0	0	1924208418	1924208418	0	0
tb.dut.spi_device_csr_assert.TlulOOBAddrErr_A	0	0	1926351399	7711	0	0
tb.dut.spi_device_csr_assert.addr_swap_data_rd_A	0	0	1926351399	850	0	0
tb.dut.spi_device_csr_assert.addr_swap_mask_rd_A	0	0	1926351399	954	0	0
tb.dut.spi_device_csr_assert.cmd_filter_0_rd_A	0	0	1926351399	9421	0	0
tb.dut.spi_device_csr_assert.cmd_filter_1_rd_A	0	0	1926351399	10758	0	0
tb.dut.spi_device_csr_assert.cmd_filter_2_rd_A	0	0	1926351399	8920	0	0
tb.dut.spi_device_csr_assert.cmd_filter_3_rd_A	0	0	1926351399	11459	0	0
tb.dut.spi_device_csr_assert.cmd_filter_4_rd_A	0	0	1926351399	10148	0	0
tb.dut.spi_device_csr_assert.cmd_filter_5_rd_A	0	0	1926351399	9833	0	0
tb.dut.spi_device_csr_assert.cmd_filter_6_rd_A	0	0	1926351399	8819	0	0
tb.dut.spi_device_csr_assert.cmd_filter_7_rd_A	0	0	1926351399	11352	0	0
tb.dut.spi_device_csr_assert.cmd_info_0_rd_A	0	0	1926351399	4053	0	0
tb.dut.spi_device_csr_assert.cmd_info_10_rd_A	0	0	1926351399	4694	0	0
tb.dut.spi_device_csr_assert.cmd_info_11_rd_A	0	0	1926351399	3790	0	0
tb.dut.spi_device_csr_assert.cmd_info_12_rd_A	0	0	1926351399	4424	0	0
tb.dut.spi_device_csr_assert.cmd_info_13_rd_A	0	0	1926351399	4295	0	0
tb.dut.spi_device_csr_assert.cmd_info_14_rd_A	0	0	1926351399	4367	0	0
tb.dut.spi_device_csr_assert.cmd_info_15_rd_A	0	0	1926351399	4346	0	0
tb.dut.spi_device_csr_assert.cmd_info_16_rd_A	0	0	1926351399	3790	0	0
tb.dut.spi_device_csr_assert.cmd_info_17_rd_A	0	0	1926351399	3846	0	0
tb.dut.spi_device_csr_assert.cmd_info_18_rd_A	0	0	1926351399	4065	0	0
tb.dut.spi_device_csr_assert.cmd_info_19_rd_A	0	0	1926351399	4041	0	0
tb.dut.spi_device_csr_assert.cmd_info_1_rd_A	0	0	1926351399	3778	0	0
tb.dut.spi_device_csr_assert.cmd_info_20_rd_A	0	0	1926351399	4270	0	0
tb.dut.spi_device_csr_assert.cmd_info_21_rd_A	0	0	1926351399	4333	0	0
tb.dut.spi_device_csr_assert.cmd_info_22_rd_A	0	0	1926351399	4011	0	0
tb.dut.spi_device_csr_assert.cmd_info_23_rd_A	0	0	1926351399	4329	0	0
tb.dut.spi_device_csr_assert.cmd_info_2_rd_A	0	0	1926351399	4265	0	0
tb.dut.spi_device_csr_assert.cmd_info_3_rd_A	0	0	1926351399	4192	0	0
tb.dut.spi_device_csr_assert.cmd_info_4_rd_A	0	0	1926351399	4067	0	0
tb.dut.spi_device_csr_assert.cmd_info_5_rd_A	0	0	1926351399	4266	0	0
tb.dut.spi_device_csr_assert.cmd_info_6_rd_A	0	0	1926351399	4508	0	0
tb.dut.spi_device_csr_assert.cmd_info_7_rd_A	0	0	1926351399	3699	0	0
tb.dut.spi_device_csr_assert.cmd_info_8_rd_A	0	0	1926351399	3872	0	0
tb.dut.spi_device_csr_assert.cmd_info_9_rd_A	0	0	1926351399	4321	0	0
tb.dut.spi_device_csr_assert.cmd_info_en4b_rd_A	0	0	1926351399	1046	0	0
tb.dut.spi_device_csr_assert.cmd_info_ex4b_rd_A	0	0	1926351399	1060	0	0
tb.dut.spi_device_csr_assert.cmd_info_wrdi_rd_A	0	0	1926351399	1192	0	0
tb.dut.spi_device_csr_assert.cmd_info_wren_rd_A	0	0	1926351399	1083	0	0
tb.dut.spi_device_csr_assert.control_rd_A	0	0	1926351399	2113	0	0
tb.dut.spi_device_csr_assert.fifo_level_rd_A	0	0	1926351399	1037	0	0
tb.dut.spi_device_csr_assert.intercept_en_rd_A	0	0	1926351399	1621	0	0
tb.dut.spi_device_csr_assert.intr_enable_rd_A	0	0	1926351399	4645	0	0
tb.dut.spi_device_csr_assert.jedec_cc_rd_A	0	0	1926351399	1068	0	0
tb.dut.spi_device_csr_assert.jedec_id_rd_A	0	0	1926351399	1237	0	0
tb.dut.spi_device_csr_assert.mailbox_addr_rd_A	0	0	1926351399	694	0	0
tb.dut.spi_device_csr_assert.payload_swap_data_rd_A	0	0	1926351399	788	0	0
tb.dut.spi_device_csr_assert.payload_swap_mask_rd_A	0	0	1926351399	866	0	0
tb.dut.spi_device_csr_assert.read_threshold_rd_A	0	0	1926351399	763	0	0
tb.dut.spi_device_csr_assert.rxf_addr_rd_A	0	0	1926351399	997	0	0
tb.dut.spi_device_csr_assert.tpm_access_0_rd_A	0	0	1926351399	1772	0	0
tb.dut.spi_device_csr_assert.tpm_access_1_rd_A	0	0	1926351399	868	0	0
tb.dut.spi_device_csr_assert.tpm_cfg_rd_A	0	0	1926351399	1856	0	0
tb.dut.spi_device_csr_assert.tpm_did_vid_rd_A	0	0	1926351399	1170	0	0
tb.dut.spi_device_csr_assert.tpm_int_enable_rd_A	0	0	1926351399	931	0	0
tb.dut.spi_device_csr_assert.tpm_int_status_rd_A	0	0	1926351399	806	0	0
tb.dut.spi_device_csr_assert.tpm_int_vector_rd_A	0	0	1926351399	817	0	0
tb.dut.spi_device_csr_assert.tpm_intf_capability_rd_A	0	0	1926351399	751	0	0
tb.dut.spi_device_csr_assert.tpm_rid_rd_A	0	0	1926351399	714	0	0
tb.dut.spi_device_csr_assert.tpm_sts_rd_A	0	0	1926351399	815	0	0
tb.dut.spi_device_csr_assert.txf_addr_rd_A	0	0	1926351399	1112	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	1926351399	260166450	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	1926351399	1926169920	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	1926351399	286890705	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	1926351399	1926169920	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
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tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1806	1806	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	1926352527	16562616	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	1926351399	7659	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	1926352527	251514576	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	1926352527	262080498	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	1926351399	7110	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	1926352527	260166459	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	1926352527	286890709	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	1926352527	260166459	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	1926352527	286890709	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	1926352527	286890709	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	1926352527	286890709	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	1926351399	6010	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	1926351399	7070	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1806	1806	0	0
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown0	0	0	596204	594573	0	0
tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic.selKnown0	0	0	410130539	410128908	0	0
tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic.selKnown1	0	0	410129260	410127824	0	0
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown0	0	0	410129881	410128418	0	0
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown0	0	0	410131121	410129490	0	0
tb.dut.u_cmdparse.CmdOnlySelDpKnown_A	0	0	410129881	348509318	0	0
tb.dut.u_cmdparse.OnlyOneDatapath_A	0	0	410129881	79792	0	0
tb.dut.u_cmdparse.SelDpKnown_A	0	0	410129881	348509318	0	0
tb.dut.u_cmdparse.StKnown_A	0	0	410129881	348509318	0	0
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	594573	593287	0	0
tb.dut.u_flash_readbuf_flip_pulse_sync.DstPulseCheck_A	0	0	1924208418	613	0	0
tb.dut.u_flash_readbuf_flip_pulse_sync.SrcPulseCheck_M	0	0	410129881	613	0	0
tb.dut.u_flash_readbuf_watermark_pulse_sync.DstPulseCheck_A	0	0	1924208418	429	0	0
tb.dut.u_flash_readbuf_watermark_pulse_sync.SrcPulseCheck_M	0	0	410129881	429	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.CheckHotOne_A	0	0	1572941229	1526369371	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A	0	0	1631	1631	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.GntImpliesReady_A	0	0	1572941229	9055677	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.GntImpliesValid_A	0	0	1572941229	9055677	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.GrantKnown_A	0	0	1572941229	1526369371	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.IdxKnown_A	0	0	1572941229	1526369371	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.IndexIsCorrect_A	0	0	1572941229	9055677	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A	0	0	1572941229	9055677	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A	0	0	1572941229	9055677	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.ReqImpliesValid_A	0	0	1572941229	9055677	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	1572941229	1513	0	716
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.ValidKnown_A	0	0	1572941229	1526369371	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A	0	0	1572941229	9055677	0	0
tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo.DataKnown_A	0	0	1572941229	4409756	0	0
tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo.DepthKnown_A	0	0	1572941229	1526369371	0	0
tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo.RvalidKnown_A	0	0	1572941229	1526369371	0	0
tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo.WreadyKnown_A	0	0	1572941229	1526369371	0	0
tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	1572941229	4409756	0	0
tb.dut.u_fwmode.u_rx_fifo.GrayRptr_A	0	0	1572941229	1572934437	0	0
tb.dut.u_fwmode.u_rx_fifo.GrayWptr_A	0	0	410129881	410128307	0	0
tb.dut.u_fwmode.u_rx_fifo.ParamCheckDepth_A	0	0	1631	1631	0	0
tb.dut.u_fwmode.u_tx_fifo.GrayRptr_A	0	0	410131121	410127990	0	0
tb.dut.u_fwmode.u_tx_fifo.GrayWptr_A	0	0	1572941229	1572934404	0	0
tb.dut.u_fwmode.u_tx_fifo.ParamCheckDepth_A	0	0	1631	1631	0	0
tb.dut.u_intr_cmdfifo_not_empty.IntrTKind_A	0	0	1631	1631	0	0
tb.dut.u_intr_payload_not_empty.IntrTKind_A	0	0	1631	1631	0	0
tb.dut.u_intr_payload_overflow.IntrTKind_A	0	0	1631	1631	0	0
tb.dut.u_intr_readbuf_flip.IntrTKind_A	0	0	1631	1631	0	0
tb.dut.u_intr_readbuf_watermark.IntrTKind_A	0	0	1631	1631	0	0
tb.dut.u_intr_rxerr.IntrTKind_A	0	0	1631	1631	0	0
tb.dut.u_intr_rxf.IntrTKind_A	0	0	1631	1631	0	0
tb.dut.u_intr_rxlvl.IntrTKind_A	0	0	1631	1631	0	0
tb.dut.u_intr_rxoverflow.IntrTKind_A	0	0	1631	1631	0	0
tb.dut.u_intr_tpm_cmdaddr_notempty.IntrTKind_A	0	0	1631	1631	0	0
tb.dut.u_intr_txlvl.IntrTKind_A	0	0	1631	1631	0	0
tb.dut.u_intr_txunderflow.IntrTKind_A	0	0	1631	1631	0	0
tb.dut.u_jedec.JedecStKnown_A	0	0	410129881	348509318	0	0
tb.dut.u_memory_2p.CannotHaveEccAndParity_A	0	0	1631	1631	0	0
tb.dut.u_memory_2p.gen_byte_parity.ParityNeedsByteWriteMask_A	0	0	1631	1631	0	0
tb.dut.u_memory_2p.gen_byte_parity.WidthNeedsToBeByteAligned_A	0	0	1631	1631	0	0
tb.dut.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheckPortA_A	0	0	1924208418	7146653	0	0
tb.dut.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheckPortB_A	0	0	1572941229	5352124	0	0
tb.dut.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[1].MaskCheckPortA_A	0	0	1924208418	7146653	0	0
tb.dut.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[1].MaskCheckPortB_A	0	0	1572941229	5352124	0	0
tb.dut.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[2].MaskCheckPortA_A	0	0	1924208418	7146653	0	0
tb.dut.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[2].MaskCheckPortB_A	0	0	1572941229	5352124	0	0
tb.dut.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[3].MaskCheckPortA_A	0	0	1924208418	7146653	0	0
tb.dut.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[3].MaskCheckPortB_A	0	0	1572941229	5352124	0	0
tb.dut.u_p2s.IoModeChangeValid_A	0	0	410131121	9814	0	0
tb.dut.u_p2s.IoModeDefault_A	0	0	410131121	66493	0	0
tb.dut.u_passthrough.AddrSetInStIdle_A	0	0	8644	8644	0	0
tb.dut.u_passthrough.PassThroughStKnown_A	0	0	410129881	348509318	0	0
tb.dut.u_passthrough.PayloadSwapConstraint_M	0	0	410129881	1823920	0	0
tb.dut.u_readcmd.AddrIncNotAssertInAddressState_A	0	0	410129881	5910322	0	0
tb.dut.u_readcmd.MailboxSizeMatch_M	0	0	410129881	348509318	0	0
tb.dut.u_readcmd.ValidCmdConfig_A	0	0	410129881	265526	0	0
tb.dut.u_readcmd.u_readbuffer.StartWithAddressUpdate_A	0	0	410129881	10018	0	0
tb.dut.u_readcmd.u_readsram.AddrLatchedPulse_M	0	0	410129881	573677	0	0
tb.dut.u_readcmd.u_readsram.FifoNotEmpty_A	0	0	410129881	5910322	0	0
tb.dut.u_readcmd.u_readsram.NotOverflow_A	0	0	410129881	1490121	0	0
tb.dut.u_readcmd.u_readsram.ReqStrbRelation_M	0	0	410129881	10018	0	0
tb.dut.u_readcmd.u_readsram.SramDataReturnRequirement_M	0	0	410129881	1489459	0	0
tb.dut.u_readcmd.u_readsram.SramReadOnly_A	0	0	410129881	1490121	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.DataKnown_A	0	0	410129881	30130773	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.DepthKnown_A	0	0	410129881	348509318	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.RvalidKnown_A	0	0	410129881	348509318	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.WreadyKnown_A	0	0	410129881	348509318	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	410129881	30130773	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.DataKnown_A	0	0	410129881	28670706	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.DepthKnown_A	0	0	410129881	348509318	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.RvalidKnown_A	0	0	410129881	348509318	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.WreadyKnown_A	0	0	410129881	348509318	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	410129881	28670706	0	0
tb.dut.u_reg.en2addrHit	0	0	1926351399	183687001	0	0
tb.dut.u_reg.reAfterRv	0	0	1926351399	183686996	0	0
tb.dut.u_reg.rePulse	0	0	1926351399	178614327	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	1806	1806	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	1806	1806	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	1806	1806	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	1806	1806	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1806	1806	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1806	1806	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	1806	1806	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1806	1806	0	0
tb.dut.u_reg.u_socket.NotOverflowed_A	0	0	195591012	195591012	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	1926351399	260166450	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1806	1806	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	1926351399	286890705	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1806	1806	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	1926351399	13896968	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1806	1806	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	1926351399	23152145	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1806	1806	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	1926351399	241566773	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1806	1806	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	1926351399	263738560	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	1926351399	1926169920	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1806	1806	0	0
tb.dut.u_reg.u_socket.maxN	0	0	1806	1806	0	0
tb.dut.u_reg.wePulse	0	0	1926351399	5072669	0	0
tb.dut.u_rx_rst_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	1857	226	0	0
tb.dut.u_rxf_overflow.DstPulseCheck_A	0	0	1924208418	6264852	0	0
tb.dut.u_rxf_overflow.SrcPulseCheck_M	0	0	325570152	224	0	0
tb.dut.u_s2p.IoModeDefault_A	0	0	410129881	66517	0	0
tb.dut.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	1631	1631	0	0
tb.dut.u_scanmode_sync.OutputsKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	1924208418	1924072880	0	0
tb.dut.u_spi_tpm.CmdAddrAvailable_A	0	0	410129881	72910	0	0
tb.dut.u_spi_tpm.CmdAddrBitCntInAddrSt_A	0	0	410129881	788544	0	0
tb.dut.u_spi_tpm.CmdAddrInfo_A	0	0	410129881	79667	0	0
tb.dut.u_spi_tpm.CmdPowerof2_A	0	0	1631	1631	0	0
tb.dut.u_spi_tpm.DataFifoLessThan64_A	0	0	1631	1631	0	0
tb.dut.u_spi_tpm.DataSelKnown_A	0	0	410131121	44725035	0	0
tb.dut.u_spi_tpm.HwRegCondition2_a	0	0	410129881	15922	0	0
tb.dut.u_spi_tpm.HwRegCondition_A	0	0	410129881	98568	0	0
tb.dut.u_spi_tpm.HwRegIdxKnown_A	0	0	410131121	44725035	0	0
tb.dut.u_spi_tpm.LocalityLatchCondition_A	0	0	410129881	98568	0	0
tb.dut.u_spi_tpm.RdFifoDepthPoT_A	0	0	1631	1631	0	0
tb.dut.u_spi_tpm.RdFifoNumBytesPoT_A	0	0	1631	1631	0	0
tb.dut.u_spi_tpm.RdPowerof2_A	0	0	1631	1631	0	0
tb.dut.u_spi_tpm.SckFifoAddrLatchCondition_A	0	0	410129881	98568	0	0
tb.dut.u_spi_tpm.TpmRegCondition_A	0	0	410129881	98568	0	0
tb.dut.u_spi_tpm.TpmRegSizeMatch_A	0	0	1631	1631	0	0
tb.dut.u_spi_tpm.WrDepthSpec_A	0	0	1631	1631	0	0
tb.dut.u_spi_tpm.WrFifoAvailable_A	0	0	410129881	635182	0	0
tb.dut.u_spi_tpm.u_cmdaddr_buffer.GrayRptr_A	0	0	1924208418	1924071072	0	0
tb.dut.u_spi_tpm.u_cmdaddr_buffer.GrayWptr_A	0	0	410129881	410128356	0	0
tb.dut.u_spi_tpm.u_cmdaddr_buffer.ParamCheckDepth_A	0	0	1631	1631	0	0
tb.dut.u_spi_tpm.u_hw_reg_slice.ValidWidth_A	0	0	1631	1631	0	0
tb.dut.u_spi_tpm.u_rdfifo.GrayRptr_A	0	0	410131121	44626465	0	0
tb.dut.u_spi_tpm.u_rdfifo.GrayWptr_A	0	0	1924208418	89273840	0	0
tb.dut.u_spi_tpm.u_rdfifo.ParamCheckDepth_A	0	0	1631	1631	0	0
tb.dut.u_spi_tpm.u_wrfifo.GrayRptr_A	0	0	1924208418	1924071072	0	0
tb.dut.u_spi_tpm.u_wrfifo.GrayWptr_A	0	0	410129881	410128356	0	0
tb.dut.u_spi_tpm.u_wrfifo.ParamCheckDepth_A	0	0	1631	1631	0	0
tb.dut.u_spid_status.BusyBitZero_A	0	0	1631	1631	0	0
tb.dut.u_spid_status.u_sw_status_update_sync.GrayRptr_A	0	0	410129881	410128356	0	0
tb.dut.u_spid_status.u_sw_status_update_sync.GrayWptr_A	0	0	1924208418	1924071072	0	0
tb.dut.u_spid_status.u_sw_status_update_sync.ParamCheckDepth_A	0	0	1631	1631	0	0
tb.dut.u_sram_clk_scan.gen_generic.u_impl_generic.selKnown0	0	0	1572941229	1572939743	0	0
tb.dut.u_sram_clk_sel.gen_generic.u_impl_generic.selKnown0	0	0	410129881	410128418	0	0
tb.dut.u_sram_clk_sel.gen_generic.u_impl_generic.selKnown1	0	0	1924208418	1924206787	0	0
tb.dut.u_sram_rst_scanmux.gen_generic.u_impl_generic.selKnown0	0	0	81048	79712	0	0
tb.dut.u_sram_rst_sel.gen_generic.u_impl_generic.selKnown0	0	0	594573	593287	0	0
tb.dut.u_sram_rst_sel.gen_generic.u_impl_generic.selKnown1	0	0	1808	177	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.CheckHotOne_A	0	0	1924208418	1924072880	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A	0	0	1631	1631	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GntImpliesReady_A	0	0	1924208418	11841268	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GntImpliesValid_A	0	0	1924208418	11841268	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GrantKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.IdxKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.IndexIsCorrect_A	0	0	1924208418	11841268	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A	0	0	1924208418	11841268	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A	0	0	1924208418	11841268	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqImpliesValid_A	0	0	1924208418	11841268	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ValidKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A	0	0	1924208418	11841268	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.DataKnown_A	0	0	1924208418	4694615	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.DepthKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.RvalidKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.WreadyKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	1924208418	4694615	0	0
tb.dut.u_tlul2sram.AddrOutKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_tlul2sram.DataIntgOptions_A	0	0	1631	1631	0	0
tb.dut.u_tlul2sram.ReqOutKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_tlul2sram.SramDwHasByteGranularity_A	0	0	1631	1631	0	0
tb.dut.u_tlul2sram.SramDwIsMultipleOfTlulWidth_A	0	0	1631	1631	0	0
tb.dut.u_tlul2sram.TlOutKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_tlul2sram.TlOutPayloadKnown_A	0	0	1924208418	23101752	0	0
tb.dut.u_tlul2sram.TlOutPayloadKnown_AKnownEnable	0	0	1924208418	1924072880	0	0
tb.dut.u_tlul2sram.WdataOutKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_tlul2sram.WeOutKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_tlul2sram.WmaskOutKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_tlul2sram.adapterNoReadOrWrite	0	0	1631	1631	0	0
tb.dut.u_tlul2sram.rvalidHighReqFifoEmpty	0	0	1924208418	4690198	0	0
tb.dut.u_tlul2sram.rvalidHighWhenRspFifoFull	0	0	1924208418	4690198	0	0
tb.dut.u_tlul2sram.u_err.dataWidthOnly32_A	0	0	1631	1631	0	0
tb.dut.u_tlul2sram.u_reqfifo.DataKnown_A	0	0	1924208418	23101752	0	0
tb.dut.u_tlul2sram.u_reqfifo.DepthKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_tlul2sram.u_reqfifo.RvalidKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_tlul2sram.u_reqfifo.WreadyKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_tlul2sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	1924208418	23101752	0	0
tb.dut.u_tlul2sram.u_rsp_gen.DataWidthCheck_A	0	0	1631	1631	0	0
tb.dut.u_tlul2sram.u_rsp_gen.PayLoadWidthCheck	0	0	1631	1631	0	0
tb.dut.u_tlul2sram.u_rspfifo.DataKnown_A	0	0	1924208418	9455945	0	0
tb.dut.u_tlul2sram.u_rspfifo.DepthKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_tlul2sram.u_rspfifo.RvalidKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_tlul2sram.u_rspfifo.WreadyKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_tlul2sram.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	1924208418	9455945	0	0
tb.dut.u_tlul2sram.u_sramreqfifo.DataKnown_A	0	0	1924208418	4690198	0	0
tb.dut.u_tlul2sram.u_sramreqfifo.DepthKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_tlul2sram.u_sramreqfifo.RvalidKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_tlul2sram.u_sramreqfifo.WreadyKnown_A	0	0	1924208418	1924072880	0	0
tb.dut.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	1924208418	4690198	0	0
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	128790	128320	0	0
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	126648	126178	0	0
tb.dut.u_tx_rst_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	1858	227	0	0
tb.dut.u_upload.AddrFifoNeverFull_M	0	0	410129881	1889	0	0
tb.dut.u_upload.CmdFifoNeverFull_M	0	0	410129881	2528	0	0
tb.dut.u_upload.CmdFifoPush_A	0	0	410129881	2528	0	0
tb.dut.u_upload.FifosOnlyOneValid_A	0	0	410129881	348509318	0	0
tb.dut.u_upload.PayloadNeverFull_M	0	0	410129881	701786	0	0
tb.dut.u_upload.u_addrfifo.MinDepth_A	0	0	1631	1631	0	0
tb.dut.u_upload.u_addrfifo.NoRAckInEmpty_A	0	0	1924208418	1889	0	0
tb.dut.u_upload.u_addrfifo.NoWAckInFull_A	0	0	410129881	1889	0	0
tb.dut.u_upload.u_addrfifo.ParamCheckDepth_A	0	0	1631	1631	0	0
tb.dut.u_upload.u_addrfifo.RSramRvalidOneCycle_M	0	0	1924208418	1889	0	0
tb.dut.u_upload.u_addrfifo.RptrGrayOneBitAtATime_A	0	0	1924208418	1889	0	0
tb.dut.u_upload.u_addrfifo.RptrIncDataValid_A	0	0	1924208418	1889	0	0
tb.dut.u_upload.u_addrfifo.RptrIncrease_A	0	0	1924208418	1889	0	0
tb.dut.u_upload.u_addrfifo.SramRvalid_A	0	0	1924208418	1889	0	0
tb.dut.u_upload.u_addrfifo.WSramRvalid_A	0	0	410129881	410129872	0	0
tb.dut.u_upload.u_addrfifo.WidthMatch_A	0	0	1631	1631	0	0
tb.dut.u_upload.u_addrfifo.WptrGrayOneBitAtATime_A	0	0	410129881	1889	0	0
tb.dut.u_upload.u_addrfifo.WptrIncrease_A	0	0	410129881	1889	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.CheckHotOne_A	0	0	410129881	348509318	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A	0	0	1631	1631	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesReady_A	0	0	410129881	706203	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesValid_A	0	0	410129881	706203	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GrantKnown_A	0	0	410129881	348509318	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.IdxKnown_A	0	0	410129881	348509318	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.IndexIsCorrect_A	0	0	410129881	706203	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A	0	0	410129881	706203	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A	0	0	410129881	706203	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqImpliesValid_A	0	0	410129881	706203	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ValidKnown_A	0	0	410129881	348509318	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A	0	0	410129881	706203	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.DepthKnown_A	0	0	410129881	348509318	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.RvalidKnown_A	0	0	410129881	348509318	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.WreadyKnown_A	0	0	410129881	348509318	0	0
tb.dut.u_upload.u_cmdfifo.MinDepth_A	0	0	1631	1631	0	0
tb.dut.u_upload.u_cmdfifo.NoRAckInEmpty_A	0	0	1924208418	2528	0	0
tb.dut.u_upload.u_cmdfifo.NoWAckInFull_A	0	0	410129881	2528	0	0
tb.dut.u_upload.u_cmdfifo.ParamCheckDepth_A	0	0	1631	1631	0	0
tb.dut.u_upload.u_cmdfifo.RSramRvalidOneCycle_M	0	0	1924208418	2528	0	0
tb.dut.u_upload.u_cmdfifo.RptrGrayOneBitAtATime_A	0	0	1924208418	2528	0	0
tb.dut.u_upload.u_cmdfifo.RptrIncDataValid_A	0	0	1924208418	2528	0	0
tb.dut.u_upload.u_cmdfifo.RptrIncrease_A	0	0	1924208418	2528	0	0
tb.dut.u_upload.u_cmdfifo.SramRvalid_A	0	0	1924208418	2528	0	0
tb.dut.u_upload.u_cmdfifo.WSramRvalid_A	0	0	410129881	410129872	0	0
tb.dut.u_upload.u_cmdfifo.WidthMatch_A	0	0	1631	1631	0	0
tb.dut.u_upload.u_cmdfifo.WptrGrayOneBitAtATime_A	0	0	410129881	2528	0	0
tb.dut.u_upload.u_cmdfifo.WptrIncrease_A	0	0	410129881	2528	0	0
tb.dut.u_upload.u_payload_buffer.g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A	0	0	1631	1631	0	0
tb.dut.u_upload.u_payload_buffer.g_multiple_entry_per_word.WidthDivideSramDw_A	0	0	1631	1631	0	0
tb.dut.u_upload.u_payloadptr_clr_psync.DstPulseCheck_A	0	0	1924208418	2528	0	0
tb.dut.u_upload.u_payloadptr_clr_psync.SrcPulseCheck_M	0	0	410129881	2528	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	1572941229	1513	0	716
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	1924208418	0	0	1631

Assertions Without Attempts:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_rx_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_sram_clk_scan.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_sram_rst_scanmux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_tx_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	1926352527	3415932	3415932	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	1926352527	1233	1233	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	1926352527	1237	1237	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	1926352527	864	864	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	1926352527	230	230	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	1926352527	655	655	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	1926352527	644	644	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	1926352527	18107	18107	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	1926352527	50296993	50296993	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	1926352527	73919085	73919085	1786

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	1926352527	3415932	3415932	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	1926352527	1233	1233	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	1926352527	1237	1237	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	1926352527	864	864	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	1926352527	230	230	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	1926352527	655	655	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	1926352527	644	644	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	1926352527	18107	18107	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	1926352527	50296993	50296993	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	1926352527	73919085	73919085	1786