| Name |
| /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3851906142 |
| /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1999280941 |
| /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2848506149 |
| /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.86911780 |
| /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1711735815 |
| /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3762148386 |
| /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.943082739 |
| /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4097262202 |
| /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.649942792 |
| /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1035243798 |
| /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1181964239 |
| /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3520510789 |
| /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2080669526 |
| /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2982195956 |
| /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3692536269 |
| /workspace/coverage/cover_reg_top/1.spi_device_intr_test.718348170 |
| /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2717974399 |
| /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3865747258 |
| /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2063893038 |
| /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3332238724 |
| /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3177159575 |
| /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2633259320 |
| /workspace/coverage/cover_reg_top/10.spi_device_intr_test.887838320 |
| /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3703479787 |
| /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3916057476 |
| /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3632053940 |
| /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1924239601 |
| /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1831380783 |
| /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3755965904 |
| /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2498615752 |
| /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.551080679 |
| /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3733564530 |
| /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3029110493 |
| /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.769870528 |
| /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1989428732 |
| /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2345240614 |
| /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.892889467 |
| /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3235920880 |
| /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1786689563 |
| /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1814198859 |
| /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1457399552 |
| /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1926841508 |
| /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2262643905 |
| /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2692848602 |
| /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3554686069 |
| /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2029890764 |
| /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.259764749 |
| /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3071312111 |
| /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.690122089 |
| /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2023180976 |
| /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.501756072 |
| /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1975595395 |
| /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2078035294 |
| /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1684198262 |
| /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3952019234 |
| /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3008860458 |
| /workspace/coverage/cover_reg_top/16.spi_device_intr_test.373679838 |
| /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1136166008 |
| /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2429814777 |
| /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1820658967 |
| /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4029942543 |
| /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3148432124 |
| /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3488199082 |
| /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.382685963 |
| /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3998634687 |
| /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1940597823 |
| /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2672123896 |
| /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2462488110 |
| /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.57319873 |
| /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2562226486 |
| /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2824380139 |
| /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1134129135 |
| /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1236014249 |
| /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1601546455 |
| /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.940886078 |
| /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.358557979 |
| /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2656653218 |
| /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2924980110 |
| /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3105301725 |
| /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4087355657 |
| /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3753930871 |
| /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2294467584 |
| /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3126851216 |
| /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.764298466 |
| /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.950205657 |
| /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1266657094 |
| /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2639420878 |
| /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3560834220 |
| /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1589394131 |
| /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1222584853 |
| /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1521325337 |
| /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2504675940 |
| /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3412144340 |
| /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3896551537 |
| /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2554098884 |
| /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2919231621 |
| /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2104345363 |
| /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2786592341 |
| /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2613201638 |
| /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1657344720 |
| /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.303734626 |
| /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3486939398 |
| /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2531787140 |
| /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.816758683 |
| /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.692272075 |
| /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3412780716 |
| /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1562488662 |
| /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2867991879 |
| /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3979589412 |
| /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3907265662 |
| /workspace/coverage/cover_reg_top/34.spi_device_intr_test.964666101 |
| /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3903426098 |
| /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1346903784 |
| /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4169998102 |
| /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1090392212 |
| /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2546982413 |
| /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3201014417 |
| /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.245523833 |
| /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4065736415 |
| /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1929308104 |
| /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3646687127 |
| /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3334079209 |
| /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1208227692 |
| /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1460334732 |
| /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1048195847 |
| /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2224144134 |
| /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1527033180 |
| /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3143089318 |
| /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2987626731 |
| /workspace/coverage/cover_reg_top/43.spi_device_intr_test.258334941 |
| /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3052405635 |
| /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1975056700 |
| /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3534204632 |
| /workspace/coverage/cover_reg_top/47.spi_device_intr_test.564626966 |
| /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3964998380 |
| /workspace/coverage/cover_reg_top/49.spi_device_intr_test.184547187 |
| /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4207986122 |
| /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.30967564 |
| /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1302804181 |
| /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1657343019 |
| /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.576911181 |
| /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3990756565 |
| /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1951085206 |
| /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1751597968 |
| /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2567223587 |
| /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3955844390 |
| /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3268263580 |
| /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1266352893 |
| /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1761831469 |
| /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1829762690 |
| /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2492569831 |
| /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2471334089 |
| /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2357694379 |
| /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1531975307 |
| /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1295302465 |
| /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.502436404 |
| /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2340163871 |
| /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2573149248 |
| /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3625277410 |
| /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3438387480 |
| /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1552856373 |
| /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3248145374 |
| /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3336348705 |
| /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1218453901 |
| /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3281801725 |
| /workspace/coverage/default/0.spi_device_alert_test.654286210 |
| /workspace/coverage/default/0.spi_device_bit_transfer.1533884039 |
| /workspace/coverage/default/0.spi_device_byte_transfer.1099741839 |
| /workspace/coverage/default/0.spi_device_cfg_cmd.2305699991 |
| /workspace/coverage/default/0.spi_device_csb_read.1443334989 |
| /workspace/coverage/default/0.spi_device_dummy_item_extra_dly.1210397608 |
| /workspace/coverage/default/0.spi_device_fifo_full.2607074315 |
| /workspace/coverage/default/0.spi_device_fifo_underflow_overflow.1647055011 |
| /workspace/coverage/default/0.spi_device_flash_all.1752100357 |
| /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1895619546 |
| /workspace/coverage/default/0.spi_device_flash_mode.1382857144 |
| /workspace/coverage/default/0.spi_device_intercept.2339826327 |
| /workspace/coverage/default/0.spi_device_intr.2190729369 |
| /workspace/coverage/default/0.spi_device_mailbox.194726730 |
| /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1598932678 |
| /workspace/coverage/default/0.spi_device_pass_cmd_filtering.216233788 |
| /workspace/coverage/default/0.spi_device_perf.1837316504 |
| /workspace/coverage/default/0.spi_device_read_buffer_direct.3136936959 |
| /workspace/coverage/default/0.spi_device_rx_async_fifo_reset.3454600871 |
| /workspace/coverage/default/0.spi_device_rx_timeout.2829331785 |
| /workspace/coverage/default/0.spi_device_smoke.327225531 |
| /workspace/coverage/default/0.spi_device_stress_all.3466429714 |
| /workspace/coverage/default/0.spi_device_tpm_all.1151381482 |
| /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1506993831 |
| /workspace/coverage/default/0.spi_device_tpm_rw.3151238487 |
| /workspace/coverage/default/0.spi_device_tpm_sts_read.2658902816 |
| /workspace/coverage/default/0.spi_device_tx_async_fifo_reset.1542496416 |
| /workspace/coverage/default/0.spi_device_txrx.1154462724 |
| /workspace/coverage/default/0.spi_device_upload.3131633426 |
| /workspace/coverage/default/1.spi_device_abort.2912927918 |
| /workspace/coverage/default/1.spi_device_bit_transfer.3817069399 |
| /workspace/coverage/default/1.spi_device_byte_transfer.3194644141 |
| /workspace/coverage/default/1.spi_device_cfg_cmd.269097059 |
| /workspace/coverage/default/1.spi_device_csb_read.2273736150 |
| /workspace/coverage/default/1.spi_device_dummy_item_extra_dly.361425517 |
| /workspace/coverage/default/1.spi_device_extreme_fifo_size.2462162824 |
| /workspace/coverage/default/1.spi_device_fifo_full.229456984 |
| /workspace/coverage/default/1.spi_device_fifo_underflow_overflow.1366609124 |
| /workspace/coverage/default/1.spi_device_flash_all.1152229540 |
| /workspace/coverage/default/1.spi_device_flash_and_tpm.1392734931 |
| /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.849014587 |
| /workspace/coverage/default/1.spi_device_flash_mode.1776925379 |
| /workspace/coverage/default/1.spi_device_intercept.2954864125 |
| /workspace/coverage/default/1.spi_device_intr.931449286 |
| /workspace/coverage/default/1.spi_device_mailbox.2590008854 |
| /workspace/coverage/default/1.spi_device_mem_parity.63240149 |
| /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2366940666 |
| /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1971606291 |
| /workspace/coverage/default/1.spi_device_perf.44081562 |
| /workspace/coverage/default/1.spi_device_ram_cfg.4006770535 |
| /workspace/coverage/default/1.spi_device_read_buffer_direct.780212714 |
| /workspace/coverage/default/1.spi_device_rx_async_fifo_reset.1117438331 |
| /workspace/coverage/default/1.spi_device_rx_timeout.1854723894 |
| /workspace/coverage/default/1.spi_device_sec_cm.1381138090 |
| /workspace/coverage/default/1.spi_device_smoke.3993443607 |
| /workspace/coverage/default/1.spi_device_stress_all.2028339567 |
| /workspace/coverage/default/1.spi_device_tpm_all.1730276838 |
| /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1478829677 |
| /workspace/coverage/default/1.spi_device_tpm_rw.790194042 |
| /workspace/coverage/default/1.spi_device_tpm_sts_read.750817201 |
| /workspace/coverage/default/1.spi_device_tx_async_fifo_reset.3432431334 |
| /workspace/coverage/default/1.spi_device_upload.3498559664 |
| /workspace/coverage/default/10.spi_device_abort.3984696 |
| /workspace/coverage/default/10.spi_device_alert_test.3940967464 |
| /workspace/coverage/default/10.spi_device_bit_transfer.961469323 |
| /workspace/coverage/default/10.spi_device_byte_transfer.1461789302 |
| /workspace/coverage/default/10.spi_device_cfg_cmd.2401315485 |
| /workspace/coverage/default/10.spi_device_csb_read.283092086 |
| /workspace/coverage/default/10.spi_device_dummy_item_extra_dly.112787026 |
| /workspace/coverage/default/10.spi_device_extreme_fifo_size.2900699286 |
| /workspace/coverage/default/10.spi_device_fifo_full.2493786997 |
| /workspace/coverage/default/10.spi_device_fifo_underflow_overflow.422409422 |
| /workspace/coverage/default/10.spi_device_flash_all.2555230177 |
| /workspace/coverage/default/10.spi_device_flash_and_tpm.458040284 |
| /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3821264463 |
| /workspace/coverage/default/10.spi_device_intercept.798015807 |
| /workspace/coverage/default/10.spi_device_intr.2379243721 |
| /workspace/coverage/default/10.spi_device_mailbox.3502793432 |
| /workspace/coverage/default/10.spi_device_mem_parity.2898796467 |
| /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.744018722 |
| /workspace/coverage/default/10.spi_device_pass_cmd_filtering.215396922 |
| /workspace/coverage/default/10.spi_device_perf.1758547070 |
| /workspace/coverage/default/10.spi_device_ram_cfg.367027763 |
| /workspace/coverage/default/10.spi_device_rx_timeout.4020523030 |
| /workspace/coverage/default/10.spi_device_smoke.4254058385 |
| /workspace/coverage/default/10.spi_device_stress_all.4202239373 |
| /workspace/coverage/default/10.spi_device_tpm_all.460551335 |
| /workspace/coverage/default/10.spi_device_tpm_rw.4127998540 |
| /workspace/coverage/default/10.spi_device_tpm_sts_read.2032664905 |
| /workspace/coverage/default/10.spi_device_tx_async_fifo_reset.1502475894 |
| /workspace/coverage/default/10.spi_device_txrx.446863155 |
| /workspace/coverage/default/10.spi_device_upload.224478226 |
| /workspace/coverage/default/11.spi_device_abort.2157119276 |
| /workspace/coverage/default/11.spi_device_alert_test.251765329 |
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| /workspace/coverage/default/7.spi_device_upload.3809158759 |
| /workspace/coverage/default/8.spi_device_abort.2075285388 |
| /workspace/coverage/default/8.spi_device_alert_test.1506227498 |
| /workspace/coverage/default/8.spi_device_bit_transfer.4122777884 |
| /workspace/coverage/default/8.spi_device_byte_transfer.653010230 |
| /workspace/coverage/default/8.spi_device_cfg_cmd.2719785455 |
| /workspace/coverage/default/8.spi_device_csb_read.1803851889 |
| /workspace/coverage/default/8.spi_device_dummy_item_extra_dly.4247256243 |
| /workspace/coverage/default/8.spi_device_fifo_full.2211458818 |
| /workspace/coverage/default/8.spi_device_fifo_underflow_overflow.3625779239 |
| /workspace/coverage/default/8.spi_device_flash_all.2204726657 |
| /workspace/coverage/default/8.spi_device_flash_and_tpm.329216071 |
| /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.35052329 |
| /workspace/coverage/default/8.spi_device_flash_mode.3320307857 |
| /workspace/coverage/default/8.spi_device_intercept.3659918083 |
| /workspace/coverage/default/8.spi_device_intr.1577723343 |
| /workspace/coverage/default/8.spi_device_mailbox.2769336133 |
| /workspace/coverage/default/8.spi_device_mem_parity.3016121381 |
| /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2554002974 |
| /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2255858373 |
| /workspace/coverage/default/8.spi_device_perf.2113791443 |
| /workspace/coverage/default/8.spi_device_ram_cfg.3689088337 |
| /workspace/coverage/default/8.spi_device_read_buffer_direct.3711561564 |
| /workspace/coverage/default/8.spi_device_rx_async_fifo_reset.4040171614 |
| /workspace/coverage/default/8.spi_device_rx_timeout.375884798 |
| /workspace/coverage/default/8.spi_device_smoke.356742824 |
| /workspace/coverage/default/8.spi_device_tpm_all.1619496878 |
| /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.158258035 |
| /workspace/coverage/default/8.spi_device_tpm_rw.832845416 |
| /workspace/coverage/default/8.spi_device_tpm_sts_read.655265605 |
| /workspace/coverage/default/8.spi_device_tx_async_fifo_reset.3659035431 |
| /workspace/coverage/default/8.spi_device_txrx.1880691471 |
| /workspace/coverage/default/8.spi_device_upload.534594882 |
| /workspace/coverage/default/9.spi_device_abort.445674127 |
| /workspace/coverage/default/9.spi_device_alert_test.3016213088 |
| /workspace/coverage/default/9.spi_device_bit_transfer.3116744671 |
| /workspace/coverage/default/9.spi_device_byte_transfer.2982849180 |
| /workspace/coverage/default/9.spi_device_cfg_cmd.1735087474 |
| /workspace/coverage/default/9.spi_device_csb_read.2288552039 |
| /workspace/coverage/default/9.spi_device_dummy_item_extra_dly.1464790953 |
| /workspace/coverage/default/9.spi_device_extreme_fifo_size.3228361995 |
| /workspace/coverage/default/9.spi_device_fifo_full.93516838 |
| /workspace/coverage/default/9.spi_device_fifo_underflow_overflow.2052426197 |
| /workspace/coverage/default/9.spi_device_flash_all.2289787566 |
| /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.272200953 |
| /workspace/coverage/default/9.spi_device_flash_mode.2098869727 |
| /workspace/coverage/default/9.spi_device_intercept.3441492842 |
| /workspace/coverage/default/9.spi_device_intr.3379706780 |
| /workspace/coverage/default/9.spi_device_mailbox.3874025375 |
| /workspace/coverage/default/9.spi_device_mem_parity.975426530 |
| /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.866756381 |
| /workspace/coverage/default/9.spi_device_pass_cmd_filtering.967784983 |
| /workspace/coverage/default/9.spi_device_perf.20820258 |
| /workspace/coverage/default/9.spi_device_ram_cfg.1713319188 |
| /workspace/coverage/default/9.spi_device_read_buffer_direct.1883783219 |
| /workspace/coverage/default/9.spi_device_rx_async_fifo_reset.2498771679 |
| /workspace/coverage/default/9.spi_device_rx_timeout.3854259839 |
| /workspace/coverage/default/9.spi_device_smoke.3751610903 |
| /workspace/coverage/default/9.spi_device_tpm_all.811700079 |
| /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.962038573 |
| /workspace/coverage/default/9.spi_device_tpm_rw.3032224623 |
| /workspace/coverage/default/9.spi_device_tpm_sts_read.3683609744 |
| /workspace/coverage/default/9.spi_device_tx_async_fifo_reset.661842506 |
| /workspace/coverage/default/9.spi_device_txrx.28148479 |
| /workspace/coverage/default/9.spi_device_upload.3662519949 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/47.spi_device_intr.4201796929 |
|
|
May 28 03:51:57 AM PDT 23 |
May 28 03:52:04 AM PDT 23 |
7150466899 ps |
| T4 |
/workspace/coverage/default/32.spi_device_alert_test.3603806586 |
|
|
May 28 03:46:55 AM PDT 23 |
May 28 03:46:58 AM PDT 23 |
13014056 ps |
| T2 |
/workspace/coverage/default/18.spi_device_byte_transfer.1683551043 |
|
|
May 28 03:41:03 AM PDT 23 |
May 28 03:41:06 AM PDT 23 |
69077403 ps |
| T5 |
/workspace/coverage/default/22.spi_device_pass_addr_payload_swap.4083809103 |
|
|
May 28 03:43:03 AM PDT 23 |
May 28 03:43:14 AM PDT 23 |
827245916 ps |
| T16 |
/workspace/coverage/default/24.spi_device_tpm_sts_read.3769519777 |
|
|
May 28 03:43:32 AM PDT 23 |
May 28 03:43:33 AM PDT 23 |
79723497 ps |
| T3 |
/workspace/coverage/default/37.spi_device_dummy_item_extra_dly.1791268030 |
|
|
May 28 03:48:31 AM PDT 23 |
May 28 04:07:47 AM PDT 23 |
139338534261 ps |
| T12 |
/workspace/coverage/default/47.spi_device_dummy_item_extra_dly.1171191726 |
|
|
May 28 03:52:09 AM PDT 23 |
May 28 03:56:27 AM PDT 23 |
69262674997 ps |
| T9 |
/workspace/coverage/default/29.spi_device_pass_addr_payload_swap.245137471 |
|
|
May 28 03:45:30 AM PDT 23 |
May 28 03:45:34 AM PDT 23 |
349591031 ps |
| T6 |
/workspace/coverage/default/9.spi_device_flash_and_tpm.547187504 |
|
|
May 28 03:38:45 AM PDT 23 |
May 28 03:42:14 AM PDT 23 |
102653618577 ps |
| T17 |
/workspace/coverage/default/41.spi_device_tpm_all.356537280 |
|
|
May 28 03:50:11 AM PDT 23 |
May 28 03:51:03 AM PDT 23 |
31725244374 ps |
| T10 |
/workspace/coverage/default/43.spi_device_intercept.4159394471 |
|
|
May 28 03:51:47 AM PDT 23 |
May 28 03:51:54 AM PDT 23 |
11957971407 ps |
| T13 |
/workspace/coverage/default/3.spi_device_byte_transfer.2538213590 |
|
|
May 28 03:35:42 AM PDT 23 |
May 28 03:35:45 AM PDT 23 |
247524749 ps |
| T38 |
/workspace/coverage/default/9.spi_device_mem_parity.975426530 |
|
|
May 28 03:38:15 AM PDT 23 |
May 28 03:38:18 AM PDT 23 |
81092086 ps |
| T7 |
/workspace/coverage/default/39.spi_device_flash_all.745089536 |
|
|
May 28 03:49:45 AM PDT 23 |
May 28 03:51:37 AM PDT 23 |
17875837916 ps |
| T37 |
/workspace/coverage/default/9.spi_device_smoke.3751610903 |
|
|
May 28 03:38:14 AM PDT 23 |
May 28 03:38:16 AM PDT 23 |
89285565 ps |
| T11 |
/workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2614416990 |
|
|
May 28 03:47:18 AM PDT 23 |
May 28 03:47:30 AM PDT 23 |
761413916 ps |
| T14 |
/workspace/coverage/default/31.spi_device_pass_cmd_filtering.2327632991 |
|
|
May 28 03:46:46 AM PDT 23 |
May 28 03:46:53 AM PDT 23 |
4978586646 ps |
| T15 |
/workspace/coverage/default/41.spi_device_flash_mode.1935440221 |
|
|
May 28 03:50:07 AM PDT 23 |
May 28 03:50:20 AM PDT 23 |
4074889995 ps |
| T43 |
/workspace/coverage/default/15.spi_device_tx_async_fifo_reset.3542249140 |
|
|
May 28 03:40:31 AM PDT 23 |
May 28 03:40:32 AM PDT 23 |
93365991 ps |
| T44 |
/workspace/coverage/default/38.spi_device_rx_async_fifo_reset.2739273665 |
|
|
May 28 03:48:25 AM PDT 23 |
May 28 03:48:26 AM PDT 23 |
18393750 ps |
| T33 |
/workspace/coverage/default/30.spi_device_flash_mode.1977249353 |
|
|
May 28 03:45:30 AM PDT 23 |
May 28 03:45:54 AM PDT 23 |
19679128490 ps |
| T41 |
/workspace/coverage/default/2.spi_device_smoke.1270538483 |
|
|
May 28 03:35:18 AM PDT 23 |
May 28 03:35:19 AM PDT 23 |
59919768 ps |
| T111 |
/workspace/coverage/default/34.spi_device_tpm_all.1567021114 |
|
|
May 28 03:47:20 AM PDT 23 |
May 28 03:50:11 AM PDT 23 |
46827007465 ps |
| T97 |
/workspace/coverage/default/44.spi_device_mailbox.3745319102 |
|
|
May 28 03:51:34 AM PDT 23 |
May 28 03:51:49 AM PDT 23 |
1893778159 ps |
| T112 |
/workspace/coverage/default/43.spi_device_tpm_rw.3643528620 |
|
|
May 28 03:51:39 AM PDT 23 |
May 28 03:51:43 AM PDT 23 |
133775235 ps |
| T42 |
/workspace/coverage/default/22.spi_device_byte_transfer.3186915906 |
|
|
May 28 03:42:15 AM PDT 23 |
May 28 03:42:18 AM PDT 23 |
111027829 ps |
| T20 |
/workspace/coverage/default/34.spi_device_cfg_cmd.2860943119 |
|
|
May 28 03:47:20 AM PDT 23 |
May 28 03:47:30 AM PDT 23 |
2332306423 ps |
| T74 |
/workspace/coverage/default/39.spi_device_dummy_item_extra_dly.3953325366 |
|
|
May 28 03:49:48 AM PDT 23 |
May 28 03:58:24 AM PDT 23 |
54263781169 ps |
| T130 |
/workspace/coverage/default/12.spi_device_perf.4225016337 |
|
|
May 28 03:39:43 AM PDT 23 |
May 28 03:42:53 AM PDT 23 |
12154136928 ps |
| T242 |
/workspace/coverage/default/4.spi_device_smoke.3285709282 |
|
|
May 28 03:35:47 AM PDT 23 |
May 28 03:35:49 AM PDT 23 |
166264923 ps |
| T129 |
/workspace/coverage/default/22.spi_device_dummy_item_extra_dly.885700068 |
|
|
May 28 03:42:24 AM PDT 23 |
May 28 03:48:22 AM PDT 23 |
41263380673 ps |
| T85 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3692536269 |
|
|
May 28 05:20:45 AM PDT 23 |
May 28 05:20:47 AM PDT 23 |
72990187 ps |
| T89 |
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.1975595395 |
|
|
May 28 05:21:12 AM PDT 23 |
May 28 05:21:13 AM PDT 23 |
15523063 ps |
| T81 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2547885475 |
|
|
May 28 05:20:40 AM PDT 23 |
May 28 05:20:43 AM PDT 23 |
156885204 ps |
| T90 |
/workspace/coverage/cover_reg_top/41.spi_device_intr_test.3143089318 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
13528938 ps |
| T84 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4050817975 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:17 AM PDT 23 |
408747886 ps |
| T91 |
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.1246496945 |
|
|
May 28 05:20:35 AM PDT 23 |
May 28 05:20:36 AM PDT 23 |
60671233 ps |
| T82 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3438387480 |
|
|
May 28 05:21:07 AM PDT 23 |
May 28 05:21:09 AM PDT 23 |
39465828 ps |
| T93 |
/workspace/coverage/cover_reg_top/6.spi_device_intr_test.2567223587 |
|
|
May 28 05:21:07 AM PDT 23 |
May 28 05:21:08 AM PDT 23 |
11580953 ps |
| T135 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3071312111 |
|
|
May 28 05:21:11 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
264817693 ps |
| T92 |
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.373679838 |
|
|
May 28 05:21:12 AM PDT 23 |
May 28 05:21:14 AM PDT 23 |
26103191 ps |
| T83 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4029942543 |
|
|
May 28 05:21:12 AM PDT 23 |
May 28 05:21:15 AM PDT 23 |
91275804 ps |
| T86 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3625277410 |
|
|
May 28 05:21:07 AM PDT 23 |
May 28 05:21:15 AM PDT 23 |
357914152 ps |
| T161 |
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.3896551537 |
|
|
May 28 05:21:15 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
13998412 ps |
| T87 |
/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2340163871 |
|
|
May 28 05:21:05 AM PDT 23 |
May 28 05:21:07 AM PDT 23 |
131169537 ps |
| T136 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2429814777 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:20 AM PDT 23 |
810634760 ps |
| T162 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2023180976 |
|
|
May 28 05:21:11 AM PDT 23 |
May 28 05:21:14 AM PDT 23 |
21832195 ps |
| T88 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1346593879 |
|
|
May 28 05:20:30 AM PDT 23 |
May 28 05:20:52 AM PDT 23 |
3975119143 ps |
| T163 |
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.1222584853 |
|
|
May 28 05:21:22 AM PDT 23 |
May 28 05:21:23 AM PDT 23 |
64516848 ps |
| T140 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1218453901 |
|
|
May 28 05:21:10 AM PDT 23 |
May 28 05:21:14 AM PDT 23 |
88169637 ps |
| T166 |
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.3646687127 |
|
|
May 28 05:20:28 AM PDT 23 |
May 28 05:20:29 AM PDT 23 |
16124180 ps |
| T167 |
/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2471334089 |
|
|
May 28 05:21:15 AM PDT 23 |
May 28 05:21:20 AM PDT 23 |
187332836 ps |
| T168 |
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1136166008 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:18 AM PDT 23 |
90769737 ps |
| T141 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3998634687 |
|
|
May 28 05:21:13 AM PDT 23 |
May 28 05:21:19 AM PDT 23 |
206493292 ps |
| T142 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3749258804 |
|
|
May 28 05:21:12 AM PDT 23 |
May 28 05:21:18 AM PDT 23 |
348427270 ps |
| T188 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1552856373 |
|
|
May 28 05:21:04 AM PDT 23 |
May 28 05:21:05 AM PDT 23 |
149344206 ps |
| T143 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1684198262 |
|
|
May 28 05:21:13 AM PDT 23 |
May 28 05:21:17 AM PDT 23 |
3151166530 ps |
| T354 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1181964239 |
|
|
May 28 05:20:41 AM PDT 23 |
May 28 05:20:50 AM PDT 23 |
318585053 ps |
| T225 |
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.1521325337 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
35184458 ps |
| T228 |
/workspace/coverage/cover_reg_top/36.spi_device_intr_test.2613966570 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
33526153 ps |
| T355 |
/workspace/coverage/cover_reg_top/37.spi_device_intr_test.1346903784 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
14436757 ps |
| T189 |
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2345240614 |
|
|
May 28 05:21:19 AM PDT 23 |
May 28 05:21:24 AM PDT 23 |
68450025 ps |
| T356 |
/workspace/coverage/cover_reg_top/9.spi_device_intr_test.3248145374 |
|
|
May 28 05:21:05 AM PDT 23 |
May 28 05:21:06 AM PDT 23 |
22141821 ps |
| T357 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1951085206 |
|
|
May 28 05:21:07 AM PDT 23 |
May 28 05:21:10 AM PDT 23 |
91109250 ps |
| T226 |
/workspace/coverage/cover_reg_top/8.spi_device_intr_test.4052255611 |
|
|
May 28 05:21:06 AM PDT 23 |
May 28 05:21:07 AM PDT 23 |
14504756 ps |
| T358 |
/workspace/coverage/cover_reg_top/46.spi_device_intr_test.3534204632 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
11774433 ps |
| T170 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2080669526 |
|
|
May 28 05:20:36 AM PDT 23 |
May 28 05:20:38 AM PDT 23 |
40243153 ps |
| T171 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2546982413 |
|
|
May 28 05:20:31 AM PDT 23 |
May 28 05:20:40 AM PDT 23 |
390310750 ps |
| T172 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2857151032 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:18 AM PDT 23 |
435605309 ps |
| T173 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.816758683 |
|
|
May 28 05:20:32 AM PDT 23 |
May 28 05:20:37 AM PDT 23 |
252478892 ps |
| T139 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1820658967 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:23 AM PDT 23 |
3327214478 ps |
| T164 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2562226486 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:19 AM PDT 23 |
240773400 ps |
| T165 |
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.764251033 |
|
|
May 28 05:20:36 AM PDT 23 |
May 28 05:20:48 AM PDT 23 |
202126581 ps |
| T174 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3554686069 |
|
|
May 28 05:21:11 AM PDT 23 |
May 28 05:21:12 AM PDT 23 |
124735973 ps |
| T175 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3008860458 |
|
|
May 28 05:21:13 AM PDT 23 |
May 28 05:21:18 AM PDT 23 |
27764118 ps |
| T169 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1048195847 |
|
|
May 28 05:20:37 AM PDT 23 |
May 28 05:20:42 AM PDT 23 |
190905231 ps |
| T182 |
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.2462488110 |
|
|
May 28 05:21:13 AM PDT 23 |
May 28 05:21:15 AM PDT 23 |
12595805 ps |
| T183 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2692848602 |
|
|
May 28 05:21:12 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
67721292 ps |
| T359 |
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3955844390 |
|
|
May 28 05:21:09 AM PDT 23 |
May 28 05:21:12 AM PDT 23 |
58162855 ps |
| T360 |
/workspace/coverage/cover_reg_top/31.spi_device_intr_test.2867991879 |
|
|
May 28 05:21:22 AM PDT 23 |
May 28 05:21:23 AM PDT 23 |
28890806 ps |
| T227 |
/workspace/coverage/cover_reg_top/5.spi_device_intr_test.1302804181 |
|
|
May 28 05:20:33 AM PDT 23 |
May 28 05:20:34 AM PDT 23 |
40627412 ps |
| T176 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3753930871 |
|
|
May 28 05:20:34 AM PDT 23 |
May 28 05:20:36 AM PDT 23 |
131017180 ps |
| T177 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2294467584 |
|
|
May 28 05:20:34 AM PDT 23 |
May 28 05:20:39 AM PDT 23 |
198729337 ps |
| T361 |
/workspace/coverage/cover_reg_top/48.spi_device_intr_test.3964998380 |
|
|
May 28 05:21:16 AM PDT 23 |
May 28 05:21:17 AM PDT 23 |
11391415 ps |
| T362 |
/workspace/coverage/cover_reg_top/45.spi_device_intr_test.1975056700 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
40235561 ps |
| T363 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3916057476 |
|
|
May 28 05:21:12 AM PDT 23 |
May 28 05:21:15 AM PDT 23 |
35815512 ps |
| T204 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1266657094 |
|
|
May 28 05:20:48 AM PDT 23 |
May 28 05:21:08 AM PDT 23 |
1048305332 ps |
| T364 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.950205657 |
|
|
May 28 05:20:34 AM PDT 23 |
May 28 05:20:38 AM PDT 23 |
196803776 ps |
| T365 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1829762690 |
|
|
May 28 05:21:07 AM PDT 23 |
May 28 05:21:10 AM PDT 23 |
340175643 ps |
| T366 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.551080679 |
|
|
May 28 05:21:09 AM PDT 23 |
May 28 05:21:12 AM PDT 23 |
68674586 ps |
| T229 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1035243798 |
|
|
May 28 05:20:32 AM PDT 23 |
May 28 05:20:39 AM PDT 23 |
1150803290 ps |
| T367 |
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2078035294 |
|
|
May 28 05:21:13 AM PDT 23 |
May 28 05:21:17 AM PDT 23 |
58840577 ps |
| T205 |
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1457399552 |
|
|
May 28 05:21:11 AM PDT 23 |
May 28 05:21:14 AM PDT 23 |
75903054 ps |
| T178 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1786689563 |
|
|
May 28 05:21:20 AM PDT 23 |
May 28 05:21:22 AM PDT 23 |
86279308 ps |
| T368 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2786592341 |
|
|
May 28 05:20:33 AM PDT 23 |
May 28 05:20:47 AM PDT 23 |
3181176564 ps |
| T234 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2262643905 |
|
|
May 28 05:21:20 AM PDT 23 |
May 28 05:21:31 AM PDT 23 |
436121152 ps |
| T230 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3632053940 |
|
|
May 28 05:21:15 AM PDT 23 |
May 28 05:21:23 AM PDT 23 |
292990123 ps |
| T369 |
/workspace/coverage/cover_reg_top/42.spi_device_intr_test.2987626731 |
|
|
May 28 05:21:23 AM PDT 23 |
May 28 05:21:24 AM PDT 23 |
13120118 ps |
| T179 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.501756072 |
|
|
May 28 05:21:11 AM PDT 23 |
May 28 05:21:13 AM PDT 23 |
57109399 ps |
| T180 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3105301725 |
|
|
May 28 05:20:35 AM PDT 23 |
May 28 05:20:36 AM PDT 23 |
58620565 ps |
| T370 |
/workspace/coverage/cover_reg_top/30.spi_device_intr_test.1562488662 |
|
|
May 28 05:21:22 AM PDT 23 |
May 28 05:21:23 AM PDT 23 |
11540386 ps |
| T371 |
/workspace/coverage/cover_reg_top/32.spi_device_intr_test.3979589412 |
|
|
May 28 05:21:23 AM PDT 23 |
May 28 05:21:24 AM PDT 23 |
17566443 ps |
| T372 |
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.3486939398 |
|
|
May 28 05:20:34 AM PDT 23 |
May 28 05:20:35 AM PDT 23 |
20322084 ps |
| T235 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.358557979 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:31 AM PDT 23 |
815464237 ps |
| T373 |
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.887838320 |
|
|
May 28 05:21:15 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
34048656 ps |
| T181 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2717974399 |
|
|
May 28 05:20:34 AM PDT 23 |
May 28 05:20:41 AM PDT 23 |
290053204 ps |
| T374 |
/workspace/coverage/cover_reg_top/7.spi_device_intr_test.2492569831 |
|
|
May 28 05:21:11 AM PDT 23 |
May 28 05:21:12 AM PDT 23 |
85668620 ps |
| T206 |
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.764298466 |
|
|
May 28 05:20:32 AM PDT 23 |
May 28 05:20:34 AM PDT 23 |
84610804 ps |
| T207 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.769870528 |
|
|
May 28 05:21:16 AM PDT 23 |
May 28 05:21:18 AM PDT 23 |
153927611 ps |
| T375 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3865747258 |
|
|
May 28 05:20:35 AM PDT 23 |
May 28 05:20:40 AM PDT 23 |
138161587 ps |
| T184 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2531787140 |
|
|
May 28 05:20:34 AM PDT 23 |
May 28 05:20:41 AM PDT 23 |
396382295 ps |
| T376 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4087355657 |
|
|
May 28 05:20:33 AM PDT 23 |
May 28 05:20:36 AM PDT 23 |
35855008 ps |
| T377 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3148432124 |
|
|
May 28 05:21:13 AM PDT 23 |
May 28 05:21:18 AM PDT 23 |
798205767 ps |
| T378 |
/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1657343019 |
|
|
May 28 05:21:12 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
361258944 ps |
| T379 |
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.940886078 |
|
|
May 28 05:21:15 AM PDT 23 |
May 28 05:21:20 AM PDT 23 |
66584148 ps |
| T231 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3733564530 |
|
|
May 28 05:21:15 AM PDT 23 |
May 28 05:21:38 AM PDT 23 |
1688589433 ps |
| T380 |
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.57319873 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:19 AM PDT 23 |
1401367985 ps |
| T381 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2224144134 |
|
|
May 28 05:20:33 AM PDT 23 |
May 28 05:20:40 AM PDT 23 |
105644299 ps |
| T185 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3762148386 |
|
|
May 28 05:20:35 AM PDT 23 |
May 28 05:20:42 AM PDT 23 |
785604025 ps |
| T382 |
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.4169998102 |
|
|
May 28 05:21:23 AM PDT 23 |
May 28 05:21:24 AM PDT 23 |
31929924 ps |
| T383 |
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.259764749 |
|
|
May 28 05:21:12 AM PDT 23 |
May 28 05:21:15 AM PDT 23 |
90198197 ps |
| T232 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3281801725 |
|
|
May 28 05:21:03 AM PDT 23 |
May 28 05:21:25 AM PDT 23 |
1009889526 ps |
| T384 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1236014249 |
|
|
May 28 05:21:13 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
100240438 ps |
| T385 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4207986122 |
|
|
May 28 05:21:06 AM PDT 23 |
May 28 05:21:08 AM PDT 23 |
14767334 ps |
| T386 |
/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1460334732 |
|
|
May 28 05:20:32 AM PDT 23 |
May 28 05:20:34 AM PDT 23 |
85550948 ps |
| T387 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.2639420878 |
|
|
May 28 05:21:13 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
16576394 ps |
| T388 |
/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3336348705 |
|
|
May 28 05:21:04 AM PDT 23 |
May 28 05:21:08 AM PDT 23 |
1333816201 ps |
| T389 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1924239601 |
|
|
May 28 05:21:16 AM PDT 23 |
May 28 05:21:18 AM PDT 23 |
20534698 ps |
| T390 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.303734626 |
|
|
May 28 05:20:30 AM PDT 23 |
May 28 05:20:31 AM PDT 23 |
75192415 ps |
| T391 |
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.692272075 |
|
|
May 28 05:20:29 AM PDT 23 |
May 28 05:20:32 AM PDT 23 |
147494812 ps |
| T186 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2104345363 |
|
|
May 28 05:20:29 AM PDT 23 |
May 28 05:20:38 AM PDT 23 |
145878528 ps |
| T392 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.892889467 |
|
|
May 28 05:21:15 AM PDT 23 |
May 28 05:21:33 AM PDT 23 |
1722883015 ps |
| T393 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3029110493 |
|
|
May 28 05:21:19 AM PDT 23 |
May 28 05:21:23 AM PDT 23 |
31250037 ps |
| T394 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1134129135 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:18 AM PDT 23 |
345473644 ps |
| T395 |
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.1814198859 |
|
|
May 28 05:21:16 AM PDT 23 |
May 28 05:21:17 AM PDT 23 |
15385532 ps |
| T396 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1761831469 |
|
|
May 28 05:21:11 AM PDT 23 |
May 28 05:21:13 AM PDT 23 |
25803171 ps |
| T397 |
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2498615752 |
|
|
May 28 05:21:11 AM PDT 23 |
May 28 05:21:13 AM PDT 23 |
164900873 ps |
| T398 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1929308104 |
|
|
May 28 05:20:28 AM PDT 23 |
May 28 05:20:30 AM PDT 23 |
132874438 ps |
| T399 |
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4097262202 |
|
|
May 28 05:20:37 AM PDT 23 |
May 28 05:20:41 AM PDT 23 |
94850827 ps |
| T400 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.3488199082 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
17058215 ps |
| T401 |
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3703479787 |
|
|
May 28 05:21:04 AM PDT 23 |
May 28 05:21:08 AM PDT 23 |
118218618 ps |
| T187 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1751597968 |
|
|
May 28 05:21:02 AM PDT 23 |
May 28 05:21:04 AM PDT 23 |
108481588 ps |
| T402 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1295302465 |
|
|
May 28 05:21:00 AM PDT 23 |
May 28 05:21:02 AM PDT 23 |
72181427 ps |
| T403 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3990756565 |
|
|
May 28 05:20:32 AM PDT 23 |
May 28 05:20:45 AM PDT 23 |
3935837035 ps |
| T404 |
/workspace/coverage/cover_reg_top/34.spi_device_intr_test.964666101 |
|
|
May 28 05:21:22 AM PDT 23 |
May 28 05:21:23 AM PDT 23 |
45546425 ps |
| T405 |
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.564626966 |
|
|
May 28 05:21:15 AM PDT 23 |
May 28 05:21:17 AM PDT 23 |
19720548 ps |
| T406 |
/workspace/coverage/cover_reg_top/1.spi_device_intr_test.718348170 |
|
|
May 28 05:20:34 AM PDT 23 |
May 28 05:20:35 AM PDT 23 |
56025476 ps |
| T233 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1266352893 |
|
|
May 28 05:21:05 AM PDT 23 |
May 28 05:21:21 AM PDT 23 |
2604511801 ps |
| T407 |
/workspace/coverage/cover_reg_top/26.spi_device_intr_test.3412144340 |
|
|
May 28 05:21:15 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
78213482 ps |
| T408 |
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2063893038 |
|
|
May 28 05:20:48 AM PDT 23 |
May 28 05:20:50 AM PDT 23 |
136384598 ps |
| T409 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4065736415 |
|
|
May 28 05:20:29 AM PDT 23 |
May 28 05:20:30 AM PDT 23 |
74808800 ps |
| T410 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1940597823 |
|
|
May 28 05:21:13 AM PDT 23 |
May 28 05:21:17 AM PDT 23 |
42706086 ps |
| T411 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.30967564 |
|
|
May 28 05:20:29 AM PDT 23 |
May 28 05:20:31 AM PDT 23 |
120012982 ps |
| T412 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.690122089 |
|
|
May 28 05:21:13 AM PDT 23 |
May 28 05:21:22 AM PDT 23 |
452319479 ps |
| T413 |
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.1711735815 |
|
|
May 28 05:20:36 AM PDT 23 |
May 28 05:20:37 AM PDT 23 |
16784300 ps |
| T414 |
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.1589394131 |
|
|
May 28 05:21:15 AM PDT 23 |
May 28 05:21:17 AM PDT 23 |
83946514 ps |
| T415 |
/workspace/coverage/cover_reg_top/49.spi_device_intr_test.184547187 |
|
|
May 28 05:21:23 AM PDT 23 |
May 28 05:21:24 AM PDT 23 |
17781434 ps |
| T416 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3126851216 |
|
|
May 28 05:20:41 AM PDT 23 |
May 28 05:20:46 AM PDT 23 |
153122062 ps |
| T417 |
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.382685963 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:17 AM PDT 23 |
56485095 ps |
| T236 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2824380139 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:37 AM PDT 23 |
1997999565 ps |
| T418 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3851906142 |
|
|
May 28 05:20:45 AM PDT 23 |
May 28 05:21:03 AM PDT 23 |
1122183549 ps |
| T419 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1926841508 |
|
|
May 28 05:21:12 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
511480179 ps |
| T420 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3177159575 |
|
|
May 28 05:21:08 AM PDT 23 |
May 28 05:21:09 AM PDT 23 |
24892899 ps |
| T421 |
/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3332238724 |
|
|
May 28 05:20:44 AM PDT 23 |
May 28 05:20:46 AM PDT 23 |
80657679 ps |
| T237 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.453060788 |
|
|
May 28 05:21:13 AM PDT 23 |
May 28 05:21:34 AM PDT 23 |
1183585346 ps |
| T422 |
/workspace/coverage/cover_reg_top/29.spi_device_intr_test.2919231621 |
|
|
May 28 05:21:13 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
39918485 ps |
| T423 |
/workspace/coverage/cover_reg_top/35.spi_device_intr_test.3903426098 |
|
|
May 28 05:21:22 AM PDT 23 |
May 28 05:21:23 AM PDT 23 |
69122046 ps |
| T424 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2573149248 |
|
|
May 28 05:21:04 AM PDT 23 |
May 28 05:21:08 AM PDT 23 |
64923703 ps |
| T425 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2672123896 |
|
|
May 28 05:21:15 AM PDT 23 |
May 28 05:21:18 AM PDT 23 |
27530428 ps |
| T426 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.943082739 |
|
|
May 28 05:20:41 AM PDT 23 |
May 28 05:20:46 AM PDT 23 |
234279508 ps |
| T427 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.502436404 |
|
|
May 28 05:21:08 AM PDT 23 |
May 28 05:21:11 AM PDT 23 |
87534925 ps |
| T428 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2613201638 |
|
|
May 28 05:20:32 AM PDT 23 |
May 28 05:20:34 AM PDT 23 |
76923930 ps |
| T429 |
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.2554098884 |
|
|
May 28 05:21:22 AM PDT 23 |
May 28 05:21:23 AM PDT 23 |
75119439 ps |
| T430 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2357694379 |
|
|
May 28 05:21:09 AM PDT 23 |
May 28 05:21:14 AM PDT 23 |
575097575 ps |
| T431 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1208227692 |
|
|
May 28 05:20:37 AM PDT 23 |
May 28 05:20:47 AM PDT 23 |
443152545 ps |
| T432 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1531975307 |
|
|
May 28 05:21:15 AM PDT 23 |
May 28 05:21:22 AM PDT 23 |
228440949 ps |
| T433 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1657344720 |
|
|
May 28 05:20:33 AM PDT 23 |
May 28 05:20:35 AM PDT 23 |
40727429 ps |
| T434 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3952019234 |
|
|
May 28 05:21:13 AM PDT 23 |
May 28 05:21:28 AM PDT 23 |
2303479098 ps |
| T435 |
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.1090392212 |
|
|
May 28 05:21:13 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
19129237 ps |
| T436 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.245523833 |
|
|
May 28 05:20:34 AM PDT 23 |
May 28 05:20:36 AM PDT 23 |
77637303 ps |
| T437 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3412780716 |
|
|
May 28 05:20:30 AM PDT 23 |
May 28 05:20:35 AM PDT 23 |
63813170 ps |
| T438 |
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.2504675940 |
|
|
May 28 05:21:15 AM PDT 23 |
May 28 05:21:17 AM PDT 23 |
41748965 ps |
| T439 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3201014417 |
|
|
May 28 05:20:31 AM PDT 23 |
May 28 05:20:44 AM PDT 23 |
755545293 ps |
| T440 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1831380783 |
|
|
May 28 05:21:12 AM PDT 23 |
May 28 05:21:15 AM PDT 23 |
69474683 ps |
| T441 |
/workspace/coverage/cover_reg_top/43.spi_device_intr_test.258334941 |
|
|
May 28 05:21:15 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
53499544 ps |
| T442 |
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.1989428732 |
|
|
May 28 05:21:20 AM PDT 23 |
May 28 05:21:21 AM PDT 23 |
50734077 ps |
| T443 |
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.1601546455 |
|
|
May 28 05:21:13 AM PDT 23 |
May 28 05:21:15 AM PDT 23 |
26126126 ps |
| T444 |
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.3755965904 |
|
|
May 28 05:21:12 AM PDT 23 |
May 28 05:21:13 AM PDT 23 |
14701090 ps |
| T445 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3268263580 |
|
|
May 28 05:21:09 AM PDT 23 |
May 28 05:21:13 AM PDT 23 |
194494607 ps |
| T446 |
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.1527033180 |
|
|
May 28 05:21:23 AM PDT 23 |
May 28 05:21:24 AM PDT 23 |
15324971 ps |
| T447 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3520510789 |
|
|
May 28 05:20:34 AM PDT 23 |
May 28 05:20:58 AM PDT 23 |
14857988811 ps |
| T448 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.576911181 |
|
|
May 28 05:20:33 AM PDT 23 |
May 28 05:20:35 AM PDT 23 |
401290796 ps |
| T449 |
/workspace/coverage/cover_reg_top/33.spi_device_intr_test.3907265662 |
|
|
May 28 05:21:22 AM PDT 23 |
May 28 05:21:23 AM PDT 23 |
28584776 ps |
| T450 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2982195956 |
|
|
May 28 05:20:40 AM PDT 23 |
May 28 05:20:42 AM PDT 23 |
86096540 ps |
| T451 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.86911780 |
|
|
May 28 05:20:47 AM PDT 23 |
May 28 05:20:48 AM PDT 23 |
38725476 ps |
| T452 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2656653218 |
|
|
May 28 05:20:30 AM PDT 23 |
May 28 05:20:39 AM PDT 23 |
375838463 ps |
| T453 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2848506149 |
|
|
May 28 05:20:37 AM PDT 23 |
May 28 05:20:38 AM PDT 23 |
62206786 ps |
| T454 |
/workspace/coverage/cover_reg_top/44.spi_device_intr_test.3052405635 |
|
|
May 28 05:21:23 AM PDT 23 |
May 28 05:21:24 AM PDT 23 |
18682466 ps |
| T455 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.649942792 |
|
|
May 28 05:20:39 AM PDT 23 |
May 28 05:20:41 AM PDT 23 |
87856824 ps |
| T456 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3235920880 |
|
|
May 28 05:21:10 AM PDT 23 |
May 28 05:21:12 AM PDT 23 |
53011122 ps |
| T457 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3334079209 |
|
|
May 28 05:20:29 AM PDT 23 |
May 28 05:20:32 AM PDT 23 |
89474051 ps |
| T458 |
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.2029890764 |
|
|
May 28 05:21:11 AM PDT 23 |
May 28 05:21:11 AM PDT 23 |
12897210 ps |
| T459 |
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.3560834220 |
|
|
May 28 05:21:14 AM PDT 23 |
May 28 05:21:16 AM PDT 23 |
25342408 ps |
| T460 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2633259320 |
|
|
May 28 05:21:07 AM PDT 23 |
May 28 05:21:10 AM PDT 23 |
38168397 ps |
| T461 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1999280941 |
|
|
May 28 05:20:48 AM PDT 23 |
May 28 05:21:01 AM PDT 23 |
707837785 ps |
| T462 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2924980110 |
|
|
May 28 05:20:40 AM PDT 23 |
May 28 05:21:14 AM PDT 23 |
596442696 ps |
| T238 |
/workspace/coverage/default/18.spi_device_bit_transfer.1089934495 |
|
|
May 28 03:40:58 AM PDT 23 |
May 28 03:41:01 AM PDT 23 |
2143752514 ps |
| T8 |
/workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.584399945 |
|
|
May 28 03:52:54 AM PDT 23 |
May 28 03:53:29 AM PDT 23 |
54913105621 ps |
| T125 |
/workspace/coverage/default/1.spi_device_perf.44081562 |
|
|
May 28 03:35:11 AM PDT 23 |
May 28 03:37:12 AM PDT 23 |
7649607291 ps |
| T126 |
/workspace/coverage/default/25.spi_device_fifo_full.362040032 |
|
|
May 28 03:43:32 AM PDT 23 |
May 28 04:29:19 AM PDT 23 |
104133111781 ps |
| T241 |
/workspace/coverage/default/46.spi_device_dummy_item_extra_dly.1241112625 |
|
|
May 28 03:52:12 AM PDT 23 |
May 28 03:53:50 AM PDT 23 |
43376789273 ps |
| T94 |
/workspace/coverage/default/10.spi_device_ram_cfg.367027763 |
|
|
May 28 03:38:45 AM PDT 23 |
May 28 03:38:46 AM PDT 23 |
15932551 ps |
| T32 |
/workspace/coverage/default/6.spi_device_flash_and_tpm.1872649160 |
|
|
May 28 03:37:33 AM PDT 23 |
May 28 03:43:30 AM PDT 23 |
49822762085 ps |
| T69 |
/workspace/coverage/default/47.spi_device_tpm_read_hw_reg.390033585 |
|
|
May 28 03:52:11 AM PDT 23 |
May 28 03:52:25 AM PDT 23 |
4951584832 ps |
| T70 |
/workspace/coverage/default/9.spi_device_tx_async_fifo_reset.661842506 |
|
|
May 28 03:38:25 AM PDT 23 |
May 28 03:38:26 AM PDT 23 |
16200379 ps |
| T71 |
/workspace/coverage/default/1.spi_device_abort.2912927918 |
|
|
May 28 03:35:11 AM PDT 23 |
May 28 03:35:12 AM PDT 23 |
20950962 ps |
| T23 |
/workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2923992463 |
|
|
May 28 03:46:56 AM PDT 23 |
May 28 03:47:01 AM PDT 23 |
155960476 ps |
| T21 |
/workspace/coverage/default/7.spi_device_cfg_cmd.2758899886 |
|
|
May 28 03:37:31 AM PDT 23 |
May 28 03:37:35 AM PDT 23 |
1043262266 ps |
| T113 |
/workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3061239981 |
|
|
May 28 03:44:10 AM PDT 23 |
May 28 03:44:14 AM PDT 23 |
670604693 ps |
| T115 |
/workspace/coverage/default/36.spi_device_fifo_underflow_overflow.1466876542 |
|
|
May 28 03:48:04 AM PDT 23 |
May 28 04:01:30 AM PDT 23 |
385177457502 ps |
| T79 |
/workspace/coverage/default/16.spi_device_alert_test.1437993498 |
|
|
May 28 03:40:57 AM PDT 23 |
May 28 03:40:58 AM PDT 23 |
14252488 ps |
| T77 |
/workspace/coverage/default/12.spi_device_rx_async_fifo_reset.2881744277 |
|
|
May 28 03:39:36 AM PDT 23 |
May 28 03:39:37 AM PDT 23 |
32357326 ps |
| T147 |
/workspace/coverage/default/38.spi_device_intercept.584213201 |
|
|
May 28 03:48:33 AM PDT 23 |
May 28 03:48:36 AM PDT 23 |
183274642 ps |
| T78 |
/workspace/coverage/default/19.spi_device_rx_async_fifo_reset.711776208 |
|
|
May 28 03:41:41 AM PDT 23 |
May 28 03:41:43 AM PDT 23 |
38774267 ps |
| T19 |
/workspace/coverage/default/42.spi_device_mailbox.3943013219 |
|
|
May 28 03:51:40 AM PDT 23 |
May 28 03:51:46 AM PDT 23 |
737716852 ps |
| T148 |
/workspace/coverage/default/11.spi_device_cfg_cmd.944974466 |
|
|
May 28 03:38:50 AM PDT 23 |
May 28 03:38:57 AM PDT 23 |
1911468206 ps |
| T239 |
/workspace/coverage/default/44.spi_device_dummy_item_extra_dly.686918242 |
|
|
May 28 03:51:35 AM PDT 23 |
May 28 03:53:36 AM PDT 23 |
96506614172 ps |
| T284 |
/workspace/coverage/default/35.spi_device_cfg_cmd.115545331 |
|
|
May 28 03:48:04 AM PDT 23 |
May 28 03:48:09 AM PDT 23 |
4505717637 ps |
| T289 |
/workspace/coverage/default/24.spi_device_cfg_cmd.136232502 |
|
|
May 28 03:43:31 AM PDT 23 |
May 28 03:43:35 AM PDT 23 |
204762764 ps |
| T114 |
/workspace/coverage/default/18.spi_device_tpm_all.1026982425 |
|
|
May 28 03:40:54 AM PDT 23 |
May 28 03:44:00 AM PDT 23 |
45258543294 ps |
| T144 |
/workspace/coverage/default/48.spi_device_rx_async_fifo_reset.3501789374 |
|
|
May 28 03:52:56 AM PDT 23 |
May 28 03:52:57 AM PDT 23 |
32256063 ps |
| T22 |
/workspace/coverage/default/13.spi_device_flash_all.1587176561 |
|
|
May 28 03:39:38 AM PDT 23 |
May 28 03:40:10 AM PDT 23 |
10466175585 ps |
| T76 |
/workspace/coverage/default/34.spi_device_tx_async_fifo_reset.1666967866 |
|
|
May 28 03:47:19 AM PDT 23 |
May 28 03:47:20 AM PDT 23 |
17202170 ps |
| T120 |
/workspace/coverage/default/20.spi_device_tpm_sts_read.2103240502 |
|
|
May 28 03:42:18 AM PDT 23 |
May 28 03:42:19 AM PDT 23 |
161183674 ps |
| T131 |
/workspace/coverage/default/40.spi_device_rx_timeout.2447905182 |
|
|
May 28 03:49:53 AM PDT 23 |
May 28 03:49:59 AM PDT 23 |
1082417075 ps |
| T121 |
/workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1092335672 |
|
|
May 28 03:51:42 AM PDT 23 |
May 28 03:52:10 AM PDT 23 |
11151264649 ps |
| T202 |
/workspace/coverage/default/37.spi_device_bit_transfer.1731756527 |
|
|
May 28 03:48:28 AM PDT 23 |
May 28 03:48:31 AM PDT 23 |
218441344 ps |
| T203 |
/workspace/coverage/default/44.spi_device_perf.4062742404 |
|
|
May 28 03:51:34 AM PDT 23 |
May 28 04:00:59 AM PDT 23 |
18669830468 ps |
| T463 |
/workspace/coverage/default/20.spi_device_csb_read.56112738 |
|
|
May 28 03:42:13 AM PDT 23 |
May 28 03:42:14 AM PDT 23 |
16117619 ps |
| T34 |
/workspace/coverage/default/34.spi_device_flash_mode.3225022591 |
|
|
May 28 03:47:17 AM PDT 23 |
May 28 03:47:36 AM PDT 23 |
1649107043 ps |
| T24 |
/workspace/coverage/default/42.spi_device_pass_cmd_filtering.3664083186 |
|
|
May 28 03:51:35 AM PDT 23 |
May 28 03:51:57 AM PDT 23 |
8282513266 ps |
| T240 |
/workspace/coverage/default/33.spi_device_bit_transfer.4243901548 |
|
|
May 28 03:47:16 AM PDT 23 |
May 28 03:47:19 AM PDT 23 |
222667740 ps |
| T145 |
/workspace/coverage/default/21.spi_device_rx_async_fifo_reset.1715691368 |
|
|
May 28 03:42:28 AM PDT 23 |
May 28 03:42:30 AM PDT 23 |
28190331 ps |
| T122 |
/workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3193151832 |
|
|
May 28 03:38:41 AM PDT 23 |
May 28 03:38:58 AM PDT 23 |
5872218989 ps |
| T123 |
/workspace/coverage/default/33.spi_device_tpm_sts_read.4076711867 |
|
|
May 28 03:47:19 AM PDT 23 |
May 28 03:47:21 AM PDT 23 |
415332298 ps |
| T137 |
/workspace/coverage/default/20.spi_device_upload.1855372531 |
|
|
May 28 03:42:17 AM PDT 23 |
May 28 03:42:44 AM PDT 23 |
27153597381 ps |
| T80 |
/workspace/coverage/default/3.spi_device_alert_test.3881321138 |
|
|
May 28 03:35:39 AM PDT 23 |
May 28 03:35:40 AM PDT 23 |
44134945 ps |
| T138 |
/workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1179931131 |
|
|
May 28 03:42:15 AM PDT 23 |
May 28 03:42:21 AM PDT 23 |
467901004 ps |
| T18 |
/workspace/coverage/default/2.spi_device_flash_and_tpm.2256504217 |
|
|
May 28 03:35:49 AM PDT 23 |
May 28 03:40:44 AM PDT 23 |
72031682048 ps |
| T36 |
/workspace/coverage/default/41.spi_device_read_buffer_direct.668036050 |
|
|
May 28 03:50:08 AM PDT 23 |
May 28 03:50:13 AM PDT 23 |
933157169 ps |