Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.61	98.96	95.60	98.63	92.06	97.97	87.00	78.04

Total tests in report: 1760

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
50.21	50.21	48.16	48.16	38.71	38.71	68.49	68.49	95.08	95.08	45.00	45.00	46.53	46.53	9.53	9.53	/workspace/coverage/cover_reg_top/42.spi_device_intr_test.101165969677814654800782515585059569200110120461157843728613113038387981833111
68.66	18.44	73.12	24.95	52.74	14.03	83.46	14.97	95.08	0.00	61.91	16.92	79.47	32.94	34.83	25.30	/workspace/coverage/default/22.spi_device_flash_all.76553753937021290167755817695430105719036708791989432525331269666745491536780
83.77	15.11	96.02	22.90	89.08	36.34	89.73	6.26	95.08	0.00	93.87	31.96	79.91	0.44	42.69	7.86	/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.10668466422549898539374226145071506156071874984733250471342504520178709310485
89.63	5.86	98.49	2.47	93.69	4.62	93.74	4.01	95.08	0.00	97.38	3.51	84.19	4.28	64.84	22.15	/workspace/coverage/default/37.spi_device_stress_all.87204300542036997945253576403153662308538775897360540897471021326188571770063
90.66	1.03	98.59	0.10	93.81	0.11	93.74	0.00	95.08	0.00	97.58	0.20	84.19	0.00	71.65	6.81	/workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.108328025936217573377299478321734483321103940430129025420183953742611253273546
91.22	0.56	98.60	0.01	93.81	0.00	97.65	3.91	95.08	0.00	97.58	0.00	84.19	0.00	71.65	0.00	/workspace/coverage/default/11.spi_device_ram_cfg.15853190593084721381298686010862706645056121321225417331720496768554882481171
91.63	0.40	98.68	0.07	94.77	0.96	98.04	0.39	95.08	0.00	97.61	0.03	84.79	0.59	72.42	0.76	/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.67897978383399150438114356039950275516051026276868321171446337272803026350235
91.98	0.35	98.68	0.00	94.77	0.00	98.04	0.00	95.08	0.00	97.61	0.00	84.79	0.00	74.89	2.48	/workspace/coverage/default/32.spi_device_flash_and_tpm.99643764227489952763121775829686744698317403206129120939518024419791768260691
92.21	0.23	98.79	0.11	95.27	0.49	98.04	0.00	95.08	0.00	97.76	0.15	85.38	0.59	75.13	0.24	/workspace/coverage/default/3.spi_device_flash_mode.106893959945057611637377373334001243038447966657819016305272476248049579188717
92.43	0.22	98.79	0.00	95.27	0.00	98.04	0.00	95.08	0.00	97.76	0.00	85.38	0.00	76.66	1.52	/workspace/coverage/default/11.spi_device_tpm_all.31641826720742955947647429715623796828897018260121434931539424864757494430846
92.60	0.18	98.80	0.01	95.29	0.03	98.04	0.00	95.08	0.00	97.78	0.02	86.56	1.18	76.66	0.00	/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.26591066936258500164536786830045957316369083235215273726849322819878915917772
92.72	0.12	98.80	0.00	95.32	0.03	98.63	0.59	95.08	0.00	97.78	0.00	86.71	0.15	76.75	0.10	/workspace/coverage/default/2.spi_device_sec_cm.90273524494379863512109695086468271756521519372454875112381304452252492962311
92.78	0.05	98.80	0.00	95.34	0.03	98.63	0.00	95.08	0.00	97.78	0.00	86.71	0.00	77.08	0.33	/workspace/coverage/default/24.spi_device_bit_transfer.86448545595863882098712976173084638421165646782234800400718288150618080012155
92.81	0.03	98.83	0.03	95.34	0.00	98.63	0.00	95.08	0.00	97.80	0.02	86.85	0.15	77.13	0.05	/workspace/coverage/default/1.spi_device_fifo_underflow_overflow.108857050503628104614555628756408373926110006330271550561118474410757069890501
92.84	0.03	98.83	0.00	95.34	0.00	98.63	0.00	95.08	0.00	97.80	0.00	86.85	0.00	77.37	0.24	/workspace/coverage/default/10.spi_device_tpm_read_hw_reg.44490845027611117122189290780777481014582112787073390825565802763740713763754
92.88	0.03	98.88	0.06	95.43	0.09	98.63	0.00	95.08	0.00	97.88	0.08	86.85	0.00	77.37	0.00	/workspace/coverage/default/0.spi_device_mem_parity.87818129535426790687255279581642267262192763815610896627828055274335654371814
92.91	0.03	98.90	0.02	95.47	0.04	98.63	0.00	95.08	0.00	97.88	0.00	87.00	0.15	77.37	0.00	/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.95638137819186236774490369072294862667858409369965022218317768804830923533728
92.93	0.03	98.90	0.00	95.47	0.00	98.63	0.00	95.08	0.00	97.88	0.00	87.00	0.00	77.56	0.19	/workspace/coverage/default/29.spi_device_extreme_fifo_size.2276629521646143041510203800751762051420710605340325368768650893109964255348
92.96	0.03	98.94	0.04	95.52	0.05	98.63	0.00	95.08	0.00	97.93	0.05	87.00	0.00	77.61	0.05	/workspace/coverage/default/17.spi_device_rx_timeout.86892263901533218724297221263282669606442887141731754848660528649957776850708
92.97	0.01	98.94	0.00	95.52	0.00	98.63	0.00	95.08	0.00	97.93	0.00	87.00	0.00	77.70	0.10	/workspace/coverage/default/0.spi_device_intercept.55960093424964298814754624847823848391423038321093634807786103557107029709931
92.99	0.01	98.94	0.00	95.52	0.00	98.63	0.00	95.08	0.00	97.93	0.00	87.00	0.00	77.80	0.10	/workspace/coverage/default/14.spi_device_fifo_full.111724296085073996504190575539276696859507984666905321259085853048735563749852
93.00	0.01	98.95	0.01	95.52	0.00	98.63	0.00	95.08	0.00	97.95	0.02	87.00	0.00	77.85	0.05	/workspace/coverage/default/26.spi_device_pass_addr_payload_swap.85664651188082800099885163163691138583497761594665803035594053726695238551606
93.00	0.01	98.95	0.00	95.52	0.00	98.63	0.00	95.08	0.00	97.95	0.00	87.00	0.00	77.89	0.05	/workspace/coverage/default/1.spi_device_mailbox.21514572648949558130156439819733201161971710920294170923181230196139176439549
93.01	0.01	98.95	0.00	95.52	0.00	98.63	0.00	95.08	0.00	97.95	0.00	87.00	0.00	77.94	0.05	/workspace/coverage/default/10.spi_device_pass_cmd_filtering.42899711490924321813764756372628336715747470347367998335275682288835916282428
93.02	0.01	98.95	0.00	95.52	0.00	98.63	0.00	95.08	0.00	97.95	0.00	87.00	0.00	77.99	0.05	/workspace/coverage/default/14.spi_device_smoke.56874677421016076217924683869789080075456384257632046168489784916774237459129
93.02	0.01	98.95	0.00	95.52	0.00	98.63	0.00	95.08	0.00	97.95	0.00	87.00	0.00	78.04	0.05	/workspace/coverage/default/14.spi_device_tpm_rw.97895523352464323008367794156578725313358443198903312110512804114757246400874
93.03	0.01	98.96	0.01	95.53	0.01	98.63	0.00	95.08	0.00	97.97	0.02	87.00	0.00	78.04	0.00	/workspace/coverage/default/11.spi_device_abort.1943025359533907669775249437624103207796778732468802364786295869472521805183
93.03	0.01	98.96	0.00	95.56	0.03	98.63	0.00	95.08	0.00	97.97	0.00	87.00	0.00	78.04	0.00	/workspace/coverage/default/10.spi_device_alert_test.88711439312725551370087959545807360483413355991743323643013011758595618246677
93.04	0.01	98.96	0.00	95.57	0.01	98.63	0.00	95.08	0.00	97.97	0.00	87.00	0.00	78.04	0.00	/workspace/coverage/default/0.spi_device_tx_async_fifo_reset.7935976241365926701331148594984956595992246538737982764446072823707765177343
93.04	0.01	98.96	0.00	95.58	0.01	98.63	0.00	95.08	0.00	97.97	0.00	87.00	0.00	78.04	0.00	/workspace/coverage/default/10.spi_device_csb_read.94050924123517652297199916452211244549652697135056701672469565723592943884452
93.04	0.01	98.96	0.00	95.60	0.01	98.63	0.00	95.08	0.00	97.97	0.00	87.00	0.00	78.04	0.00	/workspace/coverage/default/18.spi_device_rx_async_fifo_reset.101078663550490996210436170430087922557879784786953115375826113769205010551706

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.43458886114065712722048291599232128002399483901534456017063823133949163072
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.37187410455266229691789802058795304299552583192296442995104564990910931351800
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.90971211343230039674128993052687224933451255701474945275003287168150981585662
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.59643638243443201344132721301587203942978470648801148721050464869489230408981
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.64071177430913791381727691652557695794343016468330126062775479537897182746487
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.104618610112214422133355289378380836656499539412191601483900894698470750333621
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.69615829648555403138055469659645528061691210614893912704141865605835056612784
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.82188963063138211497106906490457503707330839740108246761333063181957640063437
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.31691173293474391802363964561235814284902742130262725645309678686208402509154
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.77996998090599118596038918244394642879864951211053241116160287743776561452578
/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.109747694041649347679895077251587542770920060638946781085249462468930376255704
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.77262486508128143072297797372031648400312371228635704415283249152741643040364
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.65954128909289717962492376237752505909388005223221824343241599788703040562542
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.10733402436015032696445056541693076427279799495677376312919995263703911483198
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.62920779274939540248722009133142137069552772500670584179813134791550624095084
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.32851738091733796507088579129097328017563557841788141802183327809529779112025
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.84841158105251214174956237953889221543996399794271149394914559951663253102239
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.64996065428083744670621027215234710393507848266933110168522809792860693201104
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.111141378901603832950807858638391686643971946858732655669495603103308843707001
/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.42953907046508137673710841428194445082154961666442650067134812681882052629157
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.107850812819909599971165310829161125981864865600670834012415943340081573136408
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.55223591363322954782533100666714968932920248965849254648441649525684398920978
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.60265630276690422418394536673225708996111201731401577062248730275228607038972
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.7729065829898248417111213362530180017303811246092469566991423647003634623555
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.34140359908293714346901021040546954949464747644055768416591128656399164234590
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.67227538339000538856060033962220410117635072000800032768180532104013359128982
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.94940383936668008118760367905361426385684046209383854926985424525007133843817
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.65139810083786030448090142042476491956931867190146724297927136326227427448735
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.89025962076860686554115450855996181451100398749115222986070010605545742565283
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.71027675017620676224188501794701658905143570063786802166006485162578988381170
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.57158620848908450897719575497150317448616441703052064787880101763807066414047
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.94389342077882605109596638090314611860767368968933986199974675958453601918677
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.65467508378558427718422271672205632951828899179630451132926477879528982500331
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.109526442598807181895384222518222944874286543060336942139279544822981745461288
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.60036625868627035962025303202613653610873133244088085820655274601188895310571
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.9868361740917363722556081293189577170905394644254646049094453253608321573963
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.63558489170691371297816609297542932075861736101895222407485412493990846524905
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.29215526748670506367920223279382841421844520824036703679719082747989070851018
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.25208873996007370067827772851131174251238781345155995489217740200054467744280
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.53385872938607386180075889254326486657841476999776623227085304749618218098723
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.23702240456313226940805984327130859309954639426539741609479055166972417354202
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.38308064984967644815454085626546348951438678605300627307473009298575760651873
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.110702215233532141836372916320651122493454031743420867398353403909532002647754
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.26257541633618103787655803727355045669667838863325252562094714349969658941432
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.15153253735602053611613806217197529212745107611614102996621302658098196056231
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.24367703314687908051491795501060035923955281677779166306725838286490422843680
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.45014504283230440170837956924642112905550760934837563242649344841813520358530
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.31554851779770835664709253363181136811584174518010755426149494749873942604957
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.39263626404935919401903513234817944314516058869607171300460843474308074768446
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.91853896360296962832474489154932354151216997136213370360230465660071724930347
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.78367750723225823786975894641436891462313024480549887866146376815647855309650
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.27590269859674216244998337085775142306638864029908691393890748622354260677298
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.23919980885273921734545701954411529652931939543811409654460700378629765183991
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.16691600111424299517308867929528809912258131591767487019407084087217705306272
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.87459150004883078169231426513300455131183265404993323317066764396041177543647
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.17830570951752079113949228739685082381062537531023715718186291964662544315602
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.93212788652307950562514497913265491501654293582712334604377471502543346262765
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.112668189864520136189772436270460231232859480477687347567809501965058059990632
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.25847842305201215395067555721015437610551065521907126904510911876538261716843
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.63553340939405164670859921034434553250560884134081053048125815601705834436464
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.40118900138057514735388956569673442816994016109510147737166160023591843316499
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1811876395559859262224254284329964751321107927117934333864822453690080341394
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.22059560749127409350644251586812685396225640638214385879500898467392437637789
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.56223070560744581625738666556551911345081549652150056509339730745990688239420
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.36588098570075236196841315935085337936972069626822418736003789850684714777321
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.33991077735933970989928831485455878848969705844252670142652415514028864333023
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.109698912951638018438839231338838892882990911203596724766457797139263684784971
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.92860277257340562548047959600733772952621852451980619636857250348307119640413
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/workspace/coverage/default/8.spi_device_extreme_fifo_size.10043792894571074331816926005182821098777315707299690516934652237848506079188
/workspace/coverage/default/8.spi_device_fifo_full.49207367121967092140975686577821712771781410252851286923991167450317704111574
/workspace/coverage/default/8.spi_device_fifo_underflow_overflow.45364222408566479530637856053467767235802958767272110423017487271665501486564
/workspace/coverage/default/8.spi_device_flash_all.89399191211501610751912655437033581925721874648741629382581939125435502449973
/workspace/coverage/default/8.spi_device_flash_and_tpm.52661346508337340223191152663686029534263777868692712740213535829978602343754
/workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.21018566056675835046267918632771667360538297155722193457060349594639197180209
/workspace/coverage/default/8.spi_device_flash_mode.33032774242309998762516142443361901435933787161500987462889635514125900637124
/workspace/coverage/default/8.spi_device_intercept.70774912699880727234094670158750233669259951483030085202303958904561792852999
/workspace/coverage/default/8.spi_device_intr.24454510241839936564915143932717634370420536640568940905010915825422267738307
/workspace/coverage/default/8.spi_device_mailbox.112520391114191901091196284924274552773010557843675414450375099229022592469799
/workspace/coverage/default/8.spi_device_mem_parity.61934190352864257828306499627796354671076640111326679456322279772391760036334
/workspace/coverage/default/8.spi_device_pass_addr_payload_swap.18922951976602705336889664902980760419115572079319763382526746335901607449705
/workspace/coverage/default/8.spi_device_pass_cmd_filtering.82185258124599095096783655720221548988923279645692704871797493633646314393359
/workspace/coverage/default/8.spi_device_perf.48886707216923028273211086646930445776036514953629061543157090138351937256286
/workspace/coverage/default/8.spi_device_read_buffer_direct.108446944655319757056881344455053229243087432657770929415435097479326410160423
/workspace/coverage/default/8.spi_device_rx_async_fifo_reset.113744767931147767402356038348658403911167993951041546267431154642604058561064
/workspace/coverage/default/8.spi_device_rx_timeout.91368418286370415154109749970957171559938543332960619185026299738471450803364
/workspace/coverage/default/8.spi_device_smoke.59670784741164487217076612574452311332370823783126595605723582808652305825689
/workspace/coverage/default/8.spi_device_stress_all.29220948354567064340334278613906385450987988947187813541458989303547158707335
/workspace/coverage/default/8.spi_device_tpm_all.57167149978356157810375138748907374822246554474139189784139483636785593795659
/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.72744910640397350436939938169381773360185748220457017603082618452648273784038
/workspace/coverage/default/8.spi_device_tpm_rw.1069356332100240160156497969599840163080310179574654307158165208288310439879
/workspace/coverage/default/8.spi_device_tpm_sts_read.4053993721672095860650664193001360717972791126894275099281384953356172297205
/workspace/coverage/default/8.spi_device_tx_async_fifo_reset.32182773355631722472941956388879174402899015955985580546111752426818459969707
/workspace/coverage/default/8.spi_device_txrx.97778731302587690024691667370483465860224989914397759932494388447999378272596
/workspace/coverage/default/8.spi_device_upload.61638077521341536646554251221860923174620360292749135160290298198896123023766
/workspace/coverage/default/9.spi_device_abort.651346971927874431250483282005606846393342525496683381838080570866615791461
/workspace/coverage/default/9.spi_device_alert_test.14273183534324630947015900185584820085515414683402793691405930926084916578327
/workspace/coverage/default/9.spi_device_bit_transfer.70109190135352797282093447131460915516941825399957474320547418155921546971922
/workspace/coverage/default/9.spi_device_byte_transfer.50898460653512943229475050401365703388220617954262378215747658445450267861674
/workspace/coverage/default/9.spi_device_cfg_cmd.12533106770335377975467027838411159981773283848807973367391552583338359371158
/workspace/coverage/default/9.spi_device_csb_read.114126583971409915350718014449341875340860457720813463282777673865009552512503
/workspace/coverage/default/9.spi_device_dummy_item_extra_dly.80748898293295269069630269732152549942947473939480393574995287557442661834409
/workspace/coverage/default/9.spi_device_extreme_fifo_size.78355833703472777560400199803157904163703883035756874638877464863314715503964
/workspace/coverage/default/9.spi_device_fifo_full.75006557689631996735246559389720092510675327429811218996599487211766571043427
/workspace/coverage/default/9.spi_device_fifo_underflow_overflow.1741901042144747737993540132920870247441603198924431043743882415365666989031
/workspace/coverage/default/9.spi_device_flash_all.62622891090741924668337738204898560916807451972770809153305969998363639806381
/workspace/coverage/default/9.spi_device_flash_and_tpm.35405913388355825953919426628170742143983068364062241284310604671623941752655
/workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.29682929854316842017955387772305137855847853231011741687616437241793124311655
/workspace/coverage/default/9.spi_device_flash_mode.30863626897359524481208827633793856596930661094850615860085987695733941711926
/workspace/coverage/default/9.spi_device_intercept.57406979113601568737749543252520198926265785950771905973668555421935577609760
/workspace/coverage/default/9.spi_device_intr.8865562627789022796927699087329737561491898035433046811072636618723059286804
/workspace/coverage/default/9.spi_device_mailbox.82321269076327257660532352411961760968175622326463966476428529818379976244123
/workspace/coverage/default/9.spi_device_mem_parity.103205790836230346529139451707956778495323106168738148177477197132064133437481
/workspace/coverage/default/9.spi_device_pass_addr_payload_swap.48992355972130630951364871102728695400912284397394492965683286495033286127190
/workspace/coverage/default/9.spi_device_perf.114969952694415576175850642389000152441826929023650961226437641860096568430407
/workspace/coverage/default/9.spi_device_ram_cfg.93659020740208477043490146726950594002783513256685415324507083236889720070800
/workspace/coverage/default/9.spi_device_read_buffer_direct.107973659234700331408586673995833068133128254329028351752044576432306549356428
/workspace/coverage/default/9.spi_device_rx_async_fifo_reset.52000724758040806851361670871760804579092942562756513898751120153164222427549
/workspace/coverage/default/9.spi_device_rx_timeout.89486995382046960545027676389530153564256331599794202921662448103354029689504
/workspace/coverage/default/9.spi_device_smoke.102015274154264831706617019689113795826790161713398101870005621212827370523324
/workspace/coverage/default/9.spi_device_stress_all.75367087612991220356604546162918639043310874614805985299118699979147137616504
/workspace/coverage/default/9.spi_device_tpm_all.16410986448553952850711889164529380956198923478553978787711826836525024646080
/workspace/coverage/default/9.spi_device_tpm_read_hw_reg.112370315627359292215638656845742040404657671344201546446465345024138217078081
/workspace/coverage/default/9.spi_device_tpm_rw.100404059054613995698055126205429785228683878339555129550048241674647783276041
/workspace/coverage/default/9.spi_device_tpm_sts_read.103366018120844016847730481920961931615749838675850987950467659886401110753475
/workspace/coverage/default/9.spi_device_tx_async_fifo_reset.1385199793848653221474773767536554972771340700026122026153333076847763821410
/workspace/coverage/default/9.spi_device_txrx.59514284370368149539794689709550869562433102619296688438537733320921154201282
/workspace/coverage/default/9.spi_device_upload.110178430829078851697752425464032338696768312872264407702475007085143628609198

---

Total test records in report: 1760

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T36	/workspace/coverage/cover_reg_top/42.spi_device_intr_test.101165969677814654800782515585059569200110120461157843728613113038387981833111			Nov 22 01:19:55 PM PST 23	Nov 22 01:20:00 PM PST 23	22136495 ps
T54	/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.65954128909289717962492376237752505909388005223221824343241599788703040562542			Nov 22 01:19:36 PM PST 23	Nov 22 01:20:06 PM PST 23	2385403303 ps
T57	/workspace/coverage/cover_reg_top/0.spi_device_intr_test.104618610112214422133355289378380836656499539412191601483900894698470750333621			Nov 22 01:19:32 PM PST 23	Nov 22 01:19:37 PM PST 23	22136495 ps
T58	/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.356729444426646419986685492904507295989530964952708142207214858992686472027			Nov 22 01:19:26 PM PST 23	Nov 22 01:19:29 PM PST 23	53154104 ps
T59	/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.31554851779770835664709253363181136811584174518010755426149494749873942604957			Nov 22 01:19:33 PM PST 23	Nov 22 01:19:39 PM PST 23	109760794 ps
T60	/workspace/coverage/cover_reg_top/13.spi_device_intr_test.25208873996007370067827772851131174251238781345155995489217740200054467744280			Nov 22 01:19:37 PM PST 23	Nov 22 01:19:44 PM PST 23	22136495 ps
T1	/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.41936003207591091798099904750501342370943386117043112893340855667137500816777			Nov 22 01:19:47 PM PST 23	Nov 22 01:20:06 PM PST 23	942254134 ps
T11	/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.25847842305201215395067555721015437610551065521907126904510911876538261716843			Nov 22 01:19:28 PM PST 23	Nov 22 01:19:32 PM PST 23	109760794 ps
T12	/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.104545779228937455477666656345288733788399623721327355428743462313520820201043			Nov 22 01:19:32 PM PST 23	Nov 22 01:19:39 PM PST 23	214206387 ps
T13	/workspace/coverage/cover_reg_top/26.spi_device_intr_test.39783396393061474795881870454135929665645659520750850947273780197547640559423			Nov 22 01:19:37 PM PST 23	Nov 22 01:19:43 PM PST 23	22136495 ps
T14	/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.110205198515752082319879086765432498622331294189470001860671097827185044577106			Nov 22 01:19:07 PM PST 23	Nov 22 01:19:20 PM PST 23	792201763 ps
T15	/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.26591066936258500164536786830045957316369083235215273726849322819878915917772			Nov 22 01:19:42 PM PST 23	Nov 22 01:19:53 PM PST 23	242795444 ps
T16	/workspace/coverage/cover_reg_top/33.spi_device_intr_test.7857360290627112917739199570416011554877153657675287704924093151855382956346			Nov 22 01:19:31 PM PST 23	Nov 22 01:19:35 PM PST 23	22136495 ps
T17	/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.95638137819186236774490369072294862667858409369965022218317768804830923533728			Nov 22 01:19:08 PM PST 23	Nov 22 01:19:15 PM PST 23	214206387 ps
T2	/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.10668466422549898539374226145071506156071874984733250471342504520178709310485			Nov 22 01:19:08 PM PST 23	Nov 22 01:19:25 PM PST 23	942254134 ps
T3	/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1811876395559859262224254284329964751321107927117934333864822453690080341394			Nov 22 01:19:10 PM PST 23	Nov 22 01:19:27 PM PST 23	942254134 ps
T97	/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.41351933693184731943472373454985982948263118702303408818054477499437685634575			Nov 22 01:19:03 PM PST 23	Nov 22 01:19:33 PM PST 23	2385403303 ps
T98	/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2709745731687254369542380353189353644103393495412644131445716175128792755732			Nov 22 01:19:25 PM PST 23	Nov 22 01:19:28 PM PST 23	53421959 ps
T61	/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.56024758490229467699753786795611197551399848711008011543582333030885190860312			Nov 22 01:19:47 PM PST 23	Nov 22 01:19:54 PM PST 23	53154104 ps
T99	/workspace/coverage/cover_reg_top/23.spi_device_intr_test.76512124564243154300486350594975964677563116473193894498663577011007884581053			Nov 22 01:19:20 PM PST 23	Nov 22 01:19:23 PM PST 23	22136495 ps
T4	/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.49299921667191459744612442419680056513925078942764442609177090036240086840739			Nov 22 01:19:47 PM PST 23	Nov 22 01:20:05 PM PST 23	942254134 ps
T183	/workspace/coverage/cover_reg_top/30.spi_device_intr_test.27420633873337770644316635202808165967343870357722122320001249464046672731957			Nov 22 01:19:27 PM PST 23	Nov 22 01:19:30 PM PST 23	22136495 ps
T103	/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.63553340939405164670859921034434553250560884134081053048125815601705834436464			Nov 22 01:19:33 PM PST 23	Nov 22 01:19:40 PM PST 23	214206387 ps
T5	/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.67897978383399150438114356039950275516051026276868321171446337272803026350235			Nov 22 01:20:25 PM PST 23	Nov 22 01:20:33 PM PST 23	235634787 ps
T90	/workspace/coverage/cover_reg_top/38.spi_device_intr_test.88767051522180164568305428525363652331676428856354188675055958223339801103980			Nov 22 01:19:34 PM PST 23	Nov 22 01:19:40 PM PST 23	22136495 ps
T62	/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.49015422956242048357213347967558245537068823840850403546576615560826655027685			Nov 22 01:19:32 PM PST 23	Nov 22 01:19:38 PM PST 23	53154104 ps
T91	/workspace/coverage/cover_reg_top/25.spi_device_intr_test.51797408720946993652527894561577478917818296097014928906988015234619879623238			Nov 22 01:19:23 PM PST 23	Nov 22 01:19:25 PM PST 23	22136495 ps
T92	/workspace/coverage/cover_reg_top/48.spi_device_intr_test.71090654877547980778403107666400065000386647416498956917601182590064165982245			Nov 22 01:19:43 PM PST 23	Nov 22 01:19:50 PM PST 23	22136495 ps
T93	/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.67766667739909106041295396563536500741984797448834854829126560161138274243425			Nov 22 01:19:54 PM PST 23	Nov 22 01:20:00 PM PST 23	109760794 ps
T94	/workspace/coverage/cover_reg_top/21.spi_device_intr_test.44769943559921209259450955900555129447744971348116263722553110442640452691252			Nov 22 01:19:33 PM PST 23	Nov 22 01:19:37 PM PST 23	22136495 ps
T63	/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.64996065428083744670621027215234710393507848266933110168522809792860693201104			Nov 22 01:19:38 PM PST 23	Nov 22 01:19:54 PM PST 23	792201763 ps
T95	/workspace/coverage/cover_reg_top/34.spi_device_intr_test.48391542478389938122720287148554443147413354157576000175966391799868068656531			Nov 22 01:19:29 PM PST 23	Nov 22 01:19:33 PM PST 23	22136495 ps
T96	/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.32851738091733796507088579129097328017563557841788141802183327809529779112025			Nov 22 01:19:29 PM PST 23	Nov 22 01:19:34 PM PST 23	109760794 ps
T6	/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.105406467241947493288444037285872237290968440023856870686676303714402927224791			Nov 22 01:20:25 PM PST 23	Nov 22 01:20:43 PM PST 23	942254134 ps
T184	/workspace/coverage/cover_reg_top/14.spi_device_intr_test.26257541633618103787655803727355045669667838863325252562094714349969658941432			Nov 22 01:19:41 PM PST 23	Nov 22 01:19:48 PM PST 23	22136495 ps
T104	/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.91853896360296962832474489154932354151216997136213370360230465660071724930347			Nov 22 01:19:30 PM PST 23	Nov 22 01:19:38 PM PST 23	214206387 ps
T7	/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.107850812819909599971165310829161125981864865600670834012415943340081573136408			Nov 22 01:19:32 PM PST 23	Nov 22 01:19:49 PM PST 23	942254134 ps
T185	/workspace/coverage/cover_reg_top/5.spi_device_intr_test.107240792542805675324702209335495493669377428152328364503586405858408310299439			Nov 22 01:19:41 PM PST 23	Nov 22 01:19:48 PM PST 23	22136495 ps
T186	/workspace/coverage/cover_reg_top/47.spi_device_intr_test.13653143884953609751491003189847214699956217035909731556371470801686194587708			Nov 22 01:19:34 PM PST 23	Nov 22 01:19:38 PM PST 23	22136495 ps
T8	/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.71027675017620676224188501794701658905143570063786802166006485162578988381170			Nov 22 01:19:13 PM PST 23	Nov 22 01:19:19 PM PST 23	235634787 ps
T9	/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.93190563620619633998214385438171802698583321867758792138458506088826361429699			Nov 22 01:19:26 PM PST 23	Nov 22 01:19:41 PM PST 23	942254134 ps
T64	/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.69615829648555403138055469659645528061691210614893912704141865605835056612784			Nov 22 01:19:28 PM PST 23	Nov 22 01:19:35 PM PST 23	242795444 ps
T187	/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.13391928838357030275791710287501118531278129146033383083427535818941099618716			Nov 22 01:19:30 PM PST 23	Nov 22 01:19:51 PM PST 23	1308269063 ps
T65	/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.110872458587802419362718334799057807501262199830062266353475840649199389076798			Nov 22 01:19:06 PM PST 23	Nov 22 01:19:19 PM PST 23	792201763 ps
T188	/workspace/coverage/cover_reg_top/35.spi_device_intr_test.50265362399272108260280008562844033220091903692365400514189374423277492391053			Nov 22 01:19:33 PM PST 23	Nov 22 01:19:38 PM PST 23	22136495 ps
T117	/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.48710512880593258315691593713780375377471396026222487069580989087974805253375			Nov 22 01:19:40 PM PST 23	Nov 22 01:19:47 PM PST 23	53421959 ps
T189	/workspace/coverage/cover_reg_top/8.spi_device_intr_test.7984288453462926368592319919489302749877983874497560009904958031470110899550			Nov 22 01:19:46 PM PST 23	Nov 22 01:19:52 PM PST 23	22136495 ps
T190	/workspace/coverage/cover_reg_top/22.spi_device_intr_test.24156848077045415343126148827951878920381557463218920090425168782221856516247			Nov 22 01:19:31 PM PST 23	Nov 22 01:19:36 PM PST 23	22136495 ps
T105	/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.16691600111424299517308867929528809912258131591767487019407084087217705306272			Nov 22 01:19:29 PM PST 23	Nov 22 01:19:33 PM PST 23	109760794 ps
T191	/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.35174745158335887223297782250918519492117386858497710138084576645290149417279			Nov 22 01:19:15 PM PST 23	Nov 22 01:19:19 PM PST 23	53154104 ps
T192	/workspace/coverage/cover_reg_top/28.spi_device_intr_test.107755637161932790382425289048292147813938440278683131241099437388501755025376			Nov 22 01:19:21 PM PST 23	Nov 22 01:19:23 PM PST 23	22136495 ps
T193	/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.114425809301934752406208413293377312547092812294358365584955298799835653719923			Nov 22 01:19:03 PM PST 23	Nov 22 01:19:23 PM PST 23	1308269063 ps
T10	/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.93212788652307950562514497913265491501654293582712334604377471502543346262765			Nov 22 01:19:28 PM PST 23	Nov 22 01:19:44 PM PST 23	942254134 ps
T194	/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.24287278191317975269953520788505711604662573909447638402576010133967925858194			Nov 22 01:19:39 PM PST 23	Nov 22 01:19:47 PM PST 23	53154104 ps
T82	/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.9868361740917363722556081293189577170905394644254646049094453253608321573963			Nov 22 01:19:30 PM PST 23	Nov 22 01:19:36 PM PST 23	235634787 ps
T195	/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.100510208289239709750846574242291676156778724165957227507407379195313178988820			Nov 22 01:19:47 PM PST 23	Nov 22 01:20:06 PM PST 23	942254134 ps
T83	/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.55114703945186876120524953519424334675310408903622738478267066520017291078784			Nov 22 01:19:24 PM PST 23	Nov 22 01:19:29 PM PST 23	235634787 ps
T84	/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.78367750723225823786975894641436891462313024480549887866146376815647855309650			Nov 22 01:19:31 PM PST 23	Nov 22 01:19:39 PM PST 23	235634787 ps
T100	/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.84841158105251214174956237953889221543996399794271149394914559951663253102239			Nov 22 01:19:41 PM PST 23	Nov 22 01:19:52 PM PST 23	242795444 ps
T196	/workspace/coverage/cover_reg_top/43.spi_device_intr_test.81281737104326229028438197982779633651635566064726386391447972601499676754318			Nov 22 01:19:43 PM PST 23	Nov 22 01:19:50 PM PST 23	22136495 ps
T106	/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.89025962076860686554115450855996181451100398749115222986070010605545742565283			Nov 22 01:19:07 PM PST 23	Nov 22 01:19:14 PM PST 23	214206387 ps
T197	/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.13272886015245552375126939188388657887572373440812883660925562530923169762627			Nov 22 01:19:04 PM PST 23	Nov 22 01:19:09 PM PST 23	109760794 ps
T85	/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.114326582917040542916033496315994450413666641013795389960927439864290601250905			Nov 22 01:19:29 PM PST 23	Nov 22 01:19:36 PM PST 23	235634787 ps
T198	/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.29668846460135223617200013422607161553130638479041461297324125964856566413545			Nov 22 01:19:37 PM PST 23	Nov 22 01:19:46 PM PST 23	214206387 ps
T199	/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.57158620848908450897719575497150317448616441703052064787880101763807066414047			Nov 22 01:19:27 PM PST 23	Nov 22 01:19:43 PM PST 23	942254134 ps
T200	/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.93264559443398511909556151818341864287262654332783307937954803353972376877030			Nov 22 01:19:40 PM PST 23	Nov 22 01:20:00 PM PST 23	942254134 ps
T201	/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.27590269859674216244998337085775142306638864029908691393890748622354260677298			Nov 22 01:19:31 PM PST 23	Nov 22 01:19:48 PM PST 23	942254134 ps
T202	/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.64865449542397038191742225199917698794952153427010011054167813839130692592217			Nov 22 01:19:43 PM PST 23	Nov 22 01:19:51 PM PST 23	109760794 ps
T203	/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.33991077735933970989928831485455878848969705844252670142652415514028864333023			Nov 22 01:19:34 PM PST 23	Nov 22 01:19:41 PM PST 23	214206387 ps
T204	/workspace/coverage/cover_reg_top/36.spi_device_intr_test.56437620619180762638450651752923107319820752628386622280590265922482902844415			Nov 22 01:19:31 PM PST 23	Nov 22 01:19:36 PM PST 23	22136495 ps
T205	/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.52034255848408807502044164475493086023417048578413091927863638746304581018930			Nov 22 01:19:33 PM PST 23	Nov 22 01:19:40 PM PST 23	214206387 ps
T206	/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.17830570951752079113949228739685082381062537531023715718186291964662544315602			Nov 22 01:19:33 PM PST 23	Nov 22 01:19:40 PM PST 23	214206387 ps
T207	/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.82188963063138211497106906490457503707330839740108246761333063181957640063437			Nov 22 01:19:09 PM PST 23	Nov 22 01:19:22 PM PST 23	792201763 ps
T86	/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.38128453018953123520214788546294983243104387086656507665017755532833363853416			Nov 22 01:19:43 PM PST 23	Nov 22 01:19:53 PM PST 23	235634787 ps
T208	/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.60036625868627035962025303202613653610873133244088085820655274601188895310571			Nov 22 01:19:28 PM PST 23	Nov 22 01:19:34 PM PST 23	214206387 ps
T209	/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.60600825835773358545468989888193426244566396365113522921425460126662564168557			Nov 22 01:19:04 PM PST 23	Nov 22 01:19:11 PM PST 23	214206387 ps
T210	/workspace/coverage/cover_reg_top/31.spi_device_intr_test.56736679135113378432720804514294900017897241539965493137887949173393174223731			Nov 22 01:19:43 PM PST 23	Nov 22 01:19:50 PM PST 23	22136495 ps
T211	/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.58163407205863188089935971681337940758693226579126744713786117411241215496637			Nov 22 01:19:39 PM PST 23	Nov 22 01:19:49 PM PST 23	214206387 ps
T118	/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.10733402436015032696445056541693076427279799495677376312919995263703911483198			Nov 22 01:19:31 PM PST 23	Nov 22 01:19:35 PM PST 23	53421959 ps
T212	/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.55223591363322954782533100666714968932920248965849254648441649525684398920978			Nov 22 01:19:15 PM PST 23	Nov 22 01:19:19 PM PST 23	53154104 ps
T213	/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.37187410455266229691789802058795304299552583192296442995104564990910931351800			Nov 22 01:19:24 PM PST 23	Nov 22 01:19:51 PM PST 23	2385403303 ps
T214	/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.94389342077882605109596638090314611860767368968933986199974675958453601918677			Nov 22 01:19:39 PM PST 23	Nov 22 01:19:47 PM PST 23	53154104 ps
T215	/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.65467508378558427718422271672205632951828899179630451132926477879528982500331			Nov 22 01:19:34 PM PST 23	Nov 22 01:19:40 PM PST 23	109760794 ps
T216	/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.77813885718982318598831659703891662756967183938457338807050582800143403896886			Nov 22 01:19:03 PM PST 23	Nov 22 01:19:10 PM PST 23	214206387 ps
T217	/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.29876703719270469252407796104654099578086765660639479447630582214354873189659			Nov 22 01:20:26 PM PST 23	Nov 22 01:20:40 PM PST 23	792201763 ps
T218	/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.64071177430913791381727691652557695794343016468330126062775479537897182746487			Nov 22 01:19:27 PM PST 23	Nov 22 01:19:30 PM PST 23	109760794 ps
T219	/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.63558489170691371297816609297542932075861736101895222407485412493990846524905			Nov 22 01:19:41 PM PST 23	Nov 22 01:19:49 PM PST 23	53154104 ps
T220	/workspace/coverage/cover_reg_top/10.spi_device_intr_test.7729065829898248417111213362530180017303811246092469566991423647003634623555			Nov 22 01:19:06 PM PST 23	Nov 22 01:19:11 PM PST 23	22136495 ps
T221	/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.30340844348162019920270497659373224357551528411296504072389809280221777150671			Nov 22 01:19:27 PM PST 23	Nov 22 01:19:32 PM PST 23	214206387 ps
T222	/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.15153253735602053611613806217197529212745107611614102996621302658098196056231			Nov 22 01:19:21 PM PST 23	Nov 22 01:19:25 PM PST 23	214206387 ps
T223	/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.90971211343230039674128993052687224933451255701474945275003287168150981585662			Nov 22 01:19:29 PM PST 23	Nov 22 01:19:33 PM PST 23	53421959 ps
T224	/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.57067282700237920057583428910373007662197665194402340329974289059107884132121			Nov 22 01:19:16 PM PST 23	Nov 22 01:19:32 PM PST 23	942254134 ps
T225	/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.65300507096102456546106513507240980602779726265710547132808034477691939017626			Nov 22 01:19:12 PM PST 23	Nov 22 01:19:15 PM PST 23	53421959 ps
T226	/workspace/coverage/cover_reg_top/45.spi_device_intr_test.29194628412230819728245692388447242267619693559073172518556743527807571274130			Nov 22 01:19:43 PM PST 23	Nov 22 01:19:50 PM PST 23	22136495 ps
T227	/workspace/coverage/cover_reg_top/46.spi_device_intr_test.67307149616364205853290685311870753338551978416187400739314043230680748853294			Nov 22 01:19:46 PM PST 23	Nov 22 01:19:52 PM PST 23	22136495 ps
T228	/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.62920779274939540248722009133142137069552772500670584179813134791550624095084			Nov 22 01:19:34 PM PST 23	Nov 22 01:19:41 PM PST 23	53154104 ps
T87	/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.23702240456313226940805984327130859309954639426539741609479055166972417354202			Nov 22 01:19:41 PM PST 23	Nov 22 01:19:51 PM PST 23	235634787 ps
T229	/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.103000627594776357955283106737622466132653304634132733506334430577147418718567			Nov 22 01:19:14 PM PST 23	Nov 22 01:19:18 PM PST 23	53154104 ps
T230	/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.53385872938607386180075889254326486657841476999776623227085304749618218098723			Nov 22 01:19:05 PM PST 23	Nov 22 01:19:12 PM PST 23	214206387 ps
T231	/workspace/coverage/cover_reg_top/29.spi_device_intr_test.88420557827897920995990828314703856735351557701855189079053254148820384335951			Nov 22 01:19:34 PM PST 23	Nov 22 01:19:38 PM PST 23	22136495 ps
T232	/workspace/coverage/cover_reg_top/18.spi_device_intr_test.36588098570075236196841315935085337936972069626822418736003789850684714777321			Nov 22 01:19:33 PM PST 23	Nov 22 01:19:38 PM PST 23	22136495 ps
T233	/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.22059560749127409350644251586812685396225640638214385879500898467392437637789			Nov 22 01:19:33 PM PST 23	Nov 22 01:19:39 PM PST 23	53154104 ps
T234	/workspace/coverage/cover_reg_top/24.spi_device_intr_test.40379979794240239247180519016630638736358887639947866306114297349138562548270			Nov 22 01:19:28 PM PST 23	Nov 22 01:19:31 PM PST 23	22136495 ps
T88	/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.77996998090599118596038918244394642879864951211053241116160287743776561452578			Nov 22 01:19:13 PM PST 23	Nov 22 01:19:19 PM PST 23	235634787 ps
T235	/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.109747694041649347679895077251587542770920060638946781085249462468930376255704			Nov 22 01:19:07 PM PST 23	Nov 22 01:19:25 PM PST 23	942254134 ps
T236	/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.29215526748670506367920223279382841421844520824036703679719082747989070851018			Nov 22 01:19:37 PM PST 23	Nov 22 01:19:45 PM PST 23	109760794 ps
T237	/workspace/coverage/cover_reg_top/16.spi_device_intr_test.87459150004883078169231426513300455131183265404993323317066764396041177543647			Nov 22 01:19:22 PM PST 23	Nov 22 01:19:24 PM PST 23	22136495 ps
T238	/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.56223070560744581625738666556551911345081549652150056509339730745990688239420			Nov 22 01:19:34 PM PST 23	Nov 22 01:19:41 PM PST 23	109760794 ps
T239	/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.93549336582054078616157620566906227344793484408618556903949027892404902630114			Nov 22 01:19:27 PM PST 23	Nov 22 01:19:43 PM PST 23	942254134 ps
T240	/workspace/coverage/cover_reg_top/4.spi_device_intr_test.428429932875015303328436443738298390625698245751786246892605549375857649437			Nov 22 01:19:05 PM PST 23	Nov 22 01:19:10 PM PST 23	22136495 ps
T241	/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.26848500328358584443972078016223838497459326165542202746911310105183887943676			Nov 22 01:19:42 PM PST 23	Nov 22 01:19:50 PM PST 23	109760794 ps
T242	/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.15446568255687948592058104237411585454582473441759551765738046209796890990536			Nov 22 01:19:07 PM PST 23	Nov 22 01:19:13 PM PST 23	109760794 ps
T243	/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.112668189864520136189772436270460231232859480477687347567809501965058059990632			Nov 22 01:19:42 PM PST 23	Nov 22 01:19:50 PM PST 23	53154104 ps
T244	/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.77262486508128143072297797372031648400312371228635704415283249152741643040364			Nov 22 01:20:28 PM PST 23	Nov 22 01:20:50 PM PST 23	1308269063 ps
T245	/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.45014504283230440170837956924642112905550760934837563242649344841813520358530			Nov 22 01:19:28 PM PST 23	Nov 22 01:19:33 PM PST 23	53154104 ps
T246	/workspace/coverage/cover_reg_top/7.spi_device_intr_test.48170169600198450889326937798718619198723707022283321691705602313156885224238			Nov 22 01:19:34 PM PST 23	Nov 22 01:19:38 PM PST 23	22136495 ps
T247	/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.59643638243443201344132721301587203942978470648801148721050464869489230408981			Nov 22 01:19:26 PM PST 23	Nov 22 01:19:29 PM PST 23	53154104 ps
T248	/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.89586691362269584272645555119935846556265471039485136431684011941951009712191			Nov 22 01:19:32 PM PST 23	Nov 22 01:19:38 PM PST 23	53154104 ps
T89	/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.34140359908293714346901021040546954949464747644055768416591128656399164234590			Nov 22 01:19:03 PM PST 23	Nov 22 01:19:09 PM PST 23	235634787 ps
T249	/workspace/coverage/cover_reg_top/2.spi_device_intr_test.33269736442538017152935500174013923147588388941907194257442294779122784441298			Nov 22 01:19:51 PM PST 23	Nov 22 01:19:56 PM PST 23	22136495 ps
T250	/workspace/coverage/cover_reg_top/40.spi_device_intr_test.21345770666971843125459032878971653543239711077013044519194322529130405452696			Nov 22 01:19:21 PM PST 23	Nov 22 01:19:23 PM PST 23	22136495 ps
T251	/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.109698912951638018438839231338838892882990911203596724766457797139263684784971			Nov 22 01:19:29 PM PST 23	Nov 22 01:19:35 PM PST 23	235634787 ps
T252	/workspace/coverage/cover_reg_top/19.spi_device_intr_test.31901923137455142602047851389751693867274330019999379782230575107409695632327			Nov 22 01:19:35 PM PST 23	Nov 22 01:19:41 PM PST 23	22136495 ps
T253	/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.10813931705648497902763313777398437157768518036826392925015298853036527372588			Nov 22 01:19:30 PM PST 23	Nov 22 01:19:38 PM PST 23	235634787 ps
T254	/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.40118900138057514735388956569673442816994016109510147737166160023591843316499			Nov 22 01:19:29 PM PST 23	Nov 22 01:19:35 PM PST 23	235634787 ps
T255	/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.8354144736708699317307767707562006477954563277119218870636039883079906304091			Nov 22 01:19:40 PM PST 23	Nov 22 01:19:49 PM PST 23	53154104 ps
T256	/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.110702215233532141836372916320651122493454031743420867398353403909532002647754			Nov 22 01:20:26 PM PST 23	Nov 22 01:20:33 PM PST 23	109760794 ps
T257	/workspace/coverage/cover_reg_top/3.spi_device_intr_test.82647892794212962567694532834325967290841022244644836290850603918284048208238			Nov 22 01:19:03 PM PST 23	Nov 22 01:19:07 PM PST 23	22136495 ps
T258	/workspace/coverage/cover_reg_top/49.spi_device_intr_test.100996602224804386592519247573397910930402942342380513354432504533917661833936			Nov 22 01:19:45 PM PST 23	Nov 22 01:19:51 PM PST 23	22136495 ps
T101	/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.72875233225308204832647646728407419033247325107721327330109486479965966768698			Nov 22 01:19:04 PM PST 23	Nov 22 01:19:13 PM PST 23	242795444 ps
T259	/workspace/coverage/cover_reg_top/44.spi_device_intr_test.83778537379404622506479498730985542604463813949572119002827263157091890087456			Nov 22 01:19:41 PM PST 23	Nov 22 01:19:48 PM PST 23	22136495 ps
T260	/workspace/coverage/cover_reg_top/32.spi_device_intr_test.71455012104184792889781995666649472912619654672403078730003423798887911971167			Nov 22 01:19:36 PM PST 23	Nov 22 01:19:42 PM PST 23	22136495 ps
T261	/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.5941843801508977873130200557889037670349461207982760011840728874262616726385			Nov 22 01:19:36 PM PST 23	Nov 22 01:19:44 PM PST 23	109760794 ps
T262	/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.94940383936668008118760367905361426385684046209383854926985424525007133843817			Nov 22 01:19:13 PM PST 23	Nov 22 01:19:17 PM PST 23	109760794 ps
T263	/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.50700112433744707605529699039062072765343177394896880753216650932932358752608			Nov 22 01:20:26 PM PST 23	Nov 22 01:20:34 PM PST 23	214206387 ps
T264	/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.111141378901603832950807858638391686643971946858732655669495603103308843707001			Nov 22 01:19:41 PM PST 23	Nov 22 01:19:51 PM PST 23	214206387 ps
T265	/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.68672309154910559923231520205216984950975578035086120340230884696689948244428			Nov 22 01:19:41 PM PST 23	Nov 22 01:19:51 PM PST 23	235634787 ps
T266	/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.19959619806299378475593387912768638532345746371585957978730402187064245821435			Nov 22 01:19:16 PM PST 23	Nov 22 01:19:43 PM PST 23	2385403303 ps
T267	/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.83021145595592541882806424472488107238131684130742590312085243381266397713248			Nov 22 01:19:15 PM PST 23	Nov 22 01:19:21 PM PST 23	235634787 ps
T268	/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.60265630276690422418394536673225708996111201731401577062248730275228607038972			Nov 22 01:19:05 PM PST 23	Nov 22 01:19:11 PM PST 23	109760794 ps
T269	/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.31691173293474391802363964561235814284902742130262725645309678686208402509154			Nov 22 01:19:25 PM PST 23	Nov 22 01:19:30 PM PST 23	214206387 ps
T270	/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.24367703314687908051491795501060035923955281677779166306725838286490422843680			Nov 22 01:19:33 PM PST 23	Nov 22 01:19:52 PM PST 23	942254134 ps
T271	/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.76703513523730952650824434611032637955862889591038018363210939256837974576022			Nov 22 01:19:34 PM PST 23	Nov 22 01:19:41 PM PST 23	109760794 ps
T272	/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.67227538339000538856060033962220410117635072000800032768180532104013359128982			Nov 22 01:19:30 PM PST 23	Nov 22 01:19:36 PM PST 23	53154104 ps
T273	/workspace/coverage/cover_reg_top/27.spi_device_intr_test.26608179258898586959572980234831491796725500128130542262906063595927054016634			Nov 22 01:19:24 PM PST 23	Nov 22 01:19:26 PM PST 23	22136495 ps
T274	/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.115626268264293841060772614484659289576077082556578975918208784758117681955208			Nov 22 01:19:37 PM PST 23	Nov 22 01:19:57 PM PST 23	942254134 ps
T275	/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.38308064984967644815454085626546348951438678605300627307473009298575760651873			Nov 22 01:19:36 PM PST 23	Nov 22 01:19:56 PM PST 23	942254134 ps
T276	/workspace/coverage/cover_reg_top/15.spi_device_intr_test.39263626404935919401903513234817944314516058869607171300460843474308074768446			Nov 22 01:19:33 PM PST 23	Nov 22 01:19:38 PM PST 23	22136495 ps
T277	/workspace/coverage/cover_reg_top/20.spi_device_intr_test.79648438488058694102405866842187093000475050093441136461181162739111489084327			Nov 22 01:19:29 PM PST 23	Nov 22 01:19:33 PM PST 23	22136495 ps
T278	/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.42953907046508137673710841428194445082154961666442650067134812681882052629157			Nov 22 01:19:35 PM PST 23	Nov 22 01:19:45 PM PST 23	235634787 ps
T279	/workspace/coverage/cover_reg_top/12.spi_device_intr_test.109526442598807181895384222518222944874286543060336942139279544822981745461288			Nov 22 01:19:35 PM PST 23	Nov 22 01:19:40 PM PST 23	22136495 ps
T280	/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.92860277257340562548047959600733772952621852451980619636857250348307119640413			Nov 22 01:19:27 PM PST 23	Nov 22 01:19:43 PM PST 23	942254134 ps
T281	/workspace/coverage/cover_reg_top/11.spi_device_intr_test.65139810083786030448090142042476491956931867190146724297927136326227427448735			Nov 22 01:19:14 PM PST 23	Nov 22 01:19:16 PM PST 23	22136495 ps
T282	/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.55220408591425673825329883070357023620359695881755755887925310437809078649268			Nov 22 01:19:50 PM PST 23	Nov 22 01:19:57 PM PST 23	214206387 ps
T102	/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.102670359304483021420309611618736667880646880148805431628980662363882116424518			Nov 22 01:19:13 PM PST 23	Nov 22 01:19:20 PM PST 23	242795444 ps
T283	/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.43458886114065712722048291599232128002399483901534456017063823133949163072			Nov 22 01:19:29 PM PST 23	Nov 22 01:19:50 PM PST 23	1308269063 ps
T284	/workspace/coverage/cover_reg_top/9.spi_device_intr_test.70782490287529487741158807937553174515446433713572478279178028698347576247467			Nov 22 01:19:04 PM PST 23	Nov 22 01:19:08 PM PST 23	22136495 ps
T285	/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.97698376727838028392978883567731333346933619968292468260624307168981828741844			Nov 22 01:19:30 PM PST 23	Nov 22 01:19:36 PM PST 23	109760794 ps
T286	/workspace/coverage/cover_reg_top/6.spi_device_intr_test.8653988834113336686740740043348526911644208622743899005050097583466222064766			Nov 22 01:19:42 PM PST 23	Nov 22 01:19:49 PM PST 23	22136495 ps
T287	/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.23919980885273921734545701954411529652931939543811409654460700378629765183991			Nov 22 01:19:30 PM PST 23	Nov 22 01:19:35 PM PST 23	53154104 ps
T18	/workspace/coverage/default/34.spi_device_smoke.61591620924796338166529384142371178232441613466232000663474903775868808700542			Nov 22 02:53:33 PM PST 23	Nov 22 02:53:35 PM PST 23	37422087 ps
T19	/workspace/coverage/default/5.spi_device_mem_parity.114488629251841480294740903886846247914658332129873205014615762261199620898740			Nov 22 02:48:51 PM PST 23	Nov 22 02:48:53 PM PST 23	40064923 ps
T20	/workspace/coverage/default/14.spi_device_fifo_underflow_overflow.54921330888783164607577274406476614155179443801996475763408083915596860807169			Nov 22 02:50:06 PM PST 23	Nov 22 02:54:21 PM PST 23	39286733090 ps
T24	/workspace/coverage/default/46.spi_device_dummy_item_extra_dly.100687938447258559459454735879402273429211285907753544150696626438801348486957			Nov 22 02:55:34 PM PST 23	Nov 22 02:59:37 PM PST 23	52275022040 ps
T27	/workspace/coverage/default/18.spi_device_fifo_full.2931073879470094138678080648679599361336575897859436543560774615680634797830			Nov 22 02:51:13 PM PST 23	Nov 22 03:04:02 PM PST 23	69486455776 ps
T50	/workspace/coverage/default/11.spi_device_abort.1943025359533907669775249437624103207796778732468802364786295869472521805183			Nov 22 02:49:47 PM PST 23	Nov 22 02:49:48 PM PST 23	21440072 ps
T28	/workspace/coverage/default/20.spi_device_fifo_full.25667548451819963922709975211023026422580367370428885666948025561231693847444			Nov 22 02:51:03 PM PST 23	Nov 22 03:03:54 PM PST 23	69486455776 ps
T31	/workspace/coverage/default/11.spi_device_tpm_all.31641826720742955947647429715623796828897018260121434931539424864757494430846			Nov 22 02:49:45 PM PST 23	Nov 22 02:50:51 PM PST 23	14078327616 ps
T21	/workspace/coverage/default/22.spi_device_flash_all.76553753937021290167755817695430105719036708791989432525331269666745491536780			Nov 22 02:52:08 PM PST 23	Nov 22 02:56:37 PM PST 23	85193115836 ps
T29	/workspace/coverage/default/32.spi_device_bit_transfer.5644163151176368457417204375199437071362024260903116155983222629375058059517			Nov 22 02:53:21 PM PST 23	Nov 22 02:53:25 PM PST 23	399472762 ps
T25	/workspace/coverage/default/4.spi_device_read_buffer_direct.93218150429260135679739167716251971477957327596475706526822320926811627935178			Nov 22 02:48:44 PM PST 23	Nov 22 02:48:49 PM PST 23	293866464 ps
T30	/workspace/coverage/default/13.spi_device_txrx.45119997856364757122562335896744098680869173243559591272518681729363064829730			Nov 22 02:49:47 PM PST 23	Nov 22 02:54:30 PM PST 23	45776109746 ps
T26	/workspace/coverage/default/3.spi_device_flash_mode.106893959945057611637377373334001243038447966657819016305272476248049579188717			Nov 22 02:48:34 PM PST 23	Nov 22 02:48:43 PM PST 23	1087056547 ps
T81	/workspace/coverage/default/21.spi_device_csb_read.84314228883366659471837739100713917368866696181446358384181532991171492418786			Nov 22 02:51:20 PM PST 23	Nov 22 02:51:26 PM PST 23	29082868 ps
T22	/workspace/coverage/default/37.spi_device_stress_all.87204300542036997945253576403153662308538775897360540897471021326188571770063			Nov 22 02:54:21 PM PST 23	Nov 22 03:05:23 PM PST 23	117642945521 ps
T55	/workspace/coverage/default/39.spi_device_abort.19000774857279316218690962431899426826011277901575456517955566487367758458188			Nov 22 02:54:32 PM PST 23	Nov 22 02:54:38 PM PST 23	21440072 ps
T47	/workspace/coverage/default/25.spi_device_intr.112283333037077679706759459564614669897507234117964808169722227750898153167367			Nov 22 02:51:51 PM PST 23	Nov 22 02:52:24 PM PST 23	9117581588 ps
T48	/workspace/coverage/default/24.spi_device_bit_transfer.86448545595863882098712976173084638421165646782234800400718288150618080012155			Nov 22 02:51:52 PM PST 23	Nov 22 02:51:56 PM PST 23	399472762 ps
T49	/workspace/coverage/default/3.spi_device_extreme_fifo_size.23233812618810249926792630178357849077814619218501597049508831383514890638490			Nov 22 02:48:32 PM PST 23	Nov 22 03:02:35 PM PST 23	113592817208 ps
T32	/workspace/coverage/default/0.spi_device_intercept.55960093424964298814754624847823848391423038321093634807786103557107029709931			Nov 22 02:47:51 PM PST 23	Nov 22 02:48:02 PM PST 23	3388073853 ps
T113	/workspace/coverage/default/24.spi_device_dummy_item_extra_dly.112814679642506872473296620378768178318837867766506130381225111298834314510564			Nov 22 02:52:22 PM PST 23	Nov 22 02:56:21 PM PST 23	52275022040 ps
T150	/workspace/coverage/default/8.spi_device_mailbox.112520391114191901091196284924274552773010557843675414450375099229022592469799			Nov 22 02:49:30 PM PST 23	Nov 22 02:50:19 PM PST 23	22218066069 ps
T51	/workspace/coverage/default/4.spi_device_tpm_all.21398891993249536844418581211656404734225825408665058353173064512909881545406			Nov 22 02:48:37 PM PST 23	Nov 22 02:49:44 PM PST 23	14078327616 ps
T147	/workspace/coverage/default/29.spi_device_rx_timeout.33389617299246957489264897221074633784119088766121875952665792586614753618011			Nov 22 02:52:44 PM PST 23	Nov 22 02:52:51 PM PST 23	1221948325 ps
T23	/workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.108328025936217573377299478321734483321103940430129025420183953742611253273546			Nov 22 02:50:56 PM PST 23	Nov 22 02:57:20 PM PST 23	97013306988 ps
T52	/workspace/coverage/default/26.spi_device_flash_mode.78427260090023285820057192513738042732057212121751930507417741292847889605017			Nov 22 02:52:09 PM PST 23	Nov 22 02:52:19 PM PST 23	1087056547 ps
T34	/workspace/coverage/default/19.spi_device_upload.25760255369837056530801485709815182166249641891556481591311946906854510661429			Nov 22 02:51:03 PM PST 23	Nov 22 02:51:21 PM PST 23	6582334013 ps
T146	/workspace/coverage/default/49.spi_device_byte_transfer.71888659026030244685370896575653269087054632844113812908472245782817855414690			Nov 22 02:56:36 PM PST 23	Nov 22 02:56:40 PM PST 23	272580920 ps
T110	/workspace/coverage/default/18.spi_device_rx_async_fifo_reset.101078663550490996210436170430087922557879784786953115375826113769205010551706			Nov 22 02:50:59 PM PST 23	Nov 22 02:51:01 PM PST 23	46761298 ps
T156	/workspace/coverage/default/12.spi_device_txrx.29053924079211854596280088085922403454224290291453507282671669119625458629677			Nov 22 02:50:02 PM PST 23	Nov 22 02:54:27 PM PST 23	45776109746 ps
T136	/workspace/coverage/default/19.spi_device_tpm_sts_read.665600951087772699786774234287848152104841981618426455825819185638366280170			Nov 22 02:51:02 PM PST 23	Nov 22 02:51:04 PM PST 23	154474722 ps
T163	/workspace/coverage/default/35.spi_device_extreme_fifo_size.7396196489208627152916445019653101574766961449943406003830099998288607862379			Nov 22 02:53:39 PM PST 23	Nov 22 03:07:36 PM PST 23	113592817208 ps
T137	/workspace/coverage/default/27.spi_device_tpm_rw.71367964615364770957284499575823225756946555425219843831291118927691610261381			Nov 22 02:52:30 PM PST 23	Nov 22 02:52:34 PM PST 23	334616138 ps
T138	/workspace/coverage/default/47.spi_device_tpm_rw.57126929092143023562688956918400281048466871310501623424919178449584486812856			Nov 22 02:55:50 PM PST 23	Nov 22 02:55:54 PM PST 23	334616138 ps
T148	/workspace/coverage/default/22.spi_device_rx_timeout.40980728314511017111672206272813471168102399965061105177101558862616615274075			Nov 22 02:51:29 PM PST 23	Nov 22 02:51:36 PM PST 23	1221948325 ps
T288	/workspace/coverage/default/2.spi_device_txrx.29092572475542299482098263993838628905968909092128679334095454164414042099747			Nov 22 02:47:59 PM PST 23	Nov 22 02:52:35 PM PST 23	45776109746 ps
T53	/workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.39200778016360812759380030883414828901616100229516916110672593408035234810725			Nov 22 02:55:37 PM PST 23	Nov 22 03:02:24 PM PST 23	97013306988 ps
T139	/workspace/coverage/default/40.spi_device_tpm_read_hw_reg.103989004631019631378301275114630568151219950240009758361758955279456625636740			Nov 22 02:54:33 PM PST 23	Nov 22 02:55:03 PM PST 23	12597285893 ps
T56	/workspace/coverage/default/40.spi_device_read_buffer_direct.807963052660520142742527006663405655313896066112222544990623413916144160857			Nov 22 02:54:40 PM PST 23	Nov 22 02:54:45 PM PST 23	293866464 ps
T33	/workspace/coverage/default/35.spi_device_pass_addr_payload_swap.84009523895403546706706271917325090327018873230230872780631118893711162558921			Nov 22 02:53:40 PM PST 23	Nov 22 02:54:22 PM PST 23	18486292352 ps
T107	/workspace/coverage/default/37.spi_device_tx_async_fifo_reset.27758535996927486191833117890482271596166508630411389700314714243465515043184			Nov 22 02:54:39 PM PST 23	Nov 22 02:54:41 PM PST 23	23582912 ps
T140	/workspace/coverage/default/25.spi_device_tpm_rw.97649782130791783991268816634156276538527493027433695664985649523816883751243			Nov 22 02:52:27 PM PST 23	Nov 22 02:52:31 PM PST 23	334616138 ps
T143	/workspace/coverage/default/10.spi_device_tpm_read_hw_reg.44490845027611117122189290780777481014582112787073390825565802763740713763754			Nov 22 02:50:00 PM PST 23	Nov 22 02:50:28 PM PST 23	12597285893 ps
T162	/workspace/coverage/default/29.spi_device_extreme_fifo_size.2276629521646143041510203800751762051420710605340325368768650893109964255348			Nov 22 02:52:42 PM PST 23	Nov 22 03:06:32 PM PST 23	113592817208 ps
T165	/workspace/coverage/default/21.spi_device_read_buffer_direct.40045457423909312038174689739669435056472107004319922191143839494040042155012			Nov 22 02:51:22 PM PST 23	Nov 22 02:51:30 PM PST 23	293866464 ps
T289	/workspace/coverage/default/30.spi_device_byte_transfer.40231384391587337217772442266121020082031621285828879513102060277286964024930			Nov 22 02:52:55 PM PST 23	Nov 22 02:52:59 PM PST 23	272580920 ps
T290	/workspace/coverage/default/38.spi_device_byte_transfer.46629553909841936639639481004912254419856175961832626980179625186517456841960			Nov 22 02:54:22 PM PST 23	Nov 22 02:54:33 PM PST 23	272580920 ps
T172	/workspace/coverage/default/7.spi_device_perf.88968538049474664769358980912045086731923786010452124929993536041860518138475			Nov 22 02:48:54 PM PST 23	Nov 22 02:51:15 PM PST 23	8264927695 ps
T166	/workspace/coverage/default/45.spi_device_flash_mode.99913675744960213508876073981132107589141641215627957664181072326837176116770			Nov 22 02:55:28 PM PST 23	Nov 22 02:55:37 PM PST 23	1087056547 ps
T37	/workspace/coverage/default/7.spi_device_upload.100631510652710186648345576436455779675808527121231130930042345587417566742867			Nov 22 02:49:02 PM PST 23	Nov 22 02:49:20 PM PST 23	6582334013 ps
T144	/workspace/coverage/default/22.spi_device_tpm_sts_read.62812889300920575231661174527333927545137670899496639541110403528111946170050			Nov 22 02:51:36 PM PST 23	Nov 22 02:51:37 PM PST 23	154474722 ps
T291	/workspace/coverage/default/22.spi_device_dummy_item_extra_dly.110528629781948109322183102900391642655051281372729877354968045051520503705			Nov 22 02:51:21 PM PST 23	Nov 22 02:55:39 PM PST 23	52275022040 ps
T149	/workspace/coverage/default/17.spi_device_rx_timeout.86892263901533218724297221263282669606442887141731754848660528649957776850708			Nov 22 02:50:20 PM PST 23	Nov 22 02:50:27 PM PST 23	1221948325 ps
T35	/workspace/coverage/default/10.spi_device_flash_all.97934395926982463584721229223414730448502527509290740939116407570996771882890			Nov 22 02:49:59 PM PST 23	Nov 22 02:54:23 PM PST 23	85193115836 ps
T141	/workspace/coverage/default/7.spi_device_tpm_all.63538894751777438359643563278940793230206612664660215667008073634233613748424			Nov 22 02:48:59 PM PST 23	Nov 22 02:50:09 PM PST 23	14078327616 ps
T114	/workspace/coverage/default/19.spi_device_alert_test.48858259629825499433978468977252168543105725947592774425659915580444273010467			Nov 22 02:51:01 PM PST 23	Nov 22 02:51:02 PM PST 23	17993671 ps
T115	/workspace/coverage/default/4.spi_device_alert_test.27714336977021044799189506933592541241087275633936003393009502442130346329001			Nov 22 02:48:39 PM PST 23	Nov 22 02:48:41 PM PST 23	17993671 ps
T167	/workspace/coverage/default/18.spi_device_flash_mode.54735744013646687400905813408760216589293481502693899061362381833718693898516			Nov 22 02:50:57 PM PST 23	Nov 22 02:51:06 PM PST 23	1087056547 ps
T175	/workspace/coverage/default/1.spi_device_mailbox.21514572648949558130156439819733201161971710920294170923181230196139176439549			Nov 22 02:48:06 PM PST 23	Nov 22 02:48:54 PM PST 23	22218066069 ps
T38	/workspace/coverage/default/33.spi_device_intercept.104530479345867478530252265913857398949465702191397126759895866300380587869802			Nov 22 02:53:33 PM PST 23	Nov 22 02:53:43 PM PST 23	3388073853 ps
T142	/workspace/coverage/default/32.spi_device_tpm_rw.105198819089451719803833856577145819545701898943147349296766145841773616071332			Nov 22 02:53:28 PM PST 23	Nov 22 02:53:32 PM PST 23	334616138 ps
T69	/workspace/coverage/default/18.spi_device_fifo_underflow_overflow.111390776579580292628329190239595339773142168232459496258398677996490775936929			Nov 22 02:50:58 PM PST 23	Nov 22 02:55:04 PM PST 23	39286733090 ps
T181	/workspace/coverage/default/14.spi_device_smoke.56874677421016076217924683869789080075456384257632046168489784916774237459129			Nov 22 02:50:08 PM PST 23	Nov 22 02:50:09 PM PST 23	37422087 ps
T111	/workspace/coverage/default/6.spi_device_rx_async_fifo_reset.49712150373384732083967721822269047496783707903155553077255950225749933158538			Nov 22 02:48:51 PM PST 23	Nov 22 02:48:52 PM PST 23	46761298 ps
T182	/workspace/coverage/default/8.spi_device_smoke.59670784741164487217076612574452311332370823783126595605723582808652305825689			Nov 22 02:49:11 PM PST 23	Nov 22 02:49:12 PM PST 23	37422087 ps
T292	/workspace/coverage/default/24.spi_device_byte_transfer.82496958703843602077585842329514883380073973477609560034930356992701958151046			Nov 22 02:51:55 PM PST 23	Nov 22 02:51:59 PM PST 23	272580920 ps
T293	/workspace/coverage/default/0.spi_device_txrx.78355561434122996431379021962562770922046401893471485035625747373990883767452			Nov 22 02:47:49 PM PST 23	Nov 22 02:52:15 PM PST 23	45776109746 ps
T168	/workspace/coverage/default/1.spi_device_flash_mode.12575446771401847330777363345191643715159965822532437541544096311303884628585			Nov 22 02:47:58 PM PST 23	Nov 22 02:48:06 PM PST 23	1087056547 ps
T112	/workspace/coverage/default/2.spi_device_rx_async_fifo_reset.104524203905809583298464642650538213391865304253972779744478920323243302965499			Nov 22 02:48:19 PM PST 23	Nov 22 02:48:20 PM PST 23	46761298 ps
T108	/workspace/coverage/default/21.spi_device_tx_async_fifo_reset.72153442576765255072793602691389490445866327709031965677436460635370570310756			Nov 22 02:51:21 PM PST 23	Nov 22 02:51:26 PM PST 23	23582912 ps
T294	/workspace/coverage/default/16.spi_device_extreme_fifo_size.40552995665821964258584483394036774190658873281285680964824254727776878598292			Nov 22 02:50:23 PM PST 23	Nov 22 03:04:01 PM PST 23	113592817208 ps
T295	/workspace/coverage/default/36.spi_device_extreme_fifo_size.25658801564689983705086768365273804106481710670115503555032526824124468724223			Nov 22 02:53:57 PM PST 23	Nov 22 03:07:56 PM PST 23	113592817208 ps
T169	/workspace/coverage/default/6.spi_device_flash_mode.113640045431887809188121603650349417225112009373114030349657913221609555171619			Nov 22 02:48:53 PM PST 23	Nov 22 02:49:02 PM PST 23	1087056547 ps
T296	/workspace/coverage/default/33.spi_device_txrx.7322032550426645752821226577468959539065206048815269038559229938990156579988			Nov 22 02:53:21 PM PST 23	Nov 22 02:57:53 PM PST 23	45776109746 ps
T70	/workspace/coverage/default/22.spi_device_fifo_underflow_overflow.76886067843174559392273415323944125350335691108225926312277449863739793534546			Nov 22 02:51:21 PM PST 23	Nov 22 02:55:39 PM PST 23	39286733090 ps
T297	/workspace/coverage/default/37.spi_device_byte_transfer.108062263119717811296604045719597563803878862575045720828150296303243754916789			Nov 22 02:54:22 PM PST 23	Nov 22 02:54:32 PM PST 23	272580920 ps
T178	/workspace/coverage/default/21.spi_device_intr.108687011949553382734185008407582210785216291579340574324537586203025816766313			Nov 22 02:51:21 PM PST 23	Nov 22 02:51:57 PM PST 23	9117581588 ps
T298	/workspace/coverage/default/26.spi_device_dummy_item_extra_dly.113176933575519014042305347786172649918390656963218421533194427078027292271236			Nov 22 02:52:08 PM PST 23	Nov 22 02:56:12 PM PST 23	52275022040 ps
T109	/workspace/coverage/default/0.spi_device_tx_async_fifo_reset.7935976241365926701331148594984956595992246538737982764446072823707765177343			Nov 22 02:47:43 PM PST 23	Nov 22 02:47:45 PM PST 23	23582912 ps
T78	/workspace/coverage/default/46.spi_device_tpm_read_hw_reg.56357535311515809467479882918648351983376979029403649683696026793799286092746			Nov 22 02:55:37 PM PST 23	Nov 22 02:56:04 PM PST 23	12597285893 ps
T179	/workspace/coverage/default/14.spi_device_fifo_full.111724296085073996504190575539276696859507984666905321259085853048735563749852			Nov 22 02:50:02 PM PST 23	Nov 22 03:02:59 PM PST 23	69486455776 ps
T299	/workspace/coverage/default/24.spi_device_fifo_full.55083762837003630790354500164014467841272516590458859591905606102796192416141			Nov 22 02:52:08 PM PST 23	Nov 22 03:04:15 PM PST 23	69486455776 ps
T300	/workspace/coverage/default/1.spi_device_txrx.9259056379768713274137310043918427728566835868720229307763824772228218870337			Nov 22 02:47:42 PM PST 23	Nov 22 02:52:10 PM PST 23	45776109746 ps
T301	/workspace/coverage/default/22.spi_device_smoke.104493195914708023259119249162532580410230511761800599388487789449910554269596			Nov 22 02:51:18 PM PST 23	Nov 22 02:51:20 PM PST 23	37422087 ps
T39	/workspace/coverage/default/32.spi_device_pass_cmd_filtering.18091732425224216325782939896507975660106970590696752247594695544674559059681			Nov 22 02:53:18 PM PST 23	Nov 22 02:53:46 PM PST 23	11600901007 ps
T80	/workspace/coverage/default/42.spi_device_abort.36529475757393352783259718148712818789705998897600490781324534047263085299641			Nov 22 02:55:31 PM PST 23	Nov 22 02:55:32 PM PST 23	21440072 ps
T40	/workspace/coverage/default/46.spi_device_intercept.84738325629801262194105099984206850092011629902030700557003634584552280492164			Nov 22 02:55:46 PM PST 23	Nov 22 02:55:57 PM PST 23	3388073853 ps
T302	/workspace/coverage/default/33.spi_device_fifo_full.40129217005616238847928898571982592464083859578161303650635253131102855219231			Nov 22 02:53:30 PM PST 23	Nov 22 03:06:09 PM PST 23	69486455776 ps
T303	/workspace/coverage/default/12.spi_device_abort.110264879521981962735985580395046776287397950739053936101492754191509700530878			Nov 22 02:49:48 PM PST 23	Nov 22 02:49:50 PM PST 23	21440072 ps
T304	/workspace/coverage/default/21.spi_device_perf.59183855002732059676307802701215483703007228560405249764935815296549548176159			Nov 22 02:51:20 PM PST 23	Nov 22 02:53:59 PM PST 23	8264927695 ps