Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	213875	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

212693

1

T1

814

T2

377

T3

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	287825	1			T1	418		T2	101		T3	29
values[0x0]	68312	1			T1	187		T2	151		T3	17
values[0x1]	70431	1			T1	211		T2	282		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	152302	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

274266

1

T1

814

T2

475

T3

28

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1640	1			T1	6		T2	1		T4	1
valid_sources[0x01]	1358	1			T1	4		T2	1		T3	1
valid_sources[0x02]	1858	1			T4	1		T15	3		T25	1
valid_sources[0x03]	1389	1			T1	10		T2	1		T4	1
valid_sources[0x04]	1686	1			T1	11		T2	1		T14	1
valid_sources[0x05]	1581	1			T1	1		T2	5		T9	6
valid_sources[0x06]	1666	1			T2	1		T5	17		T15	8
valid_sources[0x07]	1363	1			T1	4		T2	1		T15	1
valid_sources[0x08]	1423	1			T1	3		T2	3		T9	2
valid_sources[0x09]	2606	1			T1	3		T2	2		T9	9
valid_sources[0x0a]	1808	1			T1	1		T15	4		T25	9
valid_sources[0x0b]	1555	1			T2	1		T9	1		T8	10
valid_sources[0x0c]	1322	1			T1	1		T2	1		T5	1
valid_sources[0x0d]	2848	1			T2	1		T9	3		T15	3
valid_sources[0x0e]	1545	1			T1	4		T2	1		T3	1
valid_sources[0x0f]	1535	1			T1	2		T2	3		T3	1
valid_sources[0x10]	1345	1			T1	6		T2	2		T9	6
valid_sources[0x11]	2118	1			T1	6		T2	5		T5	6
valid_sources[0x12]	1355	1			T1	5		T3	1		T15	4
valid_sources[0x13]	1588	1			T1	6		T2	2		T9	4
valid_sources[0x14]	1653	1			T1	6		T2	1		T3	1
valid_sources[0x15]	2310	1			T1	4		T9	4		T8	8
valid_sources[0x16]	1433	1			T1	2		T2	2		T9	1
valid_sources[0x17]	1592	1			T1	1		T2	1		T9	4
valid_sources[0x18]	1880	1			T1	5		T2	2		T15	8
valid_sources[0x19]	2364	1			T2	2		T3	1		T9	4
valid_sources[0x1a]	1785	1			T1	4		T9	8		T15	5
valid_sources[0x1b]	1327	1			T1	2		T2	1		T9	1
valid_sources[0x1c]	1496	1			T1	2		T2	3		T9	1
valid_sources[0x1d]	1399	1			T2	2		T9	7		T15	1
valid_sources[0x1e]	4571	1			T1	4		T2	3		T9	3
valid_sources[0x1f]	1453	1			T1	3		T2	1		T3	1
valid_sources[0x20]	1340	1			T1	4		T2	4		T9	3
valid_sources[0x21]	1411	1			T1	4		T2	1		T9	6
valid_sources[0x22]	1697	1			T2	2		T3	1		T9	1
valid_sources[0x23]	1778	1			T1	7		T9	2		T5	9
valid_sources[0x24]	1420	1			T2	2		T9	2		T5	1
valid_sources[0x25]	1744	1			T1	11		T2	2		T9	2
valid_sources[0x26]	1822	1			T1	2		T2	4		T9	4
valid_sources[0x27]	1561	1			T1	6		T3	1		T9	13
valid_sources[0x28]	1189	1			T1	3		T2	1		T9	6
valid_sources[0x29]	1639	1			T1	1		T2	1		T9	2
valid_sources[0x2a]	1721	1			T1	2		T2	2		T3	1
valid_sources[0x2b]	2083	1			T2	4		T9	3		T13	5
valid_sources[0x2c]	1846	1			T1	2		T2	2		T3	1
valid_sources[0x2d]	1490	1			T1	9		T2	6		T9	9
valid_sources[0x2e]	1558	1			T2	1		T9	1		T5	3
valid_sources[0x2f]	1811	1			T2	2		T3	2		T9	1
valid_sources[0x30]	2314	1			T1	4		T2	1		T9	16
valid_sources[0x31]	1482	1			T2	3		T9	6		T15	4
valid_sources[0x32]	1627	1			T1	1		T2	1		T9	2
valid_sources[0x33]	1547	1			T2	1		T9	1		T5	3
valid_sources[0x34]	1818	1			T2	2		T3	1		T9	19
valid_sources[0x35]	1778	1			T1	2		T2	4		T9	4
valid_sources[0x36]	1363	1			T1	5		T9	6		T15	6
valid_sources[0x37]	1395	1			T1	5		T2	3		T9	2
valid_sources[0x38]	1710	1			T1	3		T2	2		T9	3
valid_sources[0x39]	1447	1			T1	3		T2	6		T9	3
valid_sources[0x3a]	1342	1			T1	2		T2	3		T13	4
valid_sources[0x3b]	1556	1			T1	5		T9	2		T4	1
valid_sources[0x3c]	2168	1			T2	3		T5	4		T15	6
valid_sources[0x3d]	1586	1			T1	2		T2	2		T15	5
valid_sources[0x3e]	2691	1			T1	2		T2	1		T9	2
valid_sources[0x3f]	1984	1			T15	7		T16	14		T11	16
valid_sources[0x40]	1490	1			T2	6		T9	1		T15	5
valid_sources[0x41]	1357	1			T2	1		T5	2		T15	1
valid_sources[0x42]	1622	1			T1	2		T2	1		T15	3
valid_sources[0x43]	1692	1			T2	1		T4	1		T15	5
valid_sources[0x44]	2192	1			T1	3		T2	3		T9	5
valid_sources[0x45]	1489	1			T1	1		T9	5		T15	5
valid_sources[0x46]	1648	1			T1	2		T2	3		T4	1
valid_sources[0x47]	1744	1			T1	1		T2	5		T9	4
valid_sources[0x48]	1521	1			T1	5		T2	5		T3	1
valid_sources[0x49]	2367	1			T2	2		T9	5		T15	4
valid_sources[0x4a]	1351	1			T1	2		T2	1		T15	1
valid_sources[0x4b]	1470	1			T1	3		T2	2		T3	1
valid_sources[0x4c]	1854	1			T1	7		T2	2		T5	2
valid_sources[0x4d]	1696	1			T1	4		T2	6		T3	1
valid_sources[0x4e]	1385	1			T1	4		T9	1		T14	2
valid_sources[0x4f]	1431	1			T1	3		T14	4		T15	3
valid_sources[0x50]	1526	1			T2	4		T9	1		T15	10
valid_sources[0x51]	1325	1			T1	9		T2	3		T9	4
valid_sources[0x52]	1543	1			T1	3		T2	2		T15	4
valid_sources[0x53]	1524	1			T1	7		T2	4		T3	1
valid_sources[0x54]	1663	1			T9	3		T4	1		T15	2
valid_sources[0x55]	1599	1			T1	2		T9	10		T15	7
valid_sources[0x56]	1691	1			T1	1		T2	1		T9	9
valid_sources[0x57]	1390	1			T1	5		T9	3		T14	2
valid_sources[0x58]	1547	1			T1	2		T2	3		T9	1
valid_sources[0x59]	1740	1			T1	12		T2	3		T9	7
valid_sources[0x5a]	1575	1			T1	2		T9	8		T4	1
valid_sources[0x5b]	1729	1			T2	2		T3	1		T9	2
valid_sources[0x5c]	1652	1			T2	7		T15	2		T25	3
valid_sources[0x5d]	2304	1			T1	3		T2	4		T9	2
valid_sources[0x5e]	1466	1			T1	1		T2	3		T9	6
valid_sources[0x5f]	1866	1			T1	3		T15	1		T25	2
valid_sources[0x60]	1470	1			T1	3		T2	3		T9	1
valid_sources[0x61]	2285	1			T1	1		T2	1		T9	7
valid_sources[0x62]	1845	1			T1	2		T2	5		T9	4
valid_sources[0x63]	1629	1			T1	2		T2	3		T3	1
valid_sources[0x64]	1585	1			T1	6		T3	1		T15	1
valid_sources[0x65]	1343	1			T1	4		T2	5		T9	5
valid_sources[0x66]	1302	1			T1	1		T2	4		T9	1
valid_sources[0x67]	1658	1			T1	3		T2	1		T9	1
valid_sources[0x68]	1575	1			T1	11		T2	3		T9	7
valid_sources[0x69]	1389	1			T2	5		T3	1		T9	2
valid_sources[0x6a]	1503	1			T1	1		T2	5		T3	1
valid_sources[0x6b]	1629	1			T2	3		T14	3		T15	2
valid_sources[0x6c]	1754	1			T1	3		T2	3		T9	3
valid_sources[0x6d]	1398	1			T1	1		T2	2		T9	3
valid_sources[0x6e]	1675	1			T1	1		T2	2		T3	1
valid_sources[0x6f]	1607	1			T1	8		T2	5		T9	2
valid_sources[0x70]	1401	1			T1	13		T2	3		T3	1
valid_sources[0x71]	1562	1			T1	3		T2	4		T3	1
valid_sources[0x72]	1330	1			T1	3		T2	1		T3	1
valid_sources[0x73]	1585	1			T1	2		T2	3		T9	6
valid_sources[0x74]	1329	1			T1	3		T5	2		T15	3
valid_sources[0x75]	1766	1			T1	2		T2	3		T9	2
valid_sources[0x76]	1467	1			T1	5		T9	2		T15	2
valid_sources[0x77]	1492	1			T1	2		T2	5		T9	4
valid_sources[0x78]	1976	1			T1	1		T2	1		T9	3
valid_sources[0x79]	1358	1			T1	1		T3	1		T9	1
valid_sources[0x7a]	1723	1			T1	4		T2	4		T3	2
valid_sources[0x7b]	7457	1			T1	2		T2	2		T9	4
valid_sources[0x7c]	1344	1			T1	4		T2	2		T9	2
valid_sources[0x7d]	1732	1			T1	1		T2	4		T9	4
valid_sources[0x7e]	1672	1			T1	2		T2	3		T9	2
valid_sources[0x7f]	1583	1			T1	7		T2	1		T9	3
valid_sources[0x80]	1559	1			T1	5		T2	2		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

89306

1

T1

417

T2

85

T3

11

values[0x0]

all_enables

biggest_size

63043

1

T1

187

T2

139

T3

10

values[0x1]

all_enables

biggest_size

60344

1

T1

210

T2

153

T9

190