Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

239594

1

T1

2

T2

1717

T3

37

full_word

214229

1

T1

814

T2

488

T3

21

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	453443	1			T1	816		T2	2205		T3	58
auto[TlIntgErrCmd]	135	1			T10	3		T11	4		T12	4
auto[TlIntgErrData]	126	1			T10	5		T11	3		T12	1
auto[TlIntgErrBoth]	119	1			T10	2		T11	3		T12	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

290589

1

T1

418

T2

272

T3

29

auto[1]

163234

1

T1

398

T2

1933

T3

29

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	200838	1			T1	1		T2	166		T3	18
auto[TlIntgErrNone]	partial	auto[1]	38409	1			T1	1		T2	1551		T3	19
auto[TlIntgErrNone]	full_word	auto[0]	89584	1			T1	417		T2	106		T3	11
auto[TlIntgErrNone]	full_word	auto[1]	124612	1			T1	397		T2	382		T3	10
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T10	2		T11	1		T12	2
auto[TlIntgErrCmd]	partial	auto[1]	76	1			T10	1		T11	3		T12	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T63	1		T64	1		T65	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T22	1		T66	2		T67	2
auto[TlIntgErrData]	partial	auto[0]	54	1			T10	2		T11	2		T26	2
auto[TlIntgErrData]	partial	auto[1]	60	1			T10	3		T11	1		T12	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T23	1		T49	1		T51	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T23	1		T63	1		T68	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T12	4		T26	5		T22	6
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T10	1		T11	1		T12	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T26	1		T64	1		T68	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T10	1		T11	2		T62	1