Unified Coverage Report :: Module :: prim_fifo_async

Module : prim_fifo_async

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_fwmode.u_rx_fifo	0.00	0.00	0.00			0.00
tb.dut.u_fwmode.u_tx_fifo	0.00	0.00	0.00			0.00
tb.dut.u_spid_status.u_sw_status_update_sync	0.00	0.00	0.00			0.00
tb.dut.u_spi_tpm.u_cmdaddr_buffer	0.00	0.00	0.00			0.00
tb.dut.u_spi_tpm.u_wrfifo	0.00	0.00	0.00			0.00
tb.dut.u_spi_tpm.u_rdfifo	0.00	0.00	0.00			0.00

Line Coverage for Module : prim_fifo_async ( parameter Width=8,Depth=8,OutputZeroIfEmpty=0,OutputZeroIfInvalid=0,DepthW=4,PTRV_W=3,PTR_WIDTH=4 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_fwmode.u_rx_fifo

SCORE	LINE
0.00	0.00

tb.dut.u_fwmode.u_tx_fifo

	Line No.	Total	Covered	Percent
TOTAL		62	0	0.00
CONT_ASSIGN	53	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
ALWAYS	59	4	0	0.00
ALWAYS	68	4	0	0.00
CONT_ASSIGN	86	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
ALWAYS	92	4	0	0.00
ALWAYS	101	4	0	0.00
ALWAYS	117	3	0	0.00
CONT_ASSIGN	130	1	0	0.00
CONT_ASSIGN	131	1	0	0.00
CONT_ASSIGN	132	1	0	0.00
CONT_ASSIGN	142	1	0	0.00
CONT_ASSIGN	143	1	0	0.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	146	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	157	1	0	0.00
CONT_ASSIGN	158	1	0	0.00
CONT_ASSIGN	159	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	171	1	0	0.00
CONT_ASSIGN	172	1	0	0.00
ALWAYS	182	2	0	0.00
CONT_ASSIGN	187	1	0	0.00
CONT_ASSIGN	214	1	0	0.00
ROUTINE	230	7	0	0.00
ROUTINE	251	9	0	0.00
CONT_ASSIGN	267	1	0	0.00
CONT_ASSIGN	269	1	0	0.00
CONT_ASSIGN	271	1	0	0.00
CONT_ASSIGN	272	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	0	1
56	0	1
59	0	1
60	0	1
61	0	1
62	0	1
			==> MISSING_ELSE
68	0	1
69	0	1
70	0	1
71	0	1
			==> MISSING_ELSE
86	0	1
89	0	1
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE
101	0	1
102	0	1
103	0	1
104	0	1
			==> MISSING_ELSE
117	0	1
118	0	1
120	0	1
130	0	1
131	0	1
132	0	1
142	0	1
143	0	1
144	0	1
145	0	1
146	0	1
156	0	1
157	0	1
158	0	1
159	0	1
160	0	1
171	0	1
172	0	1
182	0	1
183	0	1
			==> MISSING_ELSE
187	0	1
214	0	1
230	0	1
232	0	1
235	0	1
236	0	1
239	0	1
240	0	1
243	0	1
251	0	1
252	0	1
253	0	1
255	0	1
256	0	1
257	0	1
259	0	1
260	0	1
262	0	1
267	0	1
269	0	1
271	0	1
272	0	1

---

Line Coverage for Module : prim_fifo_async ( parameter Width=24,Depth=2,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=2,PTRV_W=1,PTR_WIDTH=2 + Width=32,Depth=2,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=2,PTRV_W=1,PTR_WIDTH=2 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_spid_status.u_sw_status_update_sync

SCORE	LINE
0.00	0.00

tb.dut.u_spi_tpm.u_cmdaddr_buffer

	Line No.	Total	Covered	Percent
TOTAL		46	0	0.00
CONT_ASSIGN	53	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
ALWAYS	59	4	0	0.00
ALWAYS	68	4	0	0.00
CONT_ASSIGN	86	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
ALWAYS	92	4	0	0.00
ALWAYS	101	4	0	0.00
ALWAYS	117	3	0	0.00
CONT_ASSIGN	130	1	0	0.00
CONT_ASSIGN	131	1	0	0.00
CONT_ASSIGN	132	1	0	0.00
CONT_ASSIGN	142	1	0	0.00
CONT_ASSIGN	143	1	0	0.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	146	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	157	1	0	0.00
CONT_ASSIGN	158	1	0	0.00
CONT_ASSIGN	159	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	171	1	0	0.00
CONT_ASSIGN	172	1	0	0.00
ALWAYS	182	2	0	0.00
CONT_ASSIGN	187	1	0	0.00
CONT_ASSIGN	207	1	0	0.00
CONT_ASSIGN	276	1	0	0.00
CONT_ASSIGN	277	1	0	0.00
CONT_ASSIGN	279	1	0	0.00
CONT_ASSIGN	280	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	0	1
56	0	1
59	0	1
60	0	1
61	0	1
62	0	1
			==> MISSING_ELSE
68	0	1
69	0	1
70	0	1
71	0	1
			==> MISSING_ELSE
86	0	1
89	0	1
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE
101	0	1
102	0	1
103	0	1
104	0	1
			==> MISSING_ELSE
117	0	1
118	0	1
120	0	1
130	0	1
131	0	1
132	0	1
142	0	1
143	0	1
144	0	1
145	0	1
146	0	1
156	0	1
157	0	1
158	0	1
159	0	1
160	0	1
171	0	1
172	0	1
182	0	1
183	0	1
			==> MISSING_ELSE
187	0	1
207	0	1
276	0	1
277	0	1
279	0	1
280	0	1

---

Line Coverage for Module : prim_fifo_async ( parameter Width=8,Depth=64,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=7,PTRV_W=6,PTR_WIDTH=7 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_spi_tpm.u_wrfifo

	Line No.	Total	Covered	Percent
TOTAL		62	0	0.00
CONT_ASSIGN	53	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
ALWAYS	59	4	0	0.00
ALWAYS	68	4	0	0.00
CONT_ASSIGN	86	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
ALWAYS	92	4	0	0.00
ALWAYS	101	4	0	0.00
ALWAYS	117	3	0	0.00
CONT_ASSIGN	130	1	0	0.00
CONT_ASSIGN	131	1	0	0.00
CONT_ASSIGN	132	1	0	0.00
CONT_ASSIGN	142	1	0	0.00
CONT_ASSIGN	143	1	0	0.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	146	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	157	1	0	0.00
CONT_ASSIGN	158	1	0	0.00
CONT_ASSIGN	159	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	171	1	0	0.00
CONT_ASSIGN	172	1	0	0.00
ALWAYS	182	2	0	0.00
CONT_ASSIGN	187	1	0	0.00
CONT_ASSIGN	207	1	0	0.00
ROUTINE	230	7	0	0.00
ROUTINE	251	9	0	0.00
CONT_ASSIGN	267	1	0	0.00
CONT_ASSIGN	269	1	0	0.00
CONT_ASSIGN	271	1	0	0.00
CONT_ASSIGN	272	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	0	1
56	0	1
59	0	1
60	0	1
61	0	1
62	0	1
			==> MISSING_ELSE
68	0	1
69	0	1
70	0	1
71	0	1
			==> MISSING_ELSE
86	0	1
89	0	1
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE
101	0	1
102	0	1
103	0	1
104	0	1
			==> MISSING_ELSE
117	0	1
118	0	1
120	0	1
130	0	1
131	0	1
132	0	1
142	0	1
143	0	1
144	0	1
145	0	1
146	0	1
156	0	1
157	0	1
158	0	1
159	0	1
160	0	1
171	0	1
172	0	1
182	0	1
183	0	1
			==> MISSING_ELSE
187	0	1
207	0	1
230	0	1
232	0	1
235	0	1
236	0	1
239	0	1
240	0	1
243	0	1
251	0	1
252	0	1
253	0	1
255	0	1
256	0	1
257	0	1
259	0	1
260	0	1
262	0	1
267	0	1
269	0	1
271	0	1
272	0	1

---

Line Coverage for Module : prim_fifo_async ( parameter Width=32,Depth=16,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=5,PTRV_W=4,PTR_WIDTH=5 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_spi_tpm.u_rdfifo

	Line No.	Total	Covered	Percent
TOTAL		62	0	0.00
CONT_ASSIGN	53	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
ALWAYS	59	4	0	0.00
ALWAYS	68	4	0	0.00
CONT_ASSIGN	86	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
ALWAYS	92	4	0	0.00
ALWAYS	101	4	0	0.00
ALWAYS	117	3	0	0.00
CONT_ASSIGN	130	1	0	0.00
CONT_ASSIGN	131	1	0	0.00
CONT_ASSIGN	132	1	0	0.00
CONT_ASSIGN	142	1	0	0.00
CONT_ASSIGN	143	1	0	0.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	146	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	157	1	0	0.00
CONT_ASSIGN	158	1	0	0.00
CONT_ASSIGN	159	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	171	1	0	0.00
CONT_ASSIGN	172	1	0	0.00
ALWAYS	182	2	0	0.00
CONT_ASSIGN	187	1	0	0.00
CONT_ASSIGN	207	1	0	0.00
ROUTINE	230	7	0	0.00
ROUTINE	251	9	0	0.00
CONT_ASSIGN	267	1	0	0.00
CONT_ASSIGN	269	1	0	0.00
CONT_ASSIGN	271	1	0	0.00
CONT_ASSIGN	272	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	0	1
56	0	1
59	0	1
60	0	1
61	0	1
62	0	1
			==> MISSING_ELSE
68	0	1
69	0	1
70	0	1
71	0	1
			==> MISSING_ELSE
86	0	1
89	0	1
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE
101	0	1
102	0	1
103	0	1
104	0	1
			==> MISSING_ELSE
117	0	1
118	0	1
120	0	1
130	0	1
131	0	1
132	0	1
142	0	1
143	0	1
144	0	1
145	0	1
146	0	1
156	0	1
157	0	1
158	0	1
159	0	1
160	0	1
171	0	1
172	0	1
182	0	1
183	0	1
			==> MISSING_ELSE
187	0	1
207	0	1
230	0	1
232	0	1
235	0	1
236	0	1
239	0	1
240	0	1
243	0	1
251	0	1
252	0	1
253	0	1
255	0	1
256	0	1
257	0	1
259	0	1
260	0	1
262	0	1
267	0	1
269	0	1
271	0	1
272	0	1

---

Cond Coverage for Module : prim_fifo_async ( parameter Width=8,Depth=8,OutputZeroIfEmpty=0,OutputZeroIfInvalid=0,DepthW=4,PTRV_W=3,PTR_WIDTH=4 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.u_fwmode.u_rx_fifo

SCORE	COND
0.00	0.00

tb.dut.u_fwmode.u_tx_fifo

	Total	Covered	Percent
Conditions	30	0	0.00
Logical	30	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (4'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((4'(g_depth_calc.wptr_value) - 4'(g_depth_calc.rptr_sync_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_sync_value)) + 4'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((4'(g_depth_calc.wptr_value) - 4'(g_depth_calc.rptr_sync_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_sync_value)) + 4'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (4'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((4'(g_depth_calc.wptr_sync_value) - 4'(g_depth_calc.rptr_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_value)) + 4'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((4'(g_depth_calc.wptr_sync_value) - 4'(g_depth_calc.rptr_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_value)) + 4'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       232
 EXPRESSION (decval[(PTR_WIDTH - 1)] ? decval_sub : decval)
             -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       253
 EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Cond Coverage for Module : prim_fifo_async ( parameter Width=8,Depth=64,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=7,PTRV_W=6,PTR_WIDTH=7 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.u_spi_tpm.u_wrfifo

	Total	Covered	Percent
Conditions	32	0	0.00
Logical	32	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (7'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((7'(g_depth_calc.wptr_value) - 7'(g_depth_calc.rptr_sync_value))) : (((7'(Depth) - 7'(g_depth_calc.rptr_sync_value)) + 7'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((7'(g_depth_calc.wptr_value) - 7'(g_depth_calc.rptr_sync_value))) : (((7'(Depth) - 7'(g_depth_calc.rptr_sync_value)) + 7'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (7'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((7'(g_depth_calc.wptr_sync_value) - 7'(g_depth_calc.rptr_value))) : (((7'(Depth) - 7'(g_depth_calc.rptr_value)) + 7'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((7'(g_depth_calc.wptr_sync_value) - 7'(g_depth_calc.rptr_value))) : (((7'(Depth) - 7'(g_depth_calc.rptr_value)) + 7'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       207
 EXPRESSION (empty_rclk ? '0 : rdata_int)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       232
 EXPRESSION (decval[(PTR_WIDTH - 1)] ? decval_sub : decval)
             -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       253
 EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Cond Coverage for Module : prim_fifo_async ( parameter Width=32,Depth=2,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=2,PTRV_W=1,PTR_WIDTH=2 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.u_spi_tpm.u_cmdaddr_buffer

	Total	Covered	Percent
Conditions	26	0	0.00
Logical	26	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (2'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (2'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       207
 EXPRESSION (empty_rclk ? '0 : rdata_int)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Cond Coverage for Module : prim_fifo_async ( parameter Width=24,Depth=2,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=2,PTRV_W=1,PTR_WIDTH=2 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.u_spid_status.u_sw_status_update_sync

	Total	Covered	Percent
Conditions	25	0	0.00
Logical	25	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (2'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (2'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       207
 EXPRESSION (empty_rclk ? '0 : rdata_int)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Cond Coverage for Module : prim_fifo_async ( parameter Width=32,Depth=16,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=5,PTRV_W=4,PTR_WIDTH=5 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.u_spi_tpm.u_rdfifo

	Total	Covered	Percent
Conditions	32	0	0.00
Logical	32	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (5'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((5'(g_depth_calc.wptr_value) - 5'(g_depth_calc.rptr_sync_value))) : (((5'(Depth) - 5'(g_depth_calc.rptr_sync_value)) + 5'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((5'(g_depth_calc.wptr_value) - 5'(g_depth_calc.rptr_sync_value))) : (((5'(Depth) - 5'(g_depth_calc.rptr_sync_value)) + 5'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (5'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((5'(g_depth_calc.wptr_sync_value) - 5'(g_depth_calc.rptr_value))) : (((5'(Depth) - 5'(g_depth_calc.rptr_value)) + 5'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((5'(g_depth_calc.wptr_sync_value) - 5'(g_depth_calc.rptr_value))) : (((5'(Depth) - 5'(g_depth_calc.rptr_value)) + 5'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       207
 EXPRESSION (empty_rclk ? '0 : rdata_int)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       232
 EXPRESSION (decval[(PTR_WIDTH - 1)] ? decval_sub : decval)
             -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       253
 EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : prim_fifo_async ( parameter Width=24,Depth=2,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=2,PTRV_W=1,PTR_WIDTH=2 + Width=32,Depth=2,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=2,PTRV_W=1,PTR_WIDTH=2 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
0.00	0.00

tb.dut.u_spid_status.u_sw_status_update_sync

SCORE	BRANCH
0.00	0.00

tb.dut.u_spi_tpm.u_cmdaddr_buffer

	Line No.	Total	Covered	Percent
Branches		24	0	0.00
TERNARY	146	3	0	0.00
TERNARY	160	3	0	0.00
TERNARY	207	2	0	0.00
IF	59	3	0	0.00
IF	68	3	0	0.00
IF	92	3	0	0.00
IF	101	3	0	0.00
IF	117	2	0	0.00
IF	182	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	146	(full_wclk) ? 
-2-:	146	((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	160	(full_rclk) ? 
-2-:	160	((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	207	(empty_rclk) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	182	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

---

Branch Coverage for Module : prim_fifo_async ( parameter Width=8,Depth=8,OutputZeroIfEmpty=0,OutputZeroIfInvalid=0,DepthW=4,PTRV_W=3,PTR_WIDTH=4 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
0.00	0.00

tb.dut.u_fwmode.u_rx_fifo

SCORE	BRANCH
0.00	0.00

tb.dut.u_fwmode.u_tx_fifo

	Line No.	Total	Covered	Percent
Branches		26	0	0.00
TERNARY	146	3	0	0.00
TERNARY	160	3	0	0.00
IF	59	3	0	0.00
IF	68	3	0	0.00
IF	92	3	0	0.00
IF	101	3	0	0.00
IF	117	2	0	0.00
IF	182	2	0	0.00
TERNARY	232	2	0	0.00
IF	256	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	146	(full_wclk) ? 
-2-:	146	((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	160	(full_rclk) ? 
-2-:	160	((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	182	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	232	(decval[(PTR_WIDTH - 1)]) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	256	if (grayval[(PTR_WIDTH - 1)])

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

---

Branch Coverage for Module : prim_fifo_async ( parameter Width=8,Depth=64,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=7,PTRV_W=6,PTR_WIDTH=7 + Width=32,Depth=16,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=5,PTRV_W=4,PTR_WIDTH=5 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
0.00	0.00

tb.dut.u_spi_tpm.u_wrfifo

SCORE	BRANCH
0.00	0.00

tb.dut.u_spi_tpm.u_rdfifo

	Line No.	Total	Covered	Percent
Branches		28	0	0.00
TERNARY	146	3	0	0.00
TERNARY	160	3	0	0.00
TERNARY	207	2	0	0.00
IF	59	3	0	0.00
IF	68	3	0	0.00
IF	92	3	0	0.00
IF	101	3	0	0.00
IF	117	2	0	0.00
IF	182	2	0	0.00
TERNARY	232	2	0	0.00
IF	256	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	146	(full_wclk) ? 
-2-:	146	((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	160	(full_rclk) ? 
-2-:	160	((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	207	(empty_rclk) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	182	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	232	(decval[(PTR_WIDTH - 1)]) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	256	if (grayval[(PTR_WIDTH - 1)])

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered