Unified Coverage Report :: Module :: prim_slicer

Module : prim_slicer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_hw_reg_slice	0.00	0.00

---

Module Instance : tb.dut.u_spi_tpm.u_hw_reg_slice

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_slicer

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	25	1	0	0.00
CONT_ASSIGN	27	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	0	1
27	0	1