Unified Coverage Report :: Module :: spid_readsram

Module : spid_readsram

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_readsram.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_readcmd.u_readsram	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_readcmd.u_readsram

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_readcmd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_fifo	0.00	0.00	0.00			0.00
u_sram_fifo	0.00	0.00	0.00			0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spid_readsram

	Line No.	Total	Covered	Percent
TOTAL		57	0	0.00
CONT_ASSIGN	118	1	0	0.00
CONT_ASSIGN	123	1	0	0.00
CONT_ASSIGN	129	1	0	0.00
CONT_ASSIGN	146	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	161	1	0	0.00
ALWAYS	166	4	0	0.00
ALWAYS	172	6	0	0.00
ALWAYS	179	5	0	0.00
CONT_ASSIGN	189	1	0	0.00
ALWAYS	195	5	0	0.00
ALWAYS	225	3	0	0.00
ALWAYS	230	26	0	0.00
CONT_ASSIGN	346	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_readsram.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_readsram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
118	0	1
123	0	1
129	0	1
146	0	1
160	0	1
161	0	1
166	0	2
167	0	2
			==> MISSING_ELSE
172	0	2
173	0	2
174	0	2
			==> MISSING_ELSE
179	0	1
180	0	1
181	0	1
182	0	1
183	0	1
189	0	1
195	0	1
196	0	1
197	0	1
198	0	1
200	0	1
225	0	2
226	0	1
230	0	1
232	0	1
234	0	1
235	0	1
237	0	1
238	0	1
240	0	1
242	0	1
244	0	1
245	0	1
			==> MISSING_ELSE
248	0	1
251	0	1
253	0	1
258	0	1
259	0	1
			==> MISSING_ELSE
262	0	2
			==> MISSING_ELSE
264	0	1
266	0	1
268	0	1
270	0	1
277	0	1
278	0	1
279	0	1
281	0	1
283	0	1
346	0	1

---

Cond Coverage for Module : spid_readsram

	Total	Covered	Percent
Conditions	20	0	0.00
Logical	20	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       161
 EXPRESSION (mailbox_en_i && (mailbox_masked_addr == mailbox_addr_i))
             ------1-----    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       161
 SUB-EXPRESSION (mailbox_masked_addr == mailbox_addr_i)
                -------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       189
 EXPRESSION ((addr_sel == AddrContinuous) ? ({(current_address_i[31:2] + 1'b1), 2'b0}) : current_address_i)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       189
 SUB-EXPRESSION (addr_sel == AddrContinuous)
                --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       248
 EXPRESSION ((sram_read_req_i || sram_latched) && strb_set)
             ----------------1----------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       248
 SUB-EXPRESSION (sram_read_req_i || sram_latched)
                 -------1-------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       264
 EXPRESSION ((strb == 2'b11) && fifo_wready)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       264
 SUB-EXPRESSION (strb == 2'b11)
                -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Module : spid_readsram

Summary for FSM :: st_q

	Total	Covered	Percent
States	3	0	0.00	(Not included in score)
Transitions	3	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StActive	266	Not Covered
StIdle	253	Not Covered
StPush	251	Not Covered

transitions	Line No.	Covered	Tests
StActive->StPush	279	Not Covered
StIdle->StPush	251	Not Covered
StPush->StActive	266	Not Covered

---

Branch Coverage for Module : spid_readsram

	Line No.	Total	Covered	Percent
Branches		32	0	0.00
TERNARY	189	2	0	0.00
IF	166	3	0	0.00
IF	172	4	0	0.00
CASE	179	5	0	0.00
IF	195	3	0	0.00
IF	225	2	0	0.00
CASE	240	13	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_readsram.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_readsram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	189	((addr_sel == AddrContinuous)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	166	if ((!rst_ni))
-2-:	167	if (sram_req)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	172	if ((!rst_ni))
-2-:	173	if (data_inc)
-3-:	174	if (strb_set)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	179	case (strb)

Branches:

-1-	Status	Tests
2'b00	Not Covered
2'b01	Not Covered
2'b10	Not Covered
2'b11	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	195	if (sfdp_hit_i)
-2-:	197	if (mailbox_hit)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	225	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	240	case (st_q)
-2-:	244	if (sram_read_req_i)
-3-:	248	if (((sram_read_req_i || sram_latched) && strb_set))
-4-:	258	if (sram_d_valid)
-5-:	262	if (fifo_wready)
-6-:	264	if (((strb == 2'b11) && fifo_wready))
-7-:	278	if ((!sram_fifo_full))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle	1	-	-	-	-	-	Not Covered
StIdle	0	-	-	-	-	-	Not Covered
StIdle	-	1	-	-	-	-	Not Covered
StIdle	-	0	-	-	-	-	Not Covered
StPush	-	-	1	-	-	-	Not Covered
StPush	-	-	0	-	-	-	Not Covered
StPush	-	-	-	1	-	-	Not Covered
StPush	-	-	-	0	-	-	Not Covered
StPush	-	-	-	-	1	-	Not Covered
StPush	-	-	-	-	0	-	Not Covered
StActive	-	-	-	-	-	1	Not Covered
StActive	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	Not Covered