Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7165265	1			T4	971		T1	2		T5	1
all_values[1]	7165265	1			T4	971		T1	2		T5	1
all_values[2]	7165265	1			T4	971		T1	2		T5	1
all_values[3]	7165265	1			T4	971		T1	2		T5	1
all_values[4]	7165265	1			T4	971		T1	2		T5	1
all_values[5]	7165265	1			T4	971		T1	2		T5	1
all_values[6]	7165265	1			T4	971		T1	2		T5	1
all_values[7]	7165265	1			T4	971		T1	2		T5	1
all_values[8]	7165265	1			T4	971		T1	2		T5	1
all_values[9]	7165265	1			T4	971		T1	2		T5	1
all_values[10]	7165265	1			T4	971		T1	2		T5	1
all_values[11]	7165265	1			T4	971		T1	2		T5	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81275346

1

T4

11652

T1

14

T5

12

auto[1]

4707834

1

T1

10

T2

14

T3

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85920174

1

T4

11652

T1

24

T5

12

auto[1]

63006

1

T6

757

T66

43

T67

49

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	6881659	1			T4	971		T5	1		T3	2
all_values[0]	auto[0]	auto[1]	109	1			T66	1		T67	4		T68	2
all_values[0]	auto[1]	auto[0]	283379	1			T1	2		T2	2		T9	2
all_values[0]	auto[1]	auto[1]	118	1			T66	4		T67	2		T68	3
all_values[1]	auto[0]	auto[0]	6553021	1			T4	971		T5	1		T2	2
all_values[1]	auto[0]	auto[1]	98	1			T66	1		T67	2		T68	1
all_values[1]	auto[1]	auto[0]	612039	1			T1	2		T9	2		T17	2
all_values[1]	auto[1]	auto[1]	107	1			T66	3		T67	3		T68	2
all_values[2]	auto[0]	auto[0]	6553091	1			T4	971		T5	1		T3	2
all_values[2]	auto[0]	auto[1]	97	1			T67	1		T68	2		T156	3
all_values[2]	auto[1]	auto[0]	611972	1			T1	2		T2	2		T9	2
all_values[2]	auto[1]	auto[1]	105	1			T66	3		T67	3		T68	5
all_values[3]	auto[0]	auto[0]	6771273	1			T4	971		T5	1		T9	2
all_values[3]	auto[0]	auto[1]	99	1			T66	2		T67	3		T68	2
all_values[3]	auto[1]	auto[0]	393806	1			T1	2		T2	2		T3	2
all_values[3]	auto[1]	auto[1]	87	1			T67	2		T68	1		T157	1
all_values[4]	auto[0]	auto[0]	7035700	1			T4	971		T1	2		T5	1
all_values[4]	auto[0]	auto[1]	97	1			T66	2		T67	1		T68	3
all_values[4]	auto[1]	auto[0]	129379	1			T2	2		T3	2		T13	2
all_values[4]	auto[1]	auto[1]	89	1			T66	4		T68	1		T88	1
all_values[5]	auto[0]	auto[0]	7057270	1			T4	971		T1	2		T5	1
all_values[5]	auto[0]	auto[1]	106	1			T66	3		T68	5		T88	1
all_values[5]	auto[1]	auto[0]	107793	1			T2	2		T3	2		T17	2
all_values[5]	auto[1]	auto[1]	96	1			T67	2		T68	1		T88	3
all_values[6]	auto[0]	auto[0]	6389445	1			T4	971		T1	2		T5	1
all_values[6]	auto[0]	auto[1]	32971	1			T6	388		T67	2		T68	2
all_values[6]	auto[1]	auto[0]	739962	1			T13	2		T17	2		T66	2
all_values[6]	auto[1]	auto[1]	2887	1			T66	2		T67	4		T68	1
all_values[7]	auto[0]	auto[0]	6478470	1			T4	971		T5	1		T2	2
all_values[7]	auto[0]	auto[1]	16289	1			T6	287		T67	1		T68	2
all_values[7]	auto[1]	auto[0]	668646	1			T1	2		T9	2		T14	2
all_values[7]	auto[1]	auto[1]	1860	1			T66	3		T67	5		T68	2
all_values[8]	auto[0]	auto[0]	6975321	1			T4	971		T1	2		T5	1
all_values[8]	auto[0]	auto[1]	6520	1			T6	82		T66	3		T68	2
all_values[8]	auto[1]	auto[0]	182982	1			T2	2		T3	2		T14	2
all_values[8]	auto[1]	auto[1]	442	1			T66	2		T67	2		T68	1
all_values[9]	auto[0]	auto[0]	6932874	1			T4	971		T1	2		T5	1
all_values[9]	auto[0]	auto[1]	108	1			T66	1		T67	4		T68	1
all_values[9]	auto[1]	auto[0]	232197	1			T2	2		T9	2		T13	2
all_values[9]	auto[1]	auto[1]	86	1			T66	1		T67	1		T68	3
all_values[10]	auto[0]	auto[0]	7084307	1			T4	971		T1	2		T5	1
all_values[10]	auto[0]	auto[1]	108	1			T66	2		T68	1		T156	3
all_values[10]	auto[1]	auto[0]	80744	1			T3	2		T13	2		T14	2
all_values[10]	auto[1]	auto[1]	106	1			T66	2		T67	1		T68	7
all_values[11]	auto[0]	auto[0]	6505992	1			T4	971		T1	2		T5	1
all_values[11]	auto[0]	auto[1]	321	1			T66	1		T67	1		T68	1
all_values[11]	auto[1]	auto[0]	658852	1			T3	2		T9	2		T13	2
all_values[11]	auto[1]	auto[1]	100	1			T66	3		T67	5		T68	4