Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.10 99.01 96.35 98.63 92.06 98.05 95.86 99.76


Total tests in report: 1791
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
62.22 62.22 92.42 92.42 79.24 79.24 64.58 64.58 26.23 26.23 88.62 88.62 73.26 73.26 11.20 11.20 /workspace/coverage/default/44.spi_device_intercept.4125603867
85.08 22.86 97.99 5.58 91.74 12.50 89.33 24.76 85.25 59.02 96.66 8.04 84.49 11.23 50.07 38.88 /workspace/coverage/default/7.spi_device_stress_all.2665658553
87.96 2.88 98.28 0.28 92.27 0.53 89.33 0.00 91.80 6.56 97.09 0.42 84.64 0.15 62.32 12.24 /workspace/coverage/default/30.spi_device_flash_all.2601943189
89.97 2.01 98.29 0.02 92.48 0.20 91.78 2.45 91.80 0.00 97.12 0.03 94.09 9.45 64.22 1.91 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1279510558
91.27 1.30 98.70 0.40 92.84 0.37 93.93 2.15 91.80 0.00 97.12 0.00 94.09 0.00 70.37 6.15 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2008910139
92.49 1.23 98.73 0.03 92.92 0.08 93.93 0.00 91.80 0.00 97.19 0.07 94.09 0.00 78.80 8.43 /workspace/coverage/default/30.spi_device_stress_all.4045566891
93.39 0.89 98.74 0.02 92.95 0.03 93.93 0.00 93.44 1.64 97.22 0.03 94.09 0.00 83.33 4.53 /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.412483827
93.95 0.56 98.75 0.01 92.95 0.00 97.85 3.91 93.44 0.00 97.22 0.00 94.09 0.00 83.33 0.00 /workspace/coverage/default/10.spi_device_ram_cfg.2368618786
94.30 0.35 98.99 0.23 93.81 0.86 98.04 0.20 93.44 0.00 97.75 0.52 94.68 0.59 83.37 0.05 /workspace/coverage/default/41.spi_device_read_buffer_direct.2433283491
94.64 0.34 98.99 0.00 93.81 0.00 98.04 0.00 93.44 0.00 97.75 0.00 94.68 0.00 85.76 2.38 /workspace/coverage/default/4.spi_device_flash_and_tpm.2791830397
94.94 0.31 99.01 0.02 94.29 0.48 98.24 0.20 93.44 0.00 97.76 0.02 94.68 0.00 87.18 1.43 /workspace/coverage/default/20.spi_device_stress_all.1627061296
95.21 0.27 99.01 0.00 94.29 0.00 98.24 0.00 93.44 0.00 97.76 0.00 94.68 0.00 89.04 1.86 /workspace/coverage/default/43.spi_device_flash_and_tpm.4092649759
95.47 0.26 99.04 0.04 94.37 0.08 98.24 0.00 95.08 1.64 97.82 0.05 94.68 0.00 89.09 0.05 /workspace/coverage/default/0.spi_device_rx_timeout.701415235
95.70 0.23 99.04 0.00 95.05 0.69 98.24 0.00 95.08 0.00 97.88 0.07 94.68 0.00 89.95 0.86 /workspace/coverage/default/34.spi_device_stress_all.1125155524
95.92 0.22 99.04 0.00 95.84 0.79 98.24 0.00 95.08 0.00 97.90 0.02 94.83 0.15 90.52 0.57 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3668416576
96.12 0.20 99.04 0.00 95.84 0.00 98.24 0.00 95.08 0.00 97.90 0.00 94.83 0.00 91.90 1.38 /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2725846467
96.27 0.15 99.05 0.01 95.84 0.00 98.24 0.00 95.08 0.00 97.92 0.02 94.83 0.00 92.95 1.05 /workspace/coverage/default/16.spi_device_stress_all.2022010999
96.41 0.13 99.08 0.03 95.85 0.01 98.24 0.00 95.08 0.00 97.92 0.00 95.72 0.89 92.95 0.00 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2109885147
96.52 0.12 99.08 0.00 95.85 0.00 98.24 0.00 95.08 0.00 97.92 0.00 95.72 0.00 93.76 0.81 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2348787328
96.62 0.10 99.08 0.00 95.85 0.00 98.24 0.00 95.08 0.00 97.92 0.00 95.72 0.00 94.47 0.71 /workspace/coverage/default/31.spi_device_stress_all.1858322402
96.72 0.09 99.08 0.00 95.88 0.03 98.63 0.39 95.08 0.00 97.92 0.00 95.86 0.15 94.57 0.10 /workspace/coverage/default/1.spi_device_sec_cm.3879475640
96.79 0.07 99.08 0.00 95.88 0.00 98.63 0.00 95.08 0.00 97.92 0.00 95.86 0.00 95.05 0.48 /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1530506169
96.85 0.07 99.10 0.02 95.93 0.05 98.63 0.00 95.08 0.00 97.93 0.02 95.86 0.00 95.43 0.38 /workspace/coverage/default/30.spi_device_bit_transfer.484093887
96.91 0.06 99.10 0.00 95.93 0.00 98.63 0.00 95.08 0.00 97.93 0.00 95.86 0.00 95.86 0.43 /workspace/coverage/default/23.spi_device_flash_and_tpm.1202590026
96.96 0.05 99.10 0.00 96.00 0.08 98.63 0.00 95.08 0.00 97.93 0.00 95.86 0.00 96.14 0.29 /workspace/coverage/default/41.spi_device_stress_all.2447936147
97.01 0.05 99.10 0.00 96.00 0.00 98.63 0.00 95.08 0.00 97.93 0.00 95.86 0.00 96.47 0.33 /workspace/coverage/default/17.spi_device_flash_mode.2176632216
97.06 0.05 99.10 0.00 96.00 0.00 98.63 0.00 95.08 0.00 97.93 0.00 95.86 0.00 96.81 0.33 /workspace/coverage/default/5.spi_device_flash_and_tpm.2214323424
97.09 0.03 99.10 0.00 96.00 0.00 98.63 0.00 95.08 0.00 97.93 0.00 95.86 0.00 97.05 0.24 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2765122897
97.13 0.03 99.10 0.00 96.00 0.00 98.63 0.00 95.08 0.00 97.93 0.00 95.86 0.00 97.28 0.24 /workspace/coverage/default/12.spi_device_flash_all.4254114365
97.16 0.03 99.10 0.00 96.00 0.00 98.63 0.00 95.08 0.00 97.93 0.00 95.86 0.00 97.52 0.24 /workspace/coverage/default/7.spi_device_flash_all.994123273
97.20 0.03 99.16 0.06 96.09 0.09 98.63 0.00 95.08 0.00 98.02 0.08 95.86 0.00 97.52 0.00 /workspace/coverage/default/0.spi_device_mem_parity.1316317022
97.22 0.03 99.16 0.00 96.09 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 97.71 0.19 /workspace/coverage/default/25.spi_device_stress_all.4034155570
97.25 0.03 99.16 0.00 96.09 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 97.90 0.19 /workspace/coverage/default/49.spi_device_stress_all.1890029492
97.27 0.02 99.16 0.00 96.24 0.15 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 97.90 0.00 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1935349442
97.29 0.02 99.16 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.05 0.14 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4038011387
97.31 0.02 99.16 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.19 0.14 /workspace/coverage/default/0.spi_device_extreme_fifo_size.2062515622
97.33 0.02 99.16 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.33 0.14 /workspace/coverage/default/34.spi_device_flash_all.1182737048
97.35 0.02 99.16 0.00 96.26 0.01 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.43 0.10 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1610820716
97.36 0.01 99.16 0.00 96.26 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.52 0.10 /workspace/coverage/default/1.spi_device_flash_and_tpm.2772157837
97.38 0.01 99.16 0.00 96.26 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.62 0.10 /workspace/coverage/default/1.spi_device_stress_all.1262533897
97.39 0.01 99.16 0.00 96.26 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.71 0.10 /workspace/coverage/default/11.spi_device_stress_all.1774247418
97.40 0.01 99.16 0.00 96.26 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.81 0.10 /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2192589653
97.42 0.01 99.16 0.00 96.26 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.90 0.10 /workspace/coverage/default/2.spi_device_fifo_underflow_overflow.2999589667
97.43 0.01 99.16 0.00 96.26 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.00 0.10 /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2210212651
97.44 0.01 99.16 0.00 96.26 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.09 0.10 /workspace/coverage/default/38.spi_device_flash_mode.1313039884
97.46 0.01 99.16 0.00 96.26 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.19 0.10 /workspace/coverage/default/45.spi_device_flash_all.4055318614
97.47 0.01 99.16 0.00 96.26 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.29 0.10 /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3533123495
97.48 0.01 99.17 0.01 96.26 0.00 98.63 0.00 95.08 0.00 98.04 0.02 95.86 0.00 99.33 0.05 /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2341196010
97.49 0.01 99.17 0.00 96.27 0.01 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.38 0.05 /workspace/coverage/default/22.spi_device_fifo_underflow_overflow.2869177605
97.50 0.01 99.17 0.00 96.27 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.43 0.05 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3564057931
97.50 0.01 99.17 0.00 96.27 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.48 0.05 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.309823752
97.51 0.01 99.17 0.00 96.27 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.52 0.05 /workspace/coverage/default/12.spi_device_dummy_item_extra_dly.2120249700
97.52 0.01 99.17 0.00 96.27 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.57 0.05 /workspace/coverage/default/12.spi_device_flash_and_tpm.207226732
97.52 0.01 99.17 0.00 96.27 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.62 0.05 /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.840851834
97.53 0.01 99.17 0.00 96.27 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.67 0.05 /workspace/coverage/default/21.spi_device_intercept.3386151488
97.54 0.01 99.17 0.00 96.27 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.71 0.05 /workspace/coverage/default/28.spi_device_flash_and_tpm.881046196
97.54 0.01 99.17 0.00 96.27 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.76 0.05 /workspace/coverage/default/3.spi_device_intr.1057581536
97.55 0.01 99.18 0.01 96.27 0.00 98.63 0.00 95.08 0.00 98.05 0.02 95.86 0.00 99.76 0.00 /workspace/coverage/default/25.spi_device_abort.378835574
97.55 0.01 99.18 0.00 96.30 0.03 98.63 0.00 95.08 0.00 98.05 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/default/10.spi_device_alert_test.249474167
97.55 0.01 99.18 0.00 96.31 0.01 98.63 0.00 95.08 0.00 98.05 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2443995470
97.56 0.01 99.18 0.00 96.32 0.01 98.63 0.00 95.08 0.00 98.05 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/default/10.spi_device_rx_async_fifo_reset.1600426701
97.56 0.01 99.18 0.00 96.33 0.01 98.63 0.00 95.08 0.00 98.05 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/default/13.spi_device_tx_async_fifo_reset.4149256541
97.56 0.01 99.18 0.00 96.35 0.01 98.63 0.00 95.08 0.00 98.05 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2642931566

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2885763582
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.196423160
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.905518853
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4104994074
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1828547328
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.3472827875
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1750554705
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2053121636
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.474651928
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4057022915
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3022120568
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.787136393
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2812694176
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2488935764
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2751755661
/workspace/coverage/cover_reg_top/1.spi_device_intr_test.2423004565
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2193329546
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3323989316
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1033344863
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.608691507
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1430242372
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.3684579798
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.505946456
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2562207420
/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3412952465
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4042528284
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1030357429
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.4009563275
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3457997878
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2430930950
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3265116773
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3456207547
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.453843645
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.1484624090
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3488119035
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2415296199
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3014653773
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2353080336
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3928454498
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.3311482244
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1181346221
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4070033430
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2447828497
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1869132783
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.2055469067
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1347378678
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2819522424
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1391971627
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.882546948
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.1872101028
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2104211580
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1743777807
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3423241188
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.439332794
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2133939047
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.790955350
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.669603791
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.27374306
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4206425535
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2591938625
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.606302580
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.843805000
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2290269035
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3104050827
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.524743768
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1851368638
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2771265718
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.2433190872
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2776394928
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1964663494
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4286465273
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3364895558
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.660413256
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.15541751
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1878860322
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3519024440
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1158154058
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.992675833
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.401519899
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2515405204
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.395127404
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2634405651
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2286328156
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2581336780
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.240137054
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.1528251256
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.1976477955
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.3389557984
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.3420165383
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.3779966235
/workspace/coverage/cover_reg_top/26.spi_device_intr_test.1441088991
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.1135059383
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.3145194021
/workspace/coverage/cover_reg_top/29.spi_device_intr_test.960678244
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1296598494
/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1380212347
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1209193527
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1493149352
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2662099996
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.1459627362
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4256108349
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2080476587
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/workspace/coverage/default/6.spi_device_tpm_read_hw_reg.829476555
/workspace/coverage/default/6.spi_device_tpm_rw.94827182
/workspace/coverage/default/6.spi_device_tpm_sts_read.2008643737
/workspace/coverage/default/6.spi_device_tx_async_fifo_reset.320075389
/workspace/coverage/default/6.spi_device_txrx.2381864350
/workspace/coverage/default/6.spi_device_upload.1042995459
/workspace/coverage/default/7.spi_device_abort.3817749705
/workspace/coverage/default/7.spi_device_alert_test.2171994988
/workspace/coverage/default/7.spi_device_bit_transfer.3256686609
/workspace/coverage/default/7.spi_device_byte_transfer.390205493
/workspace/coverage/default/7.spi_device_cfg_cmd.130572008
/workspace/coverage/default/7.spi_device_csb_read.1519903837
/workspace/coverage/default/7.spi_device_dummy_item_extra_dly.1178157463
/workspace/coverage/default/7.spi_device_extreme_fifo_size.522056507
/workspace/coverage/default/7.spi_device_fifo_underflow_overflow.315407406
/workspace/coverage/default/7.spi_device_flash_and_tpm.2751731830
/workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1781069232
/workspace/coverage/default/7.spi_device_flash_mode.3657928316
/workspace/coverage/default/7.spi_device_intercept.312544635
/workspace/coverage/default/7.spi_device_intr.704204040
/workspace/coverage/default/7.spi_device_mailbox.560658312
/workspace/coverage/default/7.spi_device_mem_parity.1607916139
/workspace/coverage/default/7.spi_device_pass_addr_payload_swap.518333159
/workspace/coverage/default/7.spi_device_pass_cmd_filtering.340271366
/workspace/coverage/default/7.spi_device_perf.3792604555
/workspace/coverage/default/7.spi_device_ram_cfg.473890864
/workspace/coverage/default/7.spi_device_read_buffer_direct.2380109672
/workspace/coverage/default/7.spi_device_rx_async_fifo_reset.1875050644
/workspace/coverage/default/7.spi_device_rx_timeout.4053823333
/workspace/coverage/default/7.spi_device_smoke.3094904797
/workspace/coverage/default/7.spi_device_tpm_all.3736967898
/workspace/coverage/default/7.spi_device_tpm_read_hw_reg.184768146
/workspace/coverage/default/7.spi_device_tpm_rw.1452020413
/workspace/coverage/default/7.spi_device_tpm_sts_read.1301378117
/workspace/coverage/default/7.spi_device_tx_async_fifo_reset.3285612073
/workspace/coverage/default/7.spi_device_txrx.107997206
/workspace/coverage/default/7.spi_device_upload.300474565
/workspace/coverage/default/8.spi_device_abort.61584094
/workspace/coverage/default/8.spi_device_alert_test.552380524
/workspace/coverage/default/8.spi_device_bit_transfer.2788441767
/workspace/coverage/default/8.spi_device_byte_transfer.1957826458
/workspace/coverage/default/8.spi_device_cfg_cmd.3210800706
/workspace/coverage/default/8.spi_device_csb_read.4102890424
/workspace/coverage/default/8.spi_device_dummy_item_extra_dly.607043990
/workspace/coverage/default/8.spi_device_extreme_fifo_size.3539632481
/workspace/coverage/default/8.spi_device_fifo_full.4070241867
/workspace/coverage/default/8.spi_device_fifo_underflow_overflow.1061272993
/workspace/coverage/default/8.spi_device_flash_all.2893051162
/workspace/coverage/default/8.spi_device_flash_and_tpm.1331329121
/workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1707939069
/workspace/coverage/default/8.spi_device_flash_mode.3222508916
/workspace/coverage/default/8.spi_device_intercept.1034460863
/workspace/coverage/default/8.spi_device_intr.984926729
/workspace/coverage/default/8.spi_device_mailbox.685330040
/workspace/coverage/default/8.spi_device_mem_parity.3086066159
/workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1290058551
/workspace/coverage/default/8.spi_device_pass_cmd_filtering.1640305668
/workspace/coverage/default/8.spi_device_perf.554312194
/workspace/coverage/default/8.spi_device_ram_cfg.1913227747
/workspace/coverage/default/8.spi_device_read_buffer_direct.3424973308
/workspace/coverage/default/8.spi_device_rx_async_fifo_reset.167859695
/workspace/coverage/default/8.spi_device_rx_timeout.3913532251
/workspace/coverage/default/8.spi_device_smoke.1492452293
/workspace/coverage/default/8.spi_device_stress_all.952890185
/workspace/coverage/default/8.spi_device_tpm_all.4139532685
/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1036574209
/workspace/coverage/default/8.spi_device_tpm_rw.3280859746
/workspace/coverage/default/8.spi_device_tpm_sts_read.1784811123
/workspace/coverage/default/8.spi_device_tx_async_fifo_reset.663412021
/workspace/coverage/default/8.spi_device_txrx.2782050580
/workspace/coverage/default/8.spi_device_upload.2240193316
/workspace/coverage/default/9.spi_device_abort.927578770
/workspace/coverage/default/9.spi_device_alert_test.1963974958
/workspace/coverage/default/9.spi_device_bit_transfer.1577987526
/workspace/coverage/default/9.spi_device_byte_transfer.407556626
/workspace/coverage/default/9.spi_device_cfg_cmd.784994622
/workspace/coverage/default/9.spi_device_csb_read.1507914614
/workspace/coverage/default/9.spi_device_dummy_item_extra_dly.1510283746
/workspace/coverage/default/9.spi_device_extreme_fifo_size.3645240646
/workspace/coverage/default/9.spi_device_fifo_full.2388043071
/workspace/coverage/default/9.spi_device_fifo_underflow_overflow.1226993704
/workspace/coverage/default/9.spi_device_flash_all.3538634557
/workspace/coverage/default/9.spi_device_flash_and_tpm.2250782957
/workspace/coverage/default/9.spi_device_flash_mode.216580822
/workspace/coverage/default/9.spi_device_intercept.2635789578
/workspace/coverage/default/9.spi_device_intr.3606670513
/workspace/coverage/default/9.spi_device_mailbox.3131292403
/workspace/coverage/default/9.spi_device_mem_parity.764712797
/workspace/coverage/default/9.spi_device_pass_addr_payload_swap.28403318
/workspace/coverage/default/9.spi_device_pass_cmd_filtering.4286902864
/workspace/coverage/default/9.spi_device_perf.476633105
/workspace/coverage/default/9.spi_device_ram_cfg.3096012979
/workspace/coverage/default/9.spi_device_read_buffer_direct.1122232785
/workspace/coverage/default/9.spi_device_rx_async_fifo_reset.3787279567
/workspace/coverage/default/9.spi_device_rx_timeout.1220729724
/workspace/coverage/default/9.spi_device_smoke.1552549549
/workspace/coverage/default/9.spi_device_stress_all.3345984220
/workspace/coverage/default/9.spi_device_tpm_all.1316764272
/workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1835277570
/workspace/coverage/default/9.spi_device_tpm_rw.1377095638
/workspace/coverage/default/9.spi_device_tpm_sts_read.99656784
/workspace/coverage/default/9.spi_device_tx_async_fifo_reset.1740106290
/workspace/coverage/default/9.spi_device_txrx.2792108969
/workspace/coverage/default/9.spi_device_upload.2294365161



Total test records in report: 1791
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspace/coverage/default/14.spi_device_tpm_all.3209639125 Dec 24 01:55:15 PM PST 23 Dec 24 01:55:46 PM PST 23 7041056597 ps
T1 /workspace/coverage/default/41.spi_device_abort.24453637 Dec 24 01:57:35 PM PST 23 Dec 24 01:57:39 PM PST 23 15416415 ps
T5 /workspace/coverage/default/37.spi_device_tpm_sts_read.3504341441 Dec 24 01:57:13 PM PST 23 Dec 24 01:57:22 PM PST 23 506436109 ps
T2 /workspace/coverage/default/27.spi_device_fifo_full.1957471901 Dec 24 01:56:07 PM PST 23 Dec 24 02:07:15 PM PST 23 50866191311 ps
T3 /workspace/coverage/default/0.spi_device_perf.947417103 Dec 24 01:53:19 PM PST 23 Dec 24 01:56:27 PM PST 23 5700468144 ps
T9 /workspace/coverage/default/24.spi_device_fifo_full.3159524985 Dec 24 01:56:06 PM PST 23 Dec 24 02:08:40 PM PST 23 86404653135 ps
T39 /workspace/coverage/default/14.spi_device_ram_cfg.2504307180 Dec 24 01:55:14 PM PST 23 Dec 24 01:55:16 PM PST 23 16233589 ps
T16 /workspace/coverage/default/39.spi_device_tpm_all.2750561363 Dec 24 01:57:23 PM PST 23 Dec 24 01:58:13 PM PST 23 5566930999 ps
T12 /workspace/coverage/default/44.spi_device_intercept.4125603867 Dec 24 01:57:50 PM PST 23 Dec 24 01:57:59 PM PST 23 2329004048 ps
T13 /workspace/coverage/default/30.spi_device_bit_transfer.484093887 Dec 24 01:56:44 PM PST 23 Dec 24 01:56:53 PM PST 23 655736234 ps
T10 /workspace/coverage/default/41.spi_device_read_buffer_direct.2433283491 Dec 24 01:57:34 PM PST 23 Dec 24 01:57:40 PM PST 23 893643878 ps
T40 /workspace/coverage/default/36.spi_device_csb_read.249966086 Dec 24 01:56:58 PM PST 23 Dec 24 01:57:11 PM PST 23 46191375 ps
T41 /workspace/coverage/default/28.spi_device_csb_read.119942718 Dec 24 01:56:05 PM PST 23 Dec 24 01:56:09 PM PST 23 26579778 ps
T14 /workspace/coverage/default/27.spi_device_tx_async_fifo_reset.3781737884 Dec 24 01:56:09 PM PST 23 Dec 24 01:56:16 PM PST 23 16678044 ps
T17 /workspace/coverage/default/47.spi_device_abort.2196439581 Dec 24 01:58:19 PM PST 23 Dec 24 01:58:22 PM PST 23 16461849 ps
T6 /workspace/coverage/default/7.spi_device_stress_all.2665658553 Dec 24 01:54:21 PM PST 23 Dec 24 02:06:19 PM PST 23 227818118126 ps
T66 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3311482244 Dec 24 12:31:59 PM PST 23 Dec 24 12:32:26 PM PST 23 15025094 ps
T83 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2469612119 Dec 24 12:32:15 PM PST 23 Dec 24 12:32:42 PM PST 23 363887638 ps
T69 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.474651928 Dec 24 12:31:43 PM PST 23 Dec 24 12:32:12 PM PST 23 124917493 ps
T70 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2109885147 Dec 24 12:32:42 PM PST 23 Dec 24 12:33:10 PM PST 23 36990367 ps
T71 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1684561356 Dec 24 12:32:00 PM PST 23 Dec 24 12:32:27 PM PST 23 68415644 ps
T67 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1184147777 Dec 24 12:32:14 PM PST 23 Dec 24 12:32:40 PM PST 23 50343069 ps
T154 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2193329546 Dec 24 12:31:59 PM PST 23 Dec 24 12:32:32 PM PST 23 930081398 ps
T68 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2008910139 Dec 24 12:32:48 PM PST 23 Dec 24 12:33:16 PM PST 23 29188846 ps
T88 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.660413256 Dec 24 12:32:53 PM PST 23 Dec 24 12:33:31 PM PST 23 11887175 ps
T156 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.95154353 Dec 24 12:32:20 PM PST 23 Dec 24 12:32:47 PM PST 23 53579001 ps
T87 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3015398648 Dec 24 12:32:38 PM PST 23 Dec 24 12:33:04 PM PST 23 22703470 ps
T157 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1891872308 Dec 24 12:32:00 PM PST 23 Dec 24 12:32:26 PM PST 23 43072938 ps
T81 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3564057931 Dec 24 12:32:01 PM PST 23 Dec 24 12:32:29 PM PST 23 67744144 ps
T155 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2634405651 Dec 24 12:31:52 PM PST 23 Dec 24 12:32:26 PM PST 23 825210060 ps
T82 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1404344811 Dec 24 12:32:13 PM PST 23 Dec 24 12:32:42 PM PST 23 118102741 ps
T180 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2348787328 Dec 24 12:32:39 PM PST 23 Dec 24 12:33:05 PM PST 23 17104464 ps
T181 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3120196474 Dec 24 12:32:49 PM PST 23 Dec 24 12:33:18 PM PST 23 41707539 ps
T84 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3668416576 Dec 24 12:32:40 PM PST 23 Dec 24 12:33:12 PM PST 23 66441318 ps
T146 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4038011387 Dec 24 12:32:40 PM PST 23 Dec 24 12:33:06 PM PST 23 34888630 ps
T147 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3579094054 Dec 24 12:32:12 PM PST 23 Dec 24 12:32:38 PM PST 23 37938148 ps
T148 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1142492498 Dec 24 12:32:22 PM PST 23 Dec 24 12:32:49 PM PST 23 98612962 ps
T149 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.835388187 Dec 24 12:33:07 PM PST 23 Dec 24 12:33:49 PM PST 23 15445259 ps
T150 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2064286729 Dec 24 12:32:32 PM PST 23 Dec 24 12:33:00 PM PST 23 57354508 ps
T115 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2415296199 Dec 24 12:32:29 PM PST 23 Dec 24 12:33:11 PM PST 23 97095193 ps
T360 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.787136393 Dec 24 12:31:55 PM PST 23 Dec 24 12:32:36 PM PST 23 2680013072 ps
T85 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.688766913 Dec 24 12:32:05 PM PST 23 Dec 24 12:32:34 PM PST 23 155642956 ps
T86 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1189864850 Dec 24 12:32:02 PM PST 23 Dec 24 12:32:37 PM PST 23 31942516 ps
T185 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2415067488 Dec 24 12:32:39 PM PST 23 Dec 24 12:33:06 PM PST 23 17442873 ps
T168 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3273184500 Dec 24 12:32:22 PM PST 23 Dec 24 12:32:51 PM PST 23 762818449 ps
T117 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1279510558 Dec 24 12:32:13 PM PST 23 Dec 24 12:33:00 PM PST 23 1000368626 ps
T151 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.196423160 Dec 24 12:32:27 PM PST 23 Dec 24 12:33:32 PM PST 23 9080420665 ps
T186 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2433190872 Dec 24 12:32:44 PM PST 23 Dec 24 12:33:13 PM PST 23 43910748 ps
T179 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1851368638 Dec 24 12:32:36 PM PST 23 Dec 24 12:33:11 PM PST 23 69824104 ps
T158 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3810964689 Dec 24 12:32:01 PM PST 23 Dec 24 12:32:28 PM PST 23 29082967 ps
T121 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2305280700 Dec 24 12:32:26 PM PST 23 Dec 24 12:32:57 PM PST 23 150732727 ps
T153 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.193516832 Dec 24 12:32:43 PM PST 23 Dec 24 12:33:12 PM PST 23 13194237 ps
T188 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1441088991 Dec 24 12:32:34 PM PST 23 Dec 24 12:33:00 PM PST 23 13250234 ps
T159 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1750554705 Dec 24 12:31:40 PM PST 23 Dec 24 12:32:12 PM PST 23 234632519 ps
T361 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2448459192 Dec 24 12:32:27 PM PST 23 Dec 24 12:32:54 PM PST 23 33106203 ps
T118 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1610820716 Dec 24 12:31:51 PM PST 23 Dec 24 12:32:41 PM PST 23 3003695894 ps
T362 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2080476587 Dec 24 12:31:50 PM PST 23 Dec 24 12:32:33 PM PST 23 2840944009 ps
T160 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3769083934 Dec 24 12:32:44 PM PST 23 Dec 24 12:33:15 PM PST 23 101510018 ps
T363 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3917172850 Dec 24 12:32:14 PM PST 23 Dec 24 12:32:41 PM PST 23 171617878 ps
T161 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3022120568 Dec 24 12:32:42 PM PST 23 Dec 24 12:33:28 PM PST 23 894538178 ps
T125 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4057022915 Dec 24 12:31:52 PM PST 23 Dec 24 12:32:23 PM PST 23 591600483 ps
T123 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.927551116 Dec 24 12:32:08 PM PST 23 Dec 24 12:32:36 PM PST 23 27749549 ps
T364 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.505946456 Dec 24 12:32:04 PM PST 23 Dec 24 12:32:35 PM PST 23 334957738 ps
T365 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1135059383 Dec 24 12:32:29 PM PST 23 Dec 24 12:32:56 PM PST 23 22490718 ps
T366 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1135232107 Dec 24 12:32:24 PM PST 23 Dec 24 12:32:54 PM PST 23 240705930 ps
T119 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4070033430 Dec 24 12:32:29 PM PST 23 Dec 24 12:33:11 PM PST 23 1182410392 ps
T182 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.882546948 Dec 24 12:32:50 PM PST 23 Dec 24 12:33:24 PM PST 23 84544699 ps
T162 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2662099996 Dec 24 12:32:04 PM PST 23 Dec 24 12:32:32 PM PST 23 41857922 ps
T367 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1599959767 Dec 24 12:32:35 PM PST 23 Dec 24 12:33:09 PM PST 23 138667433 ps
T145 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.608691507 Dec 24 12:32:03 PM PST 23 Dec 24 12:32:37 PM PST 23 580476992 ps
T368 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4042528284 Dec 24 12:32:15 PM PST 23 Dec 24 12:32:42 PM PST 23 130022022 ps
T369 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3323989316 Dec 24 12:31:58 PM PST 23 Dec 24 12:32:38 PM PST 23 3555623863 ps
T370 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1872101028 Dec 24 12:32:56 PM PST 23 Dec 24 12:33:38 PM PST 23 86554404 ps
T371 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.457717766 Dec 24 12:32:45 PM PST 23 Dec 24 12:33:13 PM PST 23 30121365 ps
T152 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3412952465 Dec 24 12:32:18 PM PST 23 Dec 24 12:33:03 PM PST 23 5988828261 ps
T372 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2025799780 Dec 24 12:32:58 PM PST 23 Dec 24 12:33:41 PM PST 23 24198775 ps
T163 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.606302580 Dec 24 12:32:37 PM PST 23 Dec 24 12:33:05 PM PST 23 350978694 ps
T120 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2886019434 Dec 24 12:32:23 PM PST 23 Dec 24 12:32:53 PM PST 23 110807687 ps
T199 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4206425535 Dec 24 12:32:28 PM PST 23 Dec 24 12:33:07 PM PST 23 198714494 ps
T373 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4009563275 Dec 24 12:31:56 PM PST 23 Dec 24 12:32:25 PM PST 23 47432219 ps
T374 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4156351087 Dec 24 12:32:40 PM PST 23 Dec 24 12:33:08 PM PST 23 17544289 ps
T375 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1391971627 Dec 24 12:33:01 PM PST 23 Dec 24 12:33:44 PM PST 23 26055321 ps
T376 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3770566968 Dec 24 12:32:09 PM PST 23 Dec 24 12:32:37 PM PST 23 27147597 ps
T164 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3512187298 Dec 24 12:32:38 PM PST 23 Dec 24 12:33:06 PM PST 23 215378505 ps
T377 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3779966235 Dec 24 12:32:26 PM PST 23 Dec 24 12:32:53 PM PST 23 75018010 ps
T378 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1528251256 Dec 24 12:32:33 PM PST 23 Dec 24 12:33:09 PM PST 23 24363219 ps
T379 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2616839355 Dec 24 12:32:15 PM PST 23 Dec 24 12:32:41 PM PST 23 14295834 ps
T165 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2133939047 Dec 24 12:32:29 PM PST 23 Dec 24 12:32:57 PM PST 23 22031821 ps
T380 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2053121636 Dec 24 12:31:43 PM PST 23 Dec 24 12:32:15 PM PST 23 229812902 ps
T122 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1935349442 Dec 24 12:32:12 PM PST 23 Dec 24 12:32:42 PM PST 23 141127510 ps
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T427 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.845706011 Dec 24 12:32:25 PM PST 23 Dec 24 12:32:52 PM PST 23 21104537 ps
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T429 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.453843645 Dec 24 12:32:44 PM PST 23 Dec 24 12:33:13 PM PST 23 42221173 ps
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T433 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1976477955 Dec 24 12:33:08 PM PST 23 Dec 24 12:33:49 PM PST 23 17646960 ps
T434 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1828547328 Dec 24 12:31:38 PM PST 23 Dec 24 12:32:05 PM PST 23 63658888 ps
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T438 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2515405204 Dec 24 12:32:05 PM PST 23 Dec 24 12:32:33 PM PST 23 112056169 ps
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T59 /workspace/coverage/default/4.spi_device_dummy_item_extra_dly.1784601692 Dec 24 01:54:11 PM PST 23 Dec 24 02:23:22 PM PST 23 87176058683 ps
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T265 /workspace/coverage/default/35.spi_device_cfg_cmd.3932362508 Dec 24 01:56:57 PM PST 23 Dec 24 01:57:10 PM PST 23 568352199 ps
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