Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

Group : spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	16	0	16	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_bit_order	2	0	2	100.00	100	1	1	2
cp_cpha	2	0	2	100.00	100	1	1	2
cp_cpol	2	0	2	100.00	100	1	1	2
cp_rx_order	2	0	2	100.00	100	1	1	2
rx_order	2	0	2	100.00	100	1	1	2
tx_order	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_bit_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_bit_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3422987

1

T2

5866

T9

13556

T13

23

auto[1]

2813081

1

T2

6655

T3

8215

T9

6741

---

Summary for Variable cp_cpha

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cpha

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2972548

1

T3

8215

T13

31

T14

1

auto[1]

3263520

1

T2

12521

T9

20297

T13

49

---

Summary for Variable cp_cpol

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cpol

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2920909

1

T2

5866

T9

6741

T13

21

auto[1]

3315159

1

T2

6655

T3

8215

T9

13556

---

Summary for Variable cp_rx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3036769

1

T9

13467

T13

21

T14

1

auto[1]

3199299

1

T2

12521

T3

8215

T9

6830

---

Summary for Variable rx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3036769

1

T9

13467

T13

21

T14

1

auto[1]

3199299

1

T2

12521

T3

8215

T9

6830

---

Summary for Variable tx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for tx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3422987

1

T2

5866

T9

13556

T13

23

auto[1]

2813081

1

T2

6655

T3

8215

T9

6741

---

Summary for Cross cr_all

Samples crossed: tx_order rx_order cp_cpol cp_cpha

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

tx_order

rx_order

cp_cpol

cp_cpha

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

413172

1

T13

4

T74

1

T139

8504

auto[0]

auto[0]

auto[0]

auto[1]

395895

1

T38

5418

T49

7

T127

8564

auto[0]

auto[0]

auto[1]

auto[0]

439923

1

T13

5

T14

1

T49

23

auto[0]

auto[0]

auto[1]

auto[1]

481475

1

T9

6726

T15

83591

T138

6878

auto[0]

auto[1]

auto[0]

auto[0]

360797

1

T127

4468

T206

1502

T207

8216

auto[0]

auto[1]

auto[0]

auto[1]

331356

1

T2

5866

T13

2

T49

7

auto[0]

auto[1]

auto[1]

auto[0]

479496

1

T38

5548

T49

15

T129

1426

auto[0]

auto[1]

auto[1]

auto[1]

520873

1

T9

6830

T13

12

T15

80142

auto[1]

auto[0]

auto[0]

auto[0]

259060

1

T6

540

T37

3859

T49

4

auto[1]

auto[0]

auto[0]

auto[1]

348285

1

T9

6741

T13

2

T49

4

auto[1]

auto[0]

auto[1]

auto[0]

372741

1

T13

3

T36

74

T49

3

auto[1]

auto[0]

auto[1]

auto[1]

326218

1

T13

7

T49

7

T129

997

auto[1]

auto[1]

auto[0]

auto[0]

358555

1

T13

7

T37

3007

T127

12273

auto[1]

auto[1]

auto[0]

auto[1]

453789

1

T13

6

T49

7

T8

23723

auto[1]

auto[1]

auto[1]

auto[0]

288804

1

T3

8215

T13

12

T49

8

auto[1]

auto[1]

auto[1]

auto[1]

405629

1

T2

6655

T13

20

T6

1289