Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	37180	1			T12	4		T6	136		T11	8
auto[SpiFlashAddrCfg]	8035	1			T6	37		T11	2		T19	8
auto[SpiFlashAddr3b]	9378	1			T12	10		T6	48		T11	14
auto[SpiFlashAddr4b]	7993	1			T12	2		T6	34		T11	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35115

1

T12

16

T6

133

T18

10

auto[1]

27471

1

T6

122

T11

28

T7

127

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33570

1

T12

6

T6

135

T11

12

auto[1]

29016

1

T12

10

T6

120

T11

16

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	42105	1			T12	12		T6	159		T11	14
values[1]	1053	1			T6	5		T7	3		T8	1
values[2]	1455	1			T6	7		T7	15		T24	4
values[3]	1549	1			T6	13		T11	4		T7	6
values[4]	1559	1			T6	2		T23	4		T8	3
values[5]	1443	1			T12	2		T6	8		T7	5
values[6]	1464	1			T6	7		T11	2		T19	2
values[7]	1521	1			T6	8		T7	11		T23	2
values[8]	10437	1			T12	2		T6	46		T11	8

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34958

1

T12

16

T11

28

T18

10

auto[1]

27628

1

T6

255

T42

234

T43

182

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

60405

1

T12

16

T6

245

T11

26

write

2181

1

T6

10

T11

2

T19

8

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20386

1

T12

2

T6

91

T11

12

valids[0x1]

42200

1

T12

14

T6

164

T11

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1592	1			T12	4		T6	11		T7	5
internal_process_ops[0x5a]	1643	1			T12	8		T6	7		T11	2
internal_process_ops[0x05]	23180	1			T6	63		T7	32		T8	37
internal_process_ops[0x35]	1631	1			T6	11		T11	6		T19	8
internal_process_ops[0x15]	1579	1			T6	9		T7	9		T8	1
internal_process_ops[0x03]	1164	1			T12	2		T6	3		T7	8
internal_process_ops[0x0b]	1222	1			T6	2		T11	6		T7	9
internal_process_ops[0x3b]	1250	1			T6	2		T7	8		T24	4
internal_process_ops[0x6b]	1104	1			T6	5		T11	2		T7	8
internal_process_ops[0xbb]	1170	1			T6	3		T11	2		T7	8
internal_process_ops[0xeb]	1213	1			T12	2		T6	3		T11	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61531

1

T12

16

T6

254

T11

26

auto[1]

1055

1

T6

1

T11

2

T7

7

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60503

1

T12

16

T6

244

T11

28

auto[1]

2083

1

T6

11

T7

8

T8

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11554

1

T12

4

T18

10

T7

59

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8275

1

T11

6

T7

42

T8

40

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2407

1

T7

12

T24

12

T8

5

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2007

1

T11

2

T7

33

T8

9

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2860

1

T12

10

T19

2

T7

28

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2327

1

T11

14

T7

19

T8

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2312

1

T12

2

T7

13

T8

5

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2052

1

T11

4

T7

26

T8

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

89

1

T7

1

T21

1

T30

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

71

1

T20

2

T21

2

T28

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

62

1

T21

1

T29

1

T32

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

90

1

T11

2

T7

2

T8

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

140

1

T19

8

T7

1

T21

5

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

74

1

T7

2

T20

3

T21

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

53

1

T8

3

T21

1

T30

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

67

1

T7

2

T20

2

T30

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

75

1

T27

1

T32

1

T197

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

71

1

T8

3

T20

1

T21

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

39

1

T30

2

T31

1

T32

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

63

1

T7

1

T27

3

T30

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

87

1

T21

1

T27

2

T29

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

64

1

T27

1

T29

4

T31

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

59

1

T7

2

T27

3

T29

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

60

1

T30

5

T32

2

T62

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9609

1

T6

79

T42

72

T43

45

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7182

1

T6

56

T42

41

T43

54

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1602

1

T6

11

T42

10

T43

10

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1429

1

T6

24

T42

18

T43

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1900

1

T6

20

T42

25

T43

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1777

1

T6

25

T42

25

T43

18

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1687

1

T6

22

T42

21

T43

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1425

1

T6

8

T42

10

T43

11

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

76

1

T6

1

T110

1

T48

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

57

1

T42

4

T63

2

T60

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

54

1

T42

2

T43

1

T48

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

61

1

T28

2

T63

1

T128

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

54

1

T48

2

T60

1

T61

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

66

1

T48

1

T63

4

T61

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

79

1

T6

2

T42

3

T43

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

57

1

T28

1

T128

3

T62

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

73

1

T110

1

T60

2

T61

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

57

1

T43

3

T48

4

T63

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

55

1

T6

3

T43

1

T48

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

81

1

T110

1

T28

1

T63

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

71

1

T42

1

T110

1

T48

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

59

1

T63

2

T61

4

T62

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

60

1

T6

3

T42

2

T60

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

57

1

T6

1

T43

2

T28

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4386	1			T18	10		T7	39		T8	7
auto[0]	values[0]	valids[0x1]	18647	1			T12	12		T11	14		T19	8
auto[0]	values[1]	valids[0x1]	576	1			T7	3		T8	1		T20	3
auto[0]	values[2]	valids[0x0]	562	1			T7	6		T24	4		T8	1
auto[0]	values[2]	valids[0x1]	323	1			T7	9		T8	3		T21	3
auto[0]	values[3]	valids[0x0]	584	1			T11	2		T7	5		T24	4
auto[0]	values[3]	valids[0x1]	322	1			T11	2		T7	1		T21	4
auto[0]	values[4]	valids[0x0]	582	1			T23	4		T8	1		T20	2
auto[0]	values[4]	valids[0x1]	320	1			T8	2		T20	5		T21	3
auto[0]	values[5]	valids[0x0]	513	1			T12	2		T7	1		T8	3
auto[0]	values[5]	valids[0x1]	300	1			T7	4		T8	1		T20	1
auto[0]	values[6]	valids[0x0]	544	1			T11	2		T7	5		T8	2
auto[0]	values[6]	valids[0x1]	286	1			T19	2		T7	4		T20	1
auto[0]	values[7]	valids[0x0]	571	1			T7	8		T23	2		T20	2
auto[0]	values[7]	valids[0x1]	317	1			T7	3		T20	3		T21	8
auto[0]	values[8]	valids[0x0]	3886	1			T11	8		T7	40		T24	8
auto[0]	values[8]	valids[0x1]	2239	1			T12	2		T7	17		T24	4
auto[1]	values[0]	valids[0x0]	3912	1			T6	37		T42	36		T43	33
auto[1]	values[0]	valids[0x1]	15160	1			T6	122		T42	109		T43	83
auto[1]	values[1]	valids[0x1]	477	1			T6	5		T42	7		T43	1
auto[1]	values[2]	valids[0x0]	342	1			T6	3		T42	2		T43	10
auto[1]	values[2]	valids[0x1]	228	1			T6	4		T43	4		T48	3
auto[1]	values[3]	valids[0x0]	386	1			T6	9		T42	5		T43	6
auto[1]	values[3]	valids[0x1]	257	1			T6	4		T42	7		T43	3
auto[1]	values[4]	valids[0x0]	409	1			T6	1		T42	2		T43	5
auto[1]	values[4]	valids[0x1]	248	1			T6	1		T42	2		T43	3
auto[1]	values[5]	valids[0x0]	381	1			T6	6		T42	6		T43	2
auto[1]	values[5]	valids[0x1]	249	1			T6	2		T42	3		T43	1
auto[1]	values[6]	valids[0x0]	410	1			T6	5		T42	10		T43	2
auto[1]	values[6]	valids[0x1]	224	1			T6	2		T42	1		T43	2
auto[1]	values[7]	valids[0x0]	411	1			T6	3		T42	1		T43	2
auto[1]	values[7]	valids[0x1]	222	1			T6	5		T43	1		T48	5
auto[1]	values[8]	valids[0x0]	2507	1			T6	27		T42	20		T43	14
auto[1]	values[8]	valids[0x1]	1805	1			T6	19		T42	23		T43	10