Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18399

1

T12

19

T6

92

T11

1

auto[1]

21580

1

T6

55

T7

23

T8

36

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13943

1

T12

19

T6

64

T11

1

auto[1]

26036

1

T6

83

T7

51

T24

2

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	6750	1			T12	1		T6	29		T11	1
auto[524288:1048575]	4984	1			T12	2		T6	16		T19	1
auto[1048576:1572863]	4927	1			T6	6		T18	4		T19	4
auto[1572864:2097151]	4146	1			T6	28		T19	1		T7	13
auto[2097152:2621439]	4983	1			T6	7		T18	2		T19	2
auto[2621440:3145727]	4612	1			T12	6		T6	12		T19	3
auto[3145728:3670015]	5058	1			T12	3		T6	25		T18	2
auto[3670016:4194303]	4519	1			T12	7		T6	24		T7	16

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39463

1

T12

19

T6

147

T11

1

auto[1]

516

1

T7

1

T21

4

T48

7

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19406

1

T12

9

T6

88

T11

1

auto[1]

20573

1

T12

10

T6

59

T18

5

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1355	1			T12	1		T6	8		T11	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	716	1			T6	7		T7	3		T8	4
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	612	1			T12	1		T6	1		T23	7
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	312	1			T6	2		T42	4		T21	6
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	694	1			T6	1		T18	1		T7	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	413	1			T6	1		T42	5		T110	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	606	1			T6	3		T19	1		T23	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	347	1			T6	6		T7	2		T43	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	675	1			T6	2		T19	2		T7	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	358	1			T6	1		T25	1		T42	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	677	1			T6	3		T19	3		T7	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	357	1			T6	3		T7	5		T42	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	764	1			T6	2		T18	2		T7	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	423	1			T6	1		T7	3		T20	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	634	1			T12	7		T6	7		T7	5
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	355	1			T6	2		T7	1		T24	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	662	1			T6	6		T7	3		T24	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	397	1			T6	1		T7	1		T8	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	721	1			T12	1		T6	6		T19	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	461	1			T6	3		T7	5		T42	5
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	844	1			T18	3		T19	4		T8	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	424	1			T8	2		T42	1		T43	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	715	1			T6	2		T7	5		T24	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	403	1			T6	5		T7	6		T24	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	693	1			T6	3		T18	2		T7	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	402	1			T6	1		T7	2		T42	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	717	1			T12	6		T6	1		T7	5
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	421	1			T7	5		T42	1		T43	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	760	1			T12	3		T6	3		T19	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	362	1			T6	2		T7	2		T42	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	731	1			T6	5		T7	2		T23	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	388	1			T6	4		T7	1		T8	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	199	1			T6	2		T8	3		T42	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2125	1			T6	3		T8	7		T42	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	108	1			T42	2		T21	2		T63	4
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	988	1			T42	3		T21	73		T63	10
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	136	1			T6	1		T42	4		T21	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	938	1			T6	3		T42	10		T21	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	91	1			T6	1		T43	1		T48	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	689	1			T6	11		T43	19		T48	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	121	1			T42	1		T20	1		T21	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1136	1			T42	1		T20	6		T21	43
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	123	1			T6	1		T42	1		T27	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	943	1			T6	4		T42	3		T27	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	148	1			T6	1		T7	2		T21	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1328	1			T6	11		T7	4		T21	66
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	109	1			T7	1		T21	3		T128	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	926	1			T7	1		T21	41		T128	4
auto[1]	auto[1]	auto[0:524287]	auto[0]	122	1			T6	1		T8	1		T20	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	1174	1			T6	1		T8	10		T20	2
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	141	1			T6	1		T7	2		T42	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1641	1			T6	3		T7	4		T42	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	150	1			T8	1		T42	1		T27	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1328	1			T8	8		T42	1		T27	6
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	122	1			T21	1		T48	2		T63	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1173	1			T21	7		T48	10		T63	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	137	1			T7	1		T43	1		T21	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	1461	1			T7	1		T43	3		T21	26
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	125	1			T7	1		T21	1		T48	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1249	1			T7	1		T21	19		T48	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	124	1			T6	1		T43	1		T48	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1149	1			T6	4		T43	9		T48	22
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	127	1			T6	2		T7	1		T8	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1249	1			T6	4		T7	4		T8	5

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	9226	1			T12	9		T6	50		T11	1
auto[0]	auto[0]	auto[1]	72	1			T21	1		T61	1		T255	1
auto[0]	auto[1]	auto[0]	9021	1			T12	10		T6	42		T18	5
auto[0]	auto[1]	auto[1]	80	1			T21	1		T48	3		T29	1
auto[1]	auto[0]	auto[0]	9929	1			T6	38		T7	8		T8	10
auto[1]	auto[0]	auto[1]	179	1			T128	1		T61	2		T255	1
auto[1]	auto[1]	auto[0]	11287	1			T6	17		T7	14		T8	26
auto[1]	auto[1]	auto[1]	185	1			T7	1		T21	2		T48	4