Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.50	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	87.50

Variables for Group spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_rx_size	8	1	7	87.50	100	1	1	0

Summary for Variable cp_rx_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	1	7	87.50

User Defined Bins for cp_rx_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
specific_sizes[4092]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
specific_sizes[4]	46620	1			T50	2634		T57	1977		T128	2988
specific_sizes[2048]	126	1			T189	120		T190	2		T191	1
sizes[0]	60941	1			T76	3		T192	32		T50	2634
sizes[1]	4662	1			T8	294		T129	27		T142	32
sizes[2]	2603	1			T37	24		T127	69		T193	56
sizes[3]	111	1			T144	26		T194	3		T195	46
sizes[4]	257	1			T15	35		T52	85		T196	31