Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19804

1

T12

16

T18

10

T19

10

auto[1]

15154

1

T11

28

T7

127

T8

65

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4728	1			T7	20		T21	71		T27	50
values[1]	5146	1			T24	24		T8	76		T21	371
values[2]	4478	1			T7	77		T8	20		T20	30
values[3]	4885	1			T11	28		T7	44		T20	40
values[4]	3810	1			T18	10		T19	10		T7	42
values[5]	4449	1			T7	40		T23	12		T20	20
values[6]	3478	1			T137	12		T21	82		T29	96
values[7]	3984	1			T12	16		T7	20		T20	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4494	1			T12	16		T7	50		T20	20
values[1]	4786	1			T7	42		T8	40		T20	20
values[2]	4220	1			T19	10		T7	22		T23	12
values[3]	4543	1			T18	10		T7	20		T21	62
values[4]	3513	1			T7	47		T20	20		T137	12
values[5]	3991	1			T7	20		T25	4		T262	22
values[6]	4731	1			T7	20		T20	30		T21	120
values[7]	4680	1			T11	28		T7	22		T24	24

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	373	1			T7	10		T29	13		T31	17
auto[0]	values[0]	values[1]	439	1			T97	10		T197	22		T263	75
auto[0]	values[0]	values[2]	256	1			T264	6		T30	13		T32	9
auto[0]	values[0]	values[3]	259	1			T62	14		T233	22		T212	44
auto[0]	values[0]	values[4]	353	1			T239	8		T31	12		T243	12
auto[0]	values[0]	values[5]	253	1			T27	12		T99	10		T72	9
auto[0]	values[0]	values[6]	586	1			T21	62		T27	6		T208	15
auto[0]	values[0]	values[7]	342	1			T265	4		T32	9		T62	24
auto[0]	values[1]	values[0]	454	1			T21	145		T30	28		T62	14
auto[0]	values[1]	values[1]	382	1			T8	10		T62	17		T266	14
auto[0]	values[1]	values[2]	513	1			T8	8		T21	14		T32	27
auto[0]	values[1]	values[3]	363	1			T21	15		T28	10		T30	22
auto[0]	values[1]	values[4]	204	1			T267	14		T268	24		T269	16
auto[0]	values[1]	values[5]	572	1			T21	124		T197	31		T208	18
auto[0]	values[1]	values[6]	248	1			T208	18		T237	28		T233	7
auto[0]	values[1]	values[7]	276	1			T24	24		T29	7		T30	22
auto[0]	values[2]	values[0]	279	1			T7	10		T21	5		T30	29
auto[0]	values[2]	values[1]	287	1			T8	13		T26	14		T62	13
auto[0]	values[2]	values[2]	336	1			T62	12		T270	34		T225	14
auto[0]	values[2]	values[3]	494	1			T62	85		T208	17		T72	7
auto[0]	values[2]	values[4]	212	1			T7	16		T217	11		T271	17
auto[0]	values[2]	values[5]	370	1			T32	18		T208	22		T233	13
auto[0]	values[2]	values[6]	233	1			T20	27		T21	10		T62	11
auto[0]	values[2]	values[7]	321	1			T21	15		T31	18		T233	14
auto[0]	values[3]	values[0]	355	1			T31	14		T208	15		T233	46
auto[0]	values[3]	values[1]	385	1			T62	66		T268	9		T233	81
auto[0]	values[3]	values[2]	281	1			T7	15		T20	15		T21	9
auto[0]	values[3]	values[3]	291	1			T21	14		T30	7		T197	14
auto[0]	values[3]	values[4]	280	1			T20	13		T21	13		T232	22
auto[0]	values[3]	values[5]	200	1			T208	11		T217	6		T211	8
auto[0]	values[3]	values[6]	523	1			T21	6		T32	15		T224	52
auto[0]	values[3]	values[7]	446	1			T7	11		T99	10		T30	9
auto[0]	values[4]	values[0]	236	1			T27	17		T32	9		T62	5
auto[0]	values[4]	values[1]	201	1			T7	13		T29	14		T217	14
auto[0]	values[4]	values[2]	167	1			T19	10		T230	12		T208	17
auto[0]	values[4]	values[3]	372	1			T18	10		T7	11		T231	8
auto[0]	values[4]	values[4]	202	1			T30	14		T197	19		T214	10
auto[0]	values[4]	values[5]	134	1			T25	4		T27	12		T197	11
auto[0]	values[4]	values[6]	347	1			T208	14		T169	26		T272	10
auto[0]	values[4]	values[7]	297	1			T72	14		T273	2		T242	10
auto[0]	values[5]	values[0]	289	1			T20	11		T274	8		T29	9
auto[0]	values[5]	values[1]	294	1			T7	9		T27	21		T62	39
auto[0]	values[5]	values[2]	297	1			T23	12		T29	94		T72	12
auto[0]	values[5]	values[3]	295	1			T62	10		T72	12		T244	12
auto[0]	values[5]	values[4]	349	1			T32	13		T275	24		T276	30
auto[0]	values[5]	values[5]	256	1			T262	22		T21	29		T32	10
auto[0]	values[5]	values[6]	428	1			T7	12		T29	8		T31	15
auto[0]	values[5]	values[7]	278	1			T197	13		T170	4		T277	14
auto[0]	values[6]	values[0]	205	1			T30	9		T31	38		T32	25
auto[0]	values[6]	values[1]	269	1			T21	23		T197	18		T208	9
auto[0]	values[6]	values[2]	224	1			T31	20		T278	2		T233	16
auto[0]	values[6]	values[3]	316	1			T30	23		T32	13		T279	16
auto[0]	values[6]	values[4]	149	1			T137	12		T29	24		T211	16
auto[0]	values[6]	values[5]	220	1			T62	10		T242	12		T224	17
auto[0]	values[6]	values[6]	317	1			T240	26		T233	34		T242	15
auto[0]	values[6]	values[7]	311	1			T280	6		T233	17		T271	81
auto[0]	values[7]	values[0]	311	1			T12	16		T21	9		T27	17
auto[0]	values[7]	values[1]	397	1			T20	12		T21	10		T29	23
auto[0]	values[7]	values[2]	297	1			T281	20		T29	11		T197	10
auto[0]	values[7]	values[3]	209	1			T116	8		T282	8		T217	12
auto[0]	values[7]	values[4]	151	1			T29	5		T283	8		T284	6
auto[0]	values[7]	values[5]	218	1			T7	9		T229	22		T285	26
auto[0]	values[7]	values[6]	305	1			T62	10		T72	13		T271	11
auto[0]	values[7]	values[7]	297	1			T286	13		T62	21		T105	10
auto[1]	values[0]	values[0]	182	1			T7	10		T29	7		T31	7
auto[1]	values[0]	values[1]	261	1			T197	18		T213	7		T105	28
auto[1]	values[0]	values[2]	283	1			T30	7		T32	18		T208	11
auto[1]	values[0]	values[3]	187	1			T62	6		T233	49		T212	7
auto[1]	values[0]	values[4]	165	1			T31	8		T243	15		T287	11
auto[1]	values[0]	values[5]	163	1			T27	15		T99	10		T72	11
auto[1]	values[0]	values[6]	234	1			T21	9		T27	17		T208	5
auto[1]	values[0]	values[7]	392	1			T32	17		T62	21		T72	8
auto[1]	values[1]	values[0]	164	1			T21	12		T30	22		T62	6
auto[1]	values[1]	values[1]	277	1			T8	10		T62	5		T233	9
auto[1]	values[1]	values[2]	298	1			T8	48		T21	26		T32	21
auto[1]	values[1]	values[3]	399	1			T21	27		T28	19		T30	30
auto[1]	values[1]	values[4]	162	1			T268	5		T212	10		T225	58
auto[1]	values[1]	values[5]	219	1			T21	8		T197	5		T208	2
auto[1]	values[1]	values[6]	287	1			T208	2		T233	13		T169	99
auto[1]	values[1]	values[7]	328	1			T29	61		T30	5		T62	42
auto[1]	values[2]	values[0]	413	1			T7	20		T21	15		T30	17
auto[1]	values[2]	values[1]	296	1			T8	7		T62	7		T253	5
auto[1]	values[2]	values[2]	217	1			T62	8		T225	6		T271	9
auto[1]	values[2]	values[3]	139	1			T62	28		T208	14		T72	13
auto[1]	values[2]	values[4]	217	1			T7	31		T217	19		T288	16
auto[1]	values[2]	values[5]	241	1			T32	7		T208	23		T233	7
auto[1]	values[2]	values[6]	229	1			T20	3		T21	19		T62	32
auto[1]	values[2]	values[7]	194	1			T21	10		T31	6		T233	17
auto[1]	values[3]	values[0]	255	1			T31	6		T289	8		T208	7
auto[1]	values[3]	values[1]	138	1			T62	5		T268	13		T233	9
auto[1]	values[3]	values[2]	143	1			T7	7		T20	5		T21	44
auto[1]	values[3]	values[3]	373	1			T21	6		T30	13		T197	6
auto[1]	values[3]	values[4]	210	1			T20	7		T21	92		T225	3
auto[1]	values[3]	values[5]	501	1			T208	9		T217	16		T290	24
auto[1]	values[3]	values[6]	211	1			T21	14		T32	5		T224	8
auto[1]	values[3]	values[7]	293	1			T11	28		T7	11		T99	16
auto[1]	values[4]	values[0]	288	1			T27	10		T32	25		T62	15
auto[1]	values[4]	values[1]	288	1			T7	9		T29	98		T217	6
auto[1]	values[4]	values[2]	281	1			T208	10		T225	13		T214	12
auto[1]	values[4]	values[3]	254	1			T7	9		T225	8		T291	16
auto[1]	values[4]	values[4]	207	1			T292	16		T30	6		T197	25
auto[1]	values[4]	values[5]	68	1			T27	12		T197	9		T72	14
auto[1]	values[4]	values[6]	234	1			T208	18		T293	16		T169	9
auto[1]	values[4]	values[7]	234	1			T72	6		T242	39		T225	4
auto[1]	values[5]	values[0]	221	1			T20	9		T29	11		T32	27
auto[1]	values[5]	values[1]	257	1			T7	11		T27	3		T218	36
auto[1]	values[5]	values[2]	221	1			T29	7		T72	10		T217	8
auto[1]	values[5]	values[3]	162	1			T62	10		T72	8		T253	26
auto[1]	values[5]	values[4]	259	1			T32	15		T217	14		T105	13
auto[1]	values[5]	values[5]	293	1			T21	12		T32	13		T242	60
auto[1]	values[5]	values[6]	252	1			T7	8		T22	18		T29	12
auto[1]	values[5]	values[7]	298	1			T197	7		T170	33		T294	53
auto[1]	values[6]	values[0]	236	1			T30	11		T31	16		T32	21
auto[1]	values[6]	values[1]	254	1			T21	59		T197	22		T208	11
auto[1]	values[6]	values[2]	203	1			T31	9		T233	4		T170	18
auto[1]	values[6]	values[3]	215	1			T30	37		T32	7		T105	9
auto[1]	values[6]	values[4]	224	1			T29	72		T211	9		T224	5
auto[1]	values[6]	values[5]	134	1			T62	12		T242	8		T224	5
auto[1]	values[6]	values[6]	140	1			T233	2		T242	14		T169	11
auto[1]	values[6]	values[7]	61	1			T233	3		T271	5		T295	8
auto[1]	values[7]	values[0]	233	1			T21	50		T27	8		T29	8
auto[1]	values[7]	values[1]	361	1			T20	8		T21	10		T29	8
auto[1]	values[7]	values[2]	203	1			T29	61		T197	10		T62	6
auto[1]	values[7]	values[3]	215	1			T217	8		T211	19		T212	11
auto[1]	values[7]	values[4]	169	1			T29	15		T271	7		T105	3
auto[1]	values[7]	values[5]	149	1			T7	11		T32	11		T233	15
auto[1]	values[7]	values[6]	157	1			T62	10		T72	7		T223	28
auto[1]	values[7]	values[7]	312	1			T286	7		T62	11		T105	10