Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	12	0	12	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7165265	1			T4	971		T1	2		T5	1
all_pins[1]	7165265	1			T4	971		T1	2		T5	1
all_pins[2]	7165265	1			T4	971		T1	2		T5	1
all_pins[3]	7165265	1			T4	971		T1	2		T5	1
all_pins[4]	7165265	1			T4	971		T1	2		T5	1
all_pins[5]	7165265	1			T4	971		T1	2		T5	1
all_pins[6]	7165265	1			T4	971		T1	2		T5	1
all_pins[7]	7165265	1			T4	971		T1	2		T5	1
all_pins[8]	7165265	1			T4	971		T1	2		T5	1
all_pins[9]	7165265	1			T4	971		T1	2		T5	1
all_pins[10]	7165265	1			T4	971		T1	2		T5	1
all_pins[11]	7165265	1			T4	971		T1	2		T5	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	85607088	1			T4	11652		T1	23		T5	12
values[0x1]	376092	1			T1	1		T2	1		T9	2
transitions[0x0=>0x1]	373836	1			T1	1		T2	1		T9	1
transitions[0x1=>0x0]	373852	1			T1	1		T2	1		T9	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	7164731	1			T4	971		T1	2		T5	1
all_pins[0]	values[0x1]	534	1			T66	4		T67	2		T68	3
all_pins[0]	transitions[0x0=>0x1]	333	1			T66	2		T67	1		T68	3
all_pins[0]	transitions[0x1=>0x0]	355784	1			T9	1		T66	1		T67	2
all_pins[1]	values[0x0]	6809280	1			T4	971		T1	2		T5	1
all_pins[1]	values[0x1]	355985	1			T9	1		T66	3		T67	3
all_pins[1]	transitions[0x0=>0x1]	355866	1			T66	1		T67	2		T87	2
all_pins[1]	transitions[0x1=>0x0]	459	1			T1	1		T2	1		T13	1
all_pins[2]	values[0x0]	7164687	1			T4	971		T1	1		T5	1
all_pins[2]	values[0x1]	578	1			T1	1		T2	1		T9	1
all_pins[2]	transitions[0x0=>0x1]	555	1			T1	1		T2	1		T9	1
all_pins[2]	transitions[0x1=>0x0]	64	1			T67	2		T68	1		T157	1
all_pins[3]	values[0x0]	7165178	1			T4	971		T1	2		T5	1
all_pins[3]	values[0x1]	87	1			T67	2		T68	1		T157	1
all_pins[3]	transitions[0x0=>0x1]	61	1			T67	2		T68	1		T180	3
all_pins[3]	transitions[0x1=>0x0]	396	1			T66	4		T68	1		T88	1
all_pins[4]	values[0x0]	7164843	1			T4	971		T1	2		T5	1
all_pins[4]	values[0x1]	422	1			T66	4		T68	1		T88	1
all_pins[4]	transitions[0x0=>0x1]	230	1			T66	4		T68	1		T88	1
all_pins[4]	transitions[0x1=>0x0]	1957	1			T67	2		T68	1		T88	3
all_pins[5]	values[0x0]	7163116	1			T4	971		T1	2		T5	1
all_pins[5]	values[0x1]	2149	1			T67	2		T68	1		T88	3
all_pins[5]	transitions[0x0=>0x1]	2123	1			T67	2		T68	1		T88	1
all_pins[5]	transitions[0x1=>0x0]	2991	1			T66	2		T67	4		T68	1
all_pins[6]	values[0x0]	7162248	1			T4	971		T1	2		T5	1
all_pins[6]	values[0x1]	3017	1			T66	2		T67	4		T68	1
all_pins[6]	transitions[0x0=>0x1]	1691	1			T67	3		T68	1		T88	2
all_pins[6]	transitions[0x1=>0x0]	599	1			T66	1		T67	4		T68	2
all_pins[7]	values[0x0]	7163340	1			T4	971		T1	2		T5	1
all_pins[7]	values[0x1]	1925	1			T66	3		T67	5		T68	2
all_pins[7]	transitions[0x0=>0x1]	1694	1			T66	3		T67	4		T68	2
all_pins[7]	transitions[0x1=>0x0]	220	1			T66	2		T67	1		T68	1
all_pins[8]	values[0x0]	7164814	1			T4	971		T1	2		T5	1
all_pins[8]	values[0x1]	451	1			T66	2		T67	2		T68	1
all_pins[8]	transitions[0x0=>0x1]	435	1			T66	2		T67	1		T68	1
all_pins[8]	transitions[0x1=>0x0]	70	1			T66	1		T68	3		T88	2
all_pins[9]	values[0x0]	7165179	1			T4	971		T1	2		T5	1
all_pins[9]	values[0x1]	86	1			T66	1		T67	1		T68	3
all_pins[9]	transitions[0x0=>0x1]	62	1			T66	1		T67	1		T88	2
all_pins[9]	transitions[0x1=>0x0]	82	1			T66	2		T67	1		T68	4
all_pins[10]	values[0x0]	7165159	1			T4	971		T1	2		T5	1
all_pins[10]	values[0x1]	106	1			T66	2		T67	1		T68	7
all_pins[10]	transitions[0x0=>0x1]	77	1			T67	1		T68	4		T88	1
all_pins[10]	transitions[0x1=>0x0]	10723	1			T66	1		T67	5		T68	1
all_pins[11]	values[0x0]	7154513	1			T4	971		T1	2		T5	1
all_pins[11]	values[0x1]	10752	1			T66	3		T67	5		T68	4
all_pins[11]	transitions[0x0=>0x1]	10709	1			T66	1		T67	3		T68	1
all_pins[11]	transitions[0x1=>0x0]	507	1			T66	2		T68	1		T156	3