Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	431	1			T12	2		T7	9		T25	2
auto[ReadAddrCrossIntoMailbox]	315	1			T7	12		T8	1		T20	3
auto[ReadAddrCrossOutOfMailbox]	314	1			T7	7		T8	1		T20	2
auto[ReadAddrCrossAllMailbox]	230	1			T7	2		T20	1		T137	2
auto[ReadAddrOutsideMailbox]	3934	1			T12	2		T11	12		T7	17

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2714

1

T12

2

T11

6

T7

16

auto[1]

2510

1

T12

2

T11

6

T7

31

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	853	1			T12	2		T7	8		T24	4
read_ops[0x0b]	914	1			T11	6		T7	9		T24	2
read_ops[0x3b]	911	1			T7	8		T24	4		T8	3
read_ops[0x6b]	803	1			T11	2		T7	8		T24	8
read_ops[0xbb]	861	1			T11	2		T7	8		T23	2
read_ops[0xeb]	882	1			T12	2		T11	2		T7	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	45	1			T12	1		T7	1		T27	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T12	1		T7	1		T229	4
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	13	1			T8	1		T20	1		T296	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T7	1		T29	1		T31	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T7	1		T31	1		T62	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T7	1		T27	1		T217	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T197	1		T62	1		T72	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T30	2		T62	1		T217	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	325	1			T7	2		T24	2		T26	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	313	1			T7	1		T24	2		T20	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T20	1		T21	1		T116	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T7	1		T20	1		T116	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	37	1			T7	3		T99	1		T31	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T21	1		T29	2		T31	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T7	1		T20	1		T32	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T7	2		T27	1		T32	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T21	2		T31	1		T273	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T7	1		T273	1		T233	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	378	1			T11	3		T24	1		T8	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	326	1			T11	3		T7	1		T24	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T25	1		T28	1		T62	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T25	1		T20	1		T29	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T7	1		T20	1		T29	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T7	1		T211	1		T225	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T137	1		T32	1		T233	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T137	1		T21	2		T27	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T20	1		T27	1		T62	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T21	1		T29	3		T62	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	358	1			T7	4		T24	2		T20	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	330	1			T7	2		T24	2		T8	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T7	1		T21	1		T229	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T7	3		T27	1		T229	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T21	2		T208	1		T217	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T7	3		T20	1		T21	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T8	1		T20	1		T21	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T29	1		T72	1		T217	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T137	1		T29	1		T233	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T137	1		T213	1		T271	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	314	1			T11	1		T24	4		T137	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	286	1			T11	1		T7	1		T24	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T137	1		T229	1		T30	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T7	1		T137	1		T21	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T137	1		T197	1		T217	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T7	2		T137	1		T27	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	37	1			T137	1		T72	1		T242	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T7	1		T137	1		T29	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T62	2		T217	1		T225	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T62	1		T297	1		T298	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	335	1			T11	1		T7	1		T23	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	303	1			T11	1		T7	3		T23	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T116	1		T197	1		T232	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T7	1		T21	1		T116	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T7	1		T21	1		T27	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T21	1		T29	1		T30	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T31	1		T208	1		T253	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T7	1		T21	3		T29	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T208	1		T211	1		T224	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T7	1		T99	1		T72	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	328	1			T12	1		T11	1		T23	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	338	1			T12	1		T11	1		T7	2