Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4474	1			T7	65		T8	20		T262	22
values[1]	4513	1			T20	20		T21	205		T27	47
values[2]	4006	1			T7	20		T20	20		T137	12
values[3]	3509	1			T21	91		T27	27		T299	8
values[4]	3950	1			T19	10		T7	44		T23	12
values[5]	4032	1			T11	28		T7	30		T25	4
values[6]	5220	1			T12	16		T7	40		T24	24
values[7]	5254	1			T18	10		T7	44		T21	219

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4293	1			T19	10		T8	20		T21	82
values[1]	4444	1			T7	25		T8	20		T21	201
values[2]	4239	1			T23	12		T20	20		T21	61
values[3]	4875	1			T11	28		T7	22		T20	50
values[4]	4439	1			T7	44		T24	24		T25	4
values[5]	4380	1			T12	16		T18	10		T7	82
values[6]	3984	1			T7	50		T20	20		T27	23
values[7]	4304	1			T7	20		T8	56		T26	14

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34398

1

T12

16

T11

26

T18

10

auto[1]

560

1

T11

2

T7

7

T8

5

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	582	1			T8	18		T21	20		T31	33
auto[0]	values[0]	values[1]	476	1			T7	25		T32	20		T62	20
auto[0]	values[0]	values[2]	746	1			T29	68		T62	22		T72	19
auto[0]	values[0]	values[3]	771	1			T262	22		T28	26		T30	30
auto[0]	values[0]	values[4]	482	1			T197	20		T300	8		T211	25
auto[0]	values[0]	values[5]	413	1			T7	20		T27	24		T212	45
auto[0]	values[0]	values[6]	434	1			T197	20		T62	20		T266	14
auto[0]	values[0]	values[7]	492	1			T7	20		T29	20		T301	6
auto[0]	values[1]	values[0]	447	1			T30	27		T289	8		T197	20
auto[0]	values[1]	values[1]	525	1			T21	20		T292	16		T30	24
auto[0]	values[1]	values[2]	345	1			T21	20		T62	24		T237	28
auto[0]	values[1]	values[3]	768	1			T20	18		T21	38		T98	2
auto[0]	values[1]	values[4]	919	1			T21	105		T218	36		T72	20
auto[0]	values[1]	values[5]	514	1			T27	24		T285	26		T30	19
auto[0]	values[1]	values[6]	476	1			T27	22		T208	31		T267	14
auto[0]	values[1]	values[7]	431	1			T21	20		T32	19		T302	2
auto[0]	values[2]	values[0]	934	1			T29	109		T31	19		T32	19
auto[0]	values[2]	values[1]	384	1			T31	20		T208	18		T233	20
auto[0]	values[2]	values[2]	351	1			T20	16		T29	20		T225	23
auto[0]	values[2]	values[3]	558	1			T27	24		T62	20		T275	24
auto[0]	values[2]	values[4]	430	1			T29	101		T32	28		T62	25
auto[0]	values[2]	values[5]	473	1			T137	12		T31	20		T62	22
auto[0]	values[2]	values[6]	364	1			T7	20		T281	20		T29	20
auto[0]	values[2]	values[7]	425	1			T32	50		T208	22		T243	22
auto[0]	values[3]	values[0]	275	1			T239	8		T30	51		T303	14
auto[0]	values[3]	values[1]	653	1			T21	20		T242	28		T169	20
auto[0]	values[3]	values[2]	513	1			T30	52		T31	16		T197	21
auto[0]	values[3]	values[3]	304	1			T97	10		T31	28		T304	2
auto[0]	values[3]	values[4]	541	1			T21	69		T27	24		T62	25
auto[0]	values[3]	values[5]	487	1			T299	8		T62	31		T279	16
auto[0]	values[3]	values[6]	444	1			T233	38		T253	20		T305	6
auto[0]	values[3]	values[7]	231	1			T229	22		T274	8		T306	2
auto[0]	values[4]	values[0]	292	1			T19	10		T30	20		T286	20
auto[0]	values[4]	values[1]	463	1			T116	8		T236	8		T233	51
auto[0]	values[4]	values[2]	462	1			T23	12		T29	76		T32	23
auto[0]	values[4]	values[3]	465	1			T7	22		T21	25		T29	70
auto[0]	values[4]	values[4]	441	1			T7	19		T20	20		T62	41
auto[0]	values[4]	values[5]	663	1			T265	4		T32	20		T233	20
auto[0]	values[4]	values[6]	481	1			T197	22		T62	20		T225	20
auto[0]	values[4]	values[7]	616	1			T32	29		T197	20		T72	20
auto[0]	values[5]	values[0]	140	1			T243	20		T287	25		T307	19
auto[0]	values[5]	values[1]	429	1			T21	132		T99	26		T308	6
auto[0]	values[5]	values[2]	575	1			T72	20		T309	24		T242	20
auto[0]	values[5]	values[3]	547	1			T11	26		T21	59		T31	24
auto[0]	values[5]	values[4]	283	1			T25	4		T208	51		T310	8
auto[0]	values[5]	values[5]	720	1			T62	20		T242	41		T311	12
auto[0]	values[5]	values[6]	460	1			T7	28		T20	20		T211	20
auto[0]	values[5]	values[7]	840	1			T26	14		T21	93		T208	22
auto[0]	values[6]	values[0]	458	1			T29	20		T225	30		T271	20
auto[0]	values[6]	values[1]	786	1			T8	20		T21	29		T27	25
auto[0]	values[6]	values[2]	627	1			T21	41		T197	20		T212	80
auto[0]	values[6]	values[3]	607	1			T20	28		T99	20		T62	31
auto[0]	values[6]	values[4]	805	1			T24	24		T264	6		T255	117
auto[0]	values[6]	values[5]	384	1			T12	16		T7	40		T32	22
auto[0]	values[6]	values[6]	751	1			T31	23		T62	20		T208	20
auto[0]	values[6]	values[7]	745	1			T8	53		T312	4		T278	2
auto[0]	values[7]	values[0]	1088	1			T21	62		T30	43		T208	20
auto[0]	values[7]	values[1]	655	1			T29	20		T32	25		T230	12
auto[0]	values[7]	values[2]	566	1			T251	24		T243	19		T294	25
auto[0]	values[7]	values[3]	763	1			T21	154		T32	22		T197	20
auto[0]	values[7]	values[4]	467	1			T7	21		T29	20		T32	20
auto[0]	values[7]	values[5]	652	1			T18	10		T7	21		T30	18
auto[0]	values[7]	values[6]	511	1			T22	18		T197	20		T62	81
auto[0]	values[7]	values[7]	468	1			T30	19		T62	65		T222	4
auto[1]	values[0]	values[0]	10	1			T8	2		T31	1		T241	4
auto[1]	values[0]	values[1]	16	1			T253	1		T217	1		T214	1
auto[1]	values[0]	values[2]	8	1			T72	1		T214	3		T313	1
auto[1]	values[0]	values[3]	19	1			T28	3		T30	2		T213	1
auto[1]	values[0]	values[4]	4	1			T271	2		T314	1		T315	1
auto[1]	values[0]	values[5]	2	1			T212	1		T298	1		-	-
auto[1]	values[0]	values[6]	15	1			T316	6		T224	2		T317	2
auto[1]	values[0]	values[7]	4	1			T253	1		T318	1		T319	2
auto[1]	values[1]	values[0]	9	1			T320	3		T248	2		T321	1
auto[1]	values[1]	values[1]	10	1			T30	2		T211	1		T271	4
auto[1]	values[1]	values[2]	2	1			T221	1		T322	1		-	-
auto[1]	values[1]	values[3]	15	1			T20	2		T21	2		T211	1
auto[1]	values[1]	values[4]	19	1			T268	1		T233	2		T242	2
auto[1]	values[1]	values[5]	13	1			T30	1		T211	1		T213	2
auto[1]	values[1]	values[6]	7	1			T27	1		T208	1		T217	2
auto[1]	values[1]	values[7]	13	1			T32	1		T253	5		T323	1
auto[1]	values[2]	values[0]	24	1			T29	3		T31	1		T32	3
auto[1]	values[2]	values[1]	10	1			T208	2		T214	1		T296	3
auto[1]	values[2]	values[2]	9	1			T20	4		T225	1		T324	1
auto[1]	values[2]	values[3]	5	1			T27	1		T325	2		T326	2
auto[1]	values[2]	values[4]	15	1			T293	4		T223	6		T211	2
auto[1]	values[2]	values[5]	13	1			T296	1		T248	1		T327	2
auto[1]	values[2]	values[6]	4	1			T328	2		T329	1		T330	1
auto[1]	values[2]	values[7]	7	1			T32	2		T208	1		T226	1
auto[1]	values[3]	values[0]	5	1			T30	1		T211	1		T331	3
auto[1]	values[3]	values[1]	10	1			T242	1		T271	3		T214	1
auto[1]	values[3]	values[2]	13	1			T30	3		T31	4		T197	1
auto[1]	values[3]	values[3]	12	1			T31	1		T208	3		T325	1
auto[1]	values[3]	values[4]	7	1			T21	2		T27	3		T72	1
auto[1]	values[3]	values[5]	4	1			T62	1		T332	3		-	-
auto[1]	values[3]	values[6]	7	1			T233	1		T170	1		T333	2
auto[1]	values[3]	values[7]	3	1			T287	3		-	-		-	-
auto[1]	values[4]	values[0]	3	1			T62	2		T72	1		-	-
auto[1]	values[4]	values[1]	6	1			T233	1		T217	2		T221	1
auto[1]	values[4]	values[2]	5	1			T32	1		T334	3		T330	1
auto[1]	values[4]	values[3]	3	1			T29	2		T32	1		-	-
auto[1]	values[4]	values[4]	10	1			T7	3		T62	1		T233	2
auto[1]	values[4]	values[5]	25	1			T290	4		T335	3		T294	5
auto[1]	values[4]	values[6]	6	1			T325	2		T333	2		T336	2
auto[1]	values[4]	values[7]	9	1			T32	5		T217	2		T247	2
auto[1]	values[5]	values[0]	4	1			T307	1		T337	1		T338	2
auto[1]	values[5]	values[1]	3	1			T339	1		T340	1		T341	1
auto[1]	values[5]	values[2]	5	1			T224	1		T214	1		T248	1
auto[1]	values[5]	values[3]	7	1			T11	2		T342	5		-	-
auto[1]	values[5]	values[4]	3	1			T243	2		T322	1		-	-
auto[1]	values[5]	values[5]	4	1			T169	1		T247	1		T343	1
auto[1]	values[5]	values[6]	6	1			T7	2		T213	1		T295	2
auto[1]	values[5]	values[7]	6	1			T21	2		T72	2		T247	1
auto[1]	values[6]	values[0]	8	1			T225	2		T105	1		T296	2
auto[1]	values[6]	values[1]	10	1			T27	2		T32	1		T72	1
auto[1]	values[6]	values[2]	6	1			T212	1		T224	2		T320	1
auto[1]	values[6]	values[3]	6	1			T20	2		T62	1		T214	1
auto[1]	values[6]	values[4]	6	1			T233	1		T242	1		T105	2
auto[1]	values[6]	values[5]	6	1			T208	3		T212	1		T344	1
auto[1]	values[6]	values[6]	7	1			T31	1		T105	2		T345	1
auto[1]	values[6]	values[7]	8	1			T8	3		T243	1		T342	2
auto[1]	values[7]	values[0]	14	1			T242	1		T346	2		T243	1
auto[1]	values[7]	values[1]	8	1			T72	2		T344	2		T347	1
auto[1]	values[7]	values[2]	6	1			T251	2		T243	1		T294	2
auto[1]	values[7]	values[3]	25	1			T21	3		T170	2		T346	2
auto[1]	values[7]	values[4]	7	1			T7	1		T217	1		T248	3
auto[1]	values[7]	values[5]	7	1			T7	1		T30	2		T296	1
auto[1]	values[7]	values[6]	11	1			T62	4		T243	1		T333	2
auto[1]	values[7]	values[7]	6	1			T30	1		T62	1		T211	1