SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_flip_position | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_opcode | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 148 | 1 | T173 | 1 | T177 | 6 | T178 | 5 | ||||
auto[1] | 122 | 1 | T173 | 1 | T177 | 5 | T178 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
read_ops[0x03] | 44 | 1 | T177 | 3 | T178 | 3 | T348 | 4 | ||||
read_ops[0x0b] | 39 | 1 | T177 | 6 | T246 | 2 | T349 | 2 | ||||
read_ops[0x3b] | 54 | 1 | T177 | 2 | T178 | 4 | T246 | 1 | ||||
read_ops[0x6b] | 45 | 1 | T348 | 2 | T350 | 3 | T351 | 5 | ||||
read_ops[0xbb] | 45 | 1 | T348 | 8 | T352 | 3 | T353 | 3 | ||||
read_ops[0xeb] | 43 | 1 | T173 | 2 | T178 | 2 | T235 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |