Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2498

1

T4

15

T5

12

T16

10

auto[1]

2486

1

T4

9

T5

2

T16

7

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2638

1

T4

21

T16

17

T6

38

auto[1]

2346

1

T4

3

T5

14

T6

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3957

1

T4

15

T5

14

T16

13

auto[1]

1027

1

T4

9

T16

4

T6

18

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	960	1			T4	4		T5	4		T16	3
valid[1]	1000	1			T4	4		T5	1		T16	4
valid[2]	1025	1			T4	8		T5	3		T16	2
valid[3]	990	1			T4	6		T5	3		T16	6
valid[4]	1009	1			T4	2		T5	3		T16	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	147	1			T4	2		T16	1		T6	3
auto[0]	auto[0]	valid[0]	auto[1]	229	1			T5	4		T6	1		T33	2
auto[0]	auto[0]	valid[1]	auto[0]	147	1			T16	3		T6	2		T7	1
auto[0]	auto[0]	valid[1]	auto[1]	229	1			T5	1		T6	2		T33	5
auto[0]	auto[0]	valid[2]	auto[0]	161	1			T4	5		T7	1		T8	1
auto[0]	auto[0]	valid[2]	auto[1]	218	1			T5	2		T6	1		T42	1
auto[0]	auto[0]	valid[3]	auto[0]	176	1			T4	2		T16	3		T6	2
auto[0]	auto[0]	valid[3]	auto[1]	223	1			T4	1		T5	2		T6	1
auto[0]	auto[0]	valid[4]	auto[0]	181	1			T16	1		T6	4		T8	3
auto[0]	auto[0]	valid[4]	auto[1]	229	1			T5	3		T6	2		T33	1
auto[0]	auto[1]	valid[0]	auto[0]	159	1			T16	2		T6	1		T8	3
auto[0]	auto[1]	valid[0]	auto[1]	235	1			T6	2		T106	1		T27	1
auto[0]	auto[1]	valid[1]	auto[0]	166	1			T4	1		T16	1		T6	3
auto[0]	auto[1]	valid[1]	auto[1]	240	1			T6	1		T42	1		T107	2
auto[0]	auto[1]	valid[2]	auto[0]	158	1			T4	1		T16	1		T7	2
auto[0]	auto[1]	valid[2]	auto[1]	264	1			T5	1		T33	3		T42	1
auto[0]	auto[1]	valid[3]	auto[0]	164	1			T4	1		T7	1		T8	2
auto[0]	auto[1]	valid[3]	auto[1]	242	1			T4	1		T5	1		T33	2
auto[0]	auto[1]	valid[4]	auto[0]	152	1			T16	1		T6	5		T7	1
auto[0]	auto[1]	valid[4]	auto[1]	237	1			T4	1		T33	2		T106	1
auto[1]	auto[0]	valid[0]	auto[0]	99	1			T4	1		T8	1		T140	2
auto[1]	auto[0]	valid[1]	auto[0]	130	1			T4	1		T6	1		T42	2
auto[1]	auto[0]	valid[2]	auto[0]	117	1			T4	1		T6	2		T42	1
auto[1]	auto[0]	valid[3]	auto[0]	89	1			T4	1		T16	2		T6	3
auto[1]	auto[0]	valid[4]	auto[0]	123	1			T4	1		T6	1		T7	1
auto[1]	auto[1]	valid[0]	auto[0]	91	1			T4	1		T6	3		T8	1
auto[1]	auto[1]	valid[1]	auto[0]	88	1			T4	2		T6	2		T42	1
auto[1]	auto[1]	valid[2]	auto[0]	107	1			T4	1		T16	1		T42	1
auto[1]	auto[1]	valid[3]	auto[0]	96	1			T16	1		T6	3		T8	1
auto[1]	auto[1]	valid[4]	auto[0]	87	1			T6	3		T43	1		T140	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal