Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	72	2	70	97.22

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	72	2	70	97.22	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	416	1			T66	7		T67	10		T68	10
all_values[1]	416	1			T66	7		T67	10		T68	10
all_values[2]	416	1			T66	7		T67	10		T68	10
all_values[3]	416	1			T66	7		T67	10		T68	10
all_values[4]	416	1			T66	7		T67	10		T68	10
all_values[5]	416	1			T66	7		T67	10		T68	10
all_values[6]	416	1			T66	7		T67	10		T68	10
all_values[7]	416	1			T66	7		T67	10		T68	10
all_values[8]	416	1			T66	7		T67	10		T68	10
all_values[9]	416	1			T66	7		T67	10		T68	10
all_values[10]	416	1			T66	7		T67	10		T68	10
all_values[11]	416	1			T66	7		T67	10		T68	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2714

1

T66

44

T67

49

T68

77

auto[1]

2278

1

T66

40

T67

71

T68

43

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1883

1

T66

37

T67

52

T68

47

auto[1]

3109

1

T66

47

T67

68

T68

73

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2766

1

T66

45

T67

71

T68

69

auto[1]

2226

1

T66

39

T67

49

T68

51

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	2	70	97.22	2
Automatically Generated Cross Bins	72	2	70	97.22	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[11]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	65	1			T67	2		T68	4		T88	1
all_values[0]	auto[0]	auto[0]	auto[1]	49	1			T67	4		T68	1		T87	3
all_values[0]	auto[0]	auto[1]	auto[0]	61	1			T66	1		T67	2		T88	1
all_values[0]	auto[0]	auto[1]	auto[1]	52	1			T66	1		T68	1		T156	2
all_values[0]	auto[1]	auto[0]	auto[1]	100	1			T66	2		T67	2		T68	3
all_values[0]	auto[1]	auto[1]	auto[1]	89	1			T66	3		T68	1		T88	1
all_values[1]	auto[0]	auto[0]	auto[0]	80	1			T66	1		T68	3		T87	4
all_values[1]	auto[0]	auto[0]	auto[1]	42	1			T67	1		T88	1		T156	2
all_values[1]	auto[0]	auto[1]	auto[0]	56	1			T66	1		T67	2		T68	1
all_values[1]	auto[0]	auto[1]	auto[1]	37	1			T66	1		T68	1		T87	1
all_values[1]	auto[1]	auto[0]	auto[1]	100	1			T66	1		T67	2		T68	2
all_values[1]	auto[1]	auto[1]	auto[1]	101	1			T66	3		T67	5		T68	3
all_values[2]	auto[0]	auto[0]	auto[0]	92	1			T66	2		T67	1		T68	3
all_values[2]	auto[0]	auto[0]	auto[1]	44	1			T156	1		T87	1		T157	1
all_values[2]	auto[0]	auto[1]	auto[0]	61	1			T66	2		T67	4		T87	1
all_values[2]	auto[0]	auto[1]	auto[1]	34	1			T66	1		T67	2		T68	3
all_values[2]	auto[1]	auto[0]	auto[1]	92	1			T67	1		T68	2		T156	2
all_values[2]	auto[1]	auto[1]	auto[1]	93	1			T66	2		T67	2		T68	2
all_values[3]	auto[0]	auto[0]	auto[0]	93	1			T66	4		T68	2		T156	2
all_values[3]	auto[0]	auto[0]	auto[1]	36	1			T67	2		T88	2		T157	1
all_values[3]	auto[0]	auto[1]	auto[0]	70	1			T66	1		T67	2		T68	3
all_values[3]	auto[0]	auto[1]	auto[1]	35	1			T180	1		T181	1		T146	1
all_values[3]	auto[1]	auto[0]	auto[1]	100	1			T66	2		T67	3		T68	4
all_values[3]	auto[1]	auto[1]	auto[1]	82	1			T67	3		T68	1		T87	2
all_values[4]	auto[0]	auto[0]	auto[0]	91	1			T66	1		T67	3		T68	2
all_values[4]	auto[0]	auto[0]	auto[1]	37	1			T68	2		T88	2		T157	1
all_values[4]	auto[0]	auto[1]	auto[0]	74	1			T67	5		T68	2		T87	5
all_values[4]	auto[0]	auto[1]	auto[1]	36	1			T66	1		T68	1		T88	1
all_values[4]	auto[1]	auto[0]	auto[1]	99	1			T66	3		T67	2		T68	1
all_values[4]	auto[1]	auto[1]	auto[1]	79	1			T66	2		T68	2		T87	1
all_values[5]	auto[0]	auto[0]	auto[0]	85	1			T66	4		T67	1		T68	3
all_values[5]	auto[0]	auto[0]	auto[1]	46	1			T68	4		T156	1		T87	1
all_values[5]	auto[0]	auto[1]	auto[0]	62	1			T67	4		T156	1		T87	3
all_values[5]	auto[0]	auto[1]	auto[1]	43	1			T88	2		T180	1		T181	1
all_values[5]	auto[1]	auto[0]	auto[1]	107	1			T66	3		T68	3		T88	1
all_values[5]	auto[1]	auto[1]	auto[1]	73	1			T67	5		T88	1		T157	1
all_values[6]	auto[0]	auto[0]	auto[0]	79	1			T66	3		T67	2		T68	5
all_values[6]	auto[0]	auto[0]	auto[1]	39	1			T67	1		T88	1		T156	1
all_values[6]	auto[0]	auto[1]	auto[0]	69	1			T66	2		T68	1		T87	2
all_values[6]	auto[0]	auto[1]	auto[1]	38	1			T67	2		T88	1		T180	1
all_values[6]	auto[1]	auto[0]	auto[1]	99	1			T67	3		T68	3		T88	2
all_values[6]	auto[1]	auto[1]	auto[1]	92	1			T66	2		T67	2		T68	1
all_values[7]	auto[0]	auto[0]	auto[0]	88	1			T66	1		T67	2		T68	2
all_values[7]	auto[0]	auto[0]	auto[1]	32	1			T67	1		T68	1		T87	1
all_values[7]	auto[0]	auto[1]	auto[0]	61	1			T66	2		T67	2		T68	1
all_values[7]	auto[0]	auto[1]	auto[1]	39	1			T67	1		T68	1		T157	1
all_values[7]	auto[1]	auto[0]	auto[1]	100	1			T66	1		T67	1		T68	3
all_values[7]	auto[1]	auto[1]	auto[1]	96	1			T66	3		T67	3		T68	2
all_values[8]	auto[0]	auto[0]	auto[0]	91	1			T66	1		T68	5		T88	1
all_values[8]	auto[0]	auto[0]	auto[1]	40	1			T66	2		T68	2		T181	3
all_values[8]	auto[0]	auto[1]	auto[0]	64	1			T66	1		T67	6		T88	1
all_values[8]	auto[0]	auto[1]	auto[1]	41	1			T66	1		T88	1		T156	1
all_values[8]	auto[1]	auto[0]	auto[1]	89	1			T66	2		T67	1		T68	2
all_values[8]	auto[1]	auto[1]	auto[1]	91	1			T67	3		T68	1		T88	1
all_values[9]	auto[0]	auto[0]	auto[0]	100	1			T66	3		T67	2		T68	4
all_values[9]	auto[0]	auto[0]	auto[1]	44	1			T67	3		T68	1		T88	1
all_values[9]	auto[0]	auto[1]	auto[0]	59	1			T66	1		T67	1		T87	1
all_values[9]	auto[0]	auto[1]	auto[1]	39	1			T67	1		T68	1		T88	1
all_values[9]	auto[1]	auto[0]	auto[1]	111	1			T66	2		T67	2		T68	2
all_values[9]	auto[1]	auto[1]	auto[1]	63	1			T66	1		T67	1		T68	2
all_values[10]	auto[0]	auto[0]	auto[0]	81	1			T66	3		T67	4		T88	2
all_values[10]	auto[0]	auto[0]	auto[1]	44	1			T66	1		T156	1		T87	2
all_values[10]	auto[0]	auto[1]	auto[0]	67	1			T67	3		T68	1		T157	2
all_values[10]	auto[0]	auto[1]	auto[1]	36	1			T67	1		T68	3		T88	1
all_values[10]	auto[1]	auto[0]	auto[1]	96	1			T67	1		T68	1		T156	2
all_values[10]	auto[1]	auto[1]	auto[1]	92	1			T66	3		T67	1		T68	5
all_values[11]	auto[0]	auto[0]	auto[0]	123	1			T66	1		T67	1		T68	4
all_values[11]	auto[0]	auto[1]	auto[0]	111	1			T66	2		T67	3		T68	1
all_values[11]	auto[1]	auto[0]	auto[1]	100	1			T66	1		T67	1		T68	3
all_values[11]	auto[1]	auto[1]	auto[1]	82	1			T66	3		T67	5		T68	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal