Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67653

1

T4

396

T16

419

T6

944

auto[1]

24979

1

T4

55

T5

14

T6

103

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67759

1

T4

313

T5

14

T16

288

auto[1]

24873

1

T4

138

T16

131

T6

358

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	47565	1			T4	229		T5	14		T16	217
others[1]	7744	1			T4	35		T16	39		T6	83
others[2]	7933	1			T4	48		T16	39		T6	76
others[3]	8689	1			T4	54		T16	34		T6	103
interest[1]	5147	1			T4	14		T16	19		T6	53
interest[4]	31047	1			T4	156		T5	14		T16	143
interest[64]	15554	1			T4	71		T16	71		T6	168

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	21819	1			T4	132		T16	144		T6	317
auto[0]	auto[0]	others[1]	3580	1			T4	20		T16	28		T6	47
auto[0]	auto[0]	others[2]	3769	1			T4	27		T16	28		T6	50
auto[0]	auto[0]	others[3]	4018	1			T4	33		T16	27		T6	55
auto[0]	auto[0]	interest[1]	2364	1			T4	9		T16	9		T6	28
auto[0]	auto[0]	interest[4]	14109	1			T4	90		T16	101		T6	211
auto[0]	auto[0]	interest[64]	7230	1			T4	37		T16	52		T6	89
auto[0]	auto[1]	others[0]	12943	1			T4	29		T5	14		T6	52
auto[0]	auto[1]	others[1]	2080	1			T4	1		T6	8		T42	10
auto[0]	auto[1]	others[2]	2089	1			T4	9		T6	7		T42	12
auto[0]	auto[1]	others[3]	2299	1			T4	9		T6	9		T42	8
auto[0]	auto[1]	interest[1]	1362	1			T4	1		T6	6		T42	8
auto[0]	auto[1]	interest[4]	8607	1			T4	23		T5	14		T6	31
auto[0]	auto[1]	interest[64]	4206	1			T4	6		T6	21		T42	13
auto[1]	auto[0]	others[0]	12803	1			T4	68		T16	73		T6	195
auto[1]	auto[0]	others[1]	2084	1			T4	14		T16	11		T6	28
auto[1]	auto[0]	others[2]	2075	1			T4	12		T16	11		T6	19
auto[1]	auto[0]	others[3]	2372	1			T4	12		T16	7		T6	39
auto[1]	auto[0]	interest[1]	1421	1			T4	4		T16	10		T6	19
auto[1]	auto[0]	interest[4]	8331	1			T4	43		T16	42		T6	130
auto[1]	auto[0]	interest[64]	4118	1			T4	28		T16	19		T6	58

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal