Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::all_modes_cg

Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	0	5	100.00
Crosses	5	0	5	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_tpm_enabled	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	5	0	5	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[GenericMode]	6236068	1			T2	12521		T3	8215		T9	20297
auto[FlashMode]	93610	1			T4	451		T5	14		T16	419
auto[PassthroughMode]	64192	1			T12	30		T11	40		T18	16

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Summary for Variable cp_tpm_enabled

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tpm_enabled

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6105258

1

T2

12521

T3

8215

T9

20297

auto[1]

288612

1

T4

451

T5

14

T16

419

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Summary for Cross cr_all

Samples crossed: cp_mode cp_tpm_enabled

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	5	0	5	100.00
Automatically Generated Cross Bins	5	0	5	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_mode	cp_tpm_enabled	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[GenericMode]	auto[0]	6077723	1			T2	12521		T3	8215		T9	20297
auto[FlashMode]	auto[0]	7738	1			T173	26		T177	28		T205	213
auto[FlashMode]	auto[1]	85872	1			T4	451		T5	14		T16	419
auto[PassthroughMode]	auto[0]	19797	1			T12	30		T11	40		T18	16
auto[PassthroughMode]	auto[1]	44395	1			T7	481		T8	419		T20	474

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded