Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151585416	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

17779605

1

T1

14

T4

1

T2

13378

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	158001227	1			T1	5		T4	1		T2	851778
values[0x0]	5682846	1			T1	7		T2	4868		T3	58
values[0x1]	5680948	1			T1	6		T2	4794		T3	42

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	77335079	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

92029942

1

T1

15

T4

1

T2

437063

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	627822	1			T2	3263		T5	6		T9	5071
valid_sources[0x01]	643330	1			T2	3236		T5	2		T9	310
valid_sources[0x02]	656497	1			T2	3119		T9	1773		T16	893
valid_sources[0x03]	683763	1			T2	3335		T9	8634		T16	951
valid_sources[0x04]	631294	1			T2	3366		T9	200		T16	935
valid_sources[0x05]	621066	1			T2	3866		T9	59		T16	893
valid_sources[0x06]	636977	1			T2	3287		T9	1410		T16	927
valid_sources[0x07]	711123	1			T2	3258		T9	204		T16	922
valid_sources[0x08]	679323	1			T2	3601		T9	748		T16	880
valid_sources[0x09]	672373	1			T2	3258		T3	2		T9	7748
valid_sources[0x0a]	692837	1			T1	1		T2	3276		T3	2
valid_sources[0x0b]	678372	1			T2	3539		T9	512		T16	939
valid_sources[0x0c]	658722	1			T1	1		T2	3492		T3	1
valid_sources[0x0d]	655843	1			T2	3420		T3	1		T9	221
valid_sources[0x0e]	686896	1			T2	3455		T5	3835		T9	221
valid_sources[0x0f]	615461	1			T2	3350		T9	1500		T16	1006
valid_sources[0x10]	644889	1			T2	3135		T9	1235		T16	928
valid_sources[0x11]	679703	1			T2	3271		T9	2282		T16	958
valid_sources[0x12]	677778	1			T2	3192		T9	2356		T16	950
valid_sources[0x13]	655909	1			T2	3349		T9	3262		T16	997
valid_sources[0x14]	634437	1			T2	3445		T9	2544		T16	980
valid_sources[0x15]	659512	1			T2	3144		T3	4		T9	4193
valid_sources[0x16]	633004	1			T2	3129		T9	1276		T16	946
valid_sources[0x17]	657548	1			T2	3171		T9	1372		T16	946
valid_sources[0x18]	650736	1			T1	1		T2	3319		T3	3
valid_sources[0x19]	633431	1			T2	3193		T9	40		T16	885
valid_sources[0x1a]	689255	1			T2	3060		T9	186		T16	902
valid_sources[0x1b]	647046	1			T2	3367		T9	3754		T16	931
valid_sources[0x1c]	619122	1			T2	3333		T9	222		T16	1014
valid_sources[0x1d]	655370	1			T2	3528		T9	4017		T16	893
valid_sources[0x1e]	637683	1			T2	3384		T9	182		T16	875
valid_sources[0x1f]	683041	1			T2	3214		T9	727		T16	952
valid_sources[0x20]	652353	1			T2	3631		T9	8918		T16	973
valid_sources[0x21]	609031	1			T2	3644		T9	2208		T16	952
valid_sources[0x22]	669152	1			T2	3741		T9	756		T16	913
valid_sources[0x23]	629831	1			T2	3650		T5	105		T9	8799
valid_sources[0x24]	668747	1			T2	3437		T3	1		T9	896
valid_sources[0x25]	671567	1			T2	3378		T3	5		T9	298
valid_sources[0x26]	615658	1			T2	3476		T3	7		T9	15
valid_sources[0x27]	649128	1			T2	3599		T3	2		T9	62
valid_sources[0x28]	643210	1			T2	3226		T5	24		T9	3178
valid_sources[0x29]	666541	1			T2	3485		T3	1		T9	2918
valid_sources[0x2a]	683483	1			T2	3452		T9	5510		T16	940
valid_sources[0x2b]	658139	1			T2	3442		T9	6		T16	961
valid_sources[0x2c]	656039	1			T2	3295		T9	4397		T16	900
valid_sources[0x2d]	659567	1			T2	3430		T9	203		T10	19
valid_sources[0x2e]	672563	1			T2	3412		T5	248		T9	5632
valid_sources[0x2f]	611981	1			T2	3310		T5	4		T9	109
valid_sources[0x30]	630047	1			T2	3077		T3	5		T9	4
valid_sources[0x31]	641148	1			T2	3236		T9	24		T10	38
valid_sources[0x32]	668532	1			T2	3504		T9	15425		T16	972
valid_sources[0x33]	645972	1			T2	3604		T9	10		T16	925
valid_sources[0x34]	675898	1			T2	3136		T3	6		T9	130
valid_sources[0x35]	664908	1			T1	1		T2	3597		T9	11017
valid_sources[0x36]	650850	1			T2	3328		T9	10228		T10	7
valid_sources[0x37]	664675	1			T2	3655		T9	6331		T16	931
valid_sources[0x38]	624795	1			T2	3623		T9	8		T16	915
valid_sources[0x39]	643207	1			T2	3471		T9	26		T16	987
valid_sources[0x3a]	647293	1			T2	3641		T9	549		T16	899
valid_sources[0x3b]	654769	1			T2	2916		T9	6152		T16	998
valid_sources[0x3c]	742345	1			T2	3388		T5	9		T9	728
valid_sources[0x3d]	679456	1			T2	3326		T3	2		T9	1780
valid_sources[0x3e]	630701	1			T2	3202		T9	5798		T10	43
valid_sources[0x3f]	709184	1			T2	3290		T9	83		T16	951
valid_sources[0x40]	638512	1			T2	3142		T3	4		T5	7
valid_sources[0x41]	612488	1			T2	3195		T16	876		T22	7
valid_sources[0x42]	621554	1			T2	3165		T3	4		T9	1785
valid_sources[0x43]	656179	1			T2	3004		T9	351		T16	887
valid_sources[0x44]	677468	1			T2	3148		T5	5		T9	9952
valid_sources[0x45]	642109	1			T2	3171		T5	53		T9	1459
valid_sources[0x46]	602085	1			T2	3134		T9	3089		T16	932
valid_sources[0x47]	647903	1			T2	3157		T9	2698		T16	902
valid_sources[0x48]	636125	1			T2	3116		T3	1		T9	3869
valid_sources[0x49]	674772	1			T2	3725		T3	2		T9	4751
valid_sources[0x4a]	687400	1			T2	3334		T9	10380		T16	920
valid_sources[0x4b]	693882	1			T2	3408		T3	2		T9	11410
valid_sources[0x4c]	1153221	1			T2	3121		T3	4		T9	5046
valid_sources[0x4d]	666870	1			T2	3030		T5	17		T9	7
valid_sources[0x4e]	650032	1			T2	3218		T5	6713		T9	3485
valid_sources[0x4f]	652785	1			T2	3378		T3	2		T9	3644
valid_sources[0x50]	668492	1			T2	3585		T5	1		T9	2875
valid_sources[0x51]	650773	1			T2	3609		T9	2653		T16	890
valid_sources[0x52]	625015	1			T2	3473		T9	3		T16	932
valid_sources[0x53]	628901	1			T2	3324		T9	137		T16	897
valid_sources[0x54]	677147	1			T2	3198		T9	5456		T16	904
valid_sources[0x55]	654327	1			T2	3296		T9	282		T16	940
valid_sources[0x56]	616086	1			T2	3222		T9	155		T16	967
valid_sources[0x57]	660914	1			T2	3121		T9	4625		T16	957
valid_sources[0x58]	649518	1			T2	3457		T9	138		T16	934
valid_sources[0x59]	656663	1			T2	3384		T5	695		T9	2344
valid_sources[0x5a]	634526	1			T1	1		T2	3322		T9	32
valid_sources[0x5b]	656784	1			T2	3429		T9	3874		T16	981
valid_sources[0x5c]	649723	1			T2	3253		T3	1		T9	1779
valid_sources[0x5d]	662447	1			T1	1		T2	3573		T3	2
valid_sources[0x5e]	646240	1			T2	3263		T3	5		T5	8
valid_sources[0x5f]	692576	1			T2	3538		T9	25		T16	883
valid_sources[0x60]	660834	1			T2	3404		T9	5330		T16	959
valid_sources[0x61]	668677	1			T2	3502		T9	73		T16	957
valid_sources[0x62]	700803	1			T1	1		T2	3311		T9	1208
valid_sources[0x63]	637584	1			T2	3553		T3	1		T9	22
valid_sources[0x64]	694108	1			T2	3465		T9	31		T16	934
valid_sources[0x65]	640395	1			T2	3080		T9	7		T16	886
valid_sources[0x66]	651592	1			T2	3148		T3	1		T9	42
valid_sources[0x67]	675371	1			T2	3187		T3	1		T9	1135
valid_sources[0x68]	658287	1			T2	3452		T9	112		T16	948
valid_sources[0x69]	630503	1			T2	3257		T9	1469		T16	959
valid_sources[0x6a]	655638	1			T2	3664		T5	3045		T9	2104
valid_sources[0x6b]	622649	1			T2	3501		T3	3		T9	11
valid_sources[0x6c]	662671	1			T2	3232		T9	1596		T16	943
valid_sources[0x6d]	651952	1			T2	3269		T9	91		T16	912
valid_sources[0x6e]	1041928	1			T2	3407		T3	1		T9	6855
valid_sources[0x6f]	628287	1			T2	3363		T3	3		T9	2038
valid_sources[0x70]	626643	1			T2	3352		T9	4250		T16	937
valid_sources[0x71]	628393	1			T2	3291		T9	465		T16	941
valid_sources[0x72]	655533	1			T2	3578		T9	1823		T16	895
valid_sources[0x73]	637178	1			T2	3515		T9	109		T16	970
valid_sources[0x74]	653247	1			T2	3600		T3	2		T5	395
valid_sources[0x75]	643675	1			T2	3489		T9	6		T16	915
valid_sources[0x76]	723759	1			T2	3185		T9	4928		T16	988
valid_sources[0x77]	642513	1			T2	3126		T9	12		T16	952
valid_sources[0x78]	639719	1			T2	3348		T9	9573		T16	957
valid_sources[0x79]	668290	1			T2	3631		T3	1		T9	11955
valid_sources[0x7a]	658582	1			T2	3741		T9	89		T16	958
valid_sources[0x7b]	659139	1			T2	3432		T3	1		T9	2628
valid_sources[0x7c]	648759	1			T2	3370		T9	7167		T16	856
valid_sources[0x7d]	664152	1			T2	3026		T5	1		T9	1166
valid_sources[0x7e]	637717	1			T1	1		T2	3230		T5	110
valid_sources[0x7f]	669225	1			T2	3250		T9	6913		T16	963
valid_sources[0x80]	769530	1			T2	3203		T9	1437		T16	977

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6728044

1

T1

2

T4

1

T2

3718

values[0x0]

all_enables

biggest_size

5536651

1

T1

7

T2

4867

T3

58

values[0x1]

all_enables

biggest_size

5514910

1

T1

5

T2

4793

T3

42