Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

151608105

1

T1

4

T2

848062

T5

14749

full_word

17778737

1

T1

14

T4

1

T2

13378

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	169386452	1			T1	18		T4	1		T2	861440
auto[TlIntgErrCmd]	139	1			T87	5		T106	6		T139	9
auto[TlIntgErrData]	117	1			T87	3		T106	8		T139	11
auto[TlIntgErrBoth]	134	1			T87	2		T106	6		T139	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158001699

1

T1

5

T4

1

T2

851778

auto[1]

11385143

1

T1

13

T2

9662

T5

1563

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	151273432	1			T1	3		T2	848060		T5	14746
auto[TlIntgErrNone]	partial	auto[1]	334318	1			T1	1		T2	2		T5	3
auto[TlIntgErrNone]	full_word	auto[0]	6728081	1			T1	2		T4	1		T2	3718
auto[TlIntgErrNone]	full_word	auto[1]	11050621	1			T1	12		T2	9660		T5	1560
auto[TlIntgErrCmd]	partial	auto[0]	60	1			T87	3		T106	2		T139	4
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T87	1		T106	2		T139	5
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T87	1		T106	1		T221	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T106	1		T168	1		T221	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T106	3		T139	6		T168	2
auto[TlIntgErrData]	partial	auto[1]	52	1			T87	2		T106	5		T139	3
auto[TlIntgErrData]	full_word	auto[0]	9	1			T87	1		T139	1		T168	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T139	1		T222	2		T223	1
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T87	2		T106	4		T139	3
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T106	1		T139	7		T168	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T176	1		T170	1		T221	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T106	1		T168	1		T221	1