Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1572	1572	0	0
OutputsKnown_A	1866834928	1866703956	0	0
gen_no_flops.OutputDelay_A	1866834928	1866703956	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1572	1572	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1866834928	1866703956	0	0
T1	1264	1166	0	0
T2	102476	102475	0	0
T3	2384	2319	0	0
T4	662	573	0	0
T5	152086	151989	0	0
T9	995239	995222	0	0
T10	32446	32356	0	0
T16	182444	182438	0	0
T17	15398	15324	0	0
T22	661009	660953	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1866834928	1866703956	0	0
T1	1264	1166	0	0
T2	102476	102475	0	0
T3	2384	2319	0	0
T4	662	573	0	0
T5	152086	151989	0	0
T9	995239	995222	0	0
T10	32446	32356	0	0
T16	182444	182438	0	0
T17	15398	15324	0	0
T22	661009	660953	0	0