Unified Coverage Report :: Module :: spid_status

Module : spid_status

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.82	100.00	100.00		100.00	94.12	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_status	98.82	100.00	100.00		100.00	94.12	100.00

---

Module Instance : tb.dut.u_spid_status

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.82	100.00	100.00		100.00	94.12	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.19	100.00	86.84		100.00	94.12	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_stage_to_commit	100.00	100.00				100.00
u_sw_status_update_sync	93.44	100.00	80.00			93.75	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spid_status

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
ALWAYS	140	6	6	100.00
ALWAYS	151	8	8	100.00
ALWAYS	164	4	4	100.00
CONT_ASSIGN	182	1	1	100.00
ALWAYS	211	4	4	100.00
ALWAYS	224	5	5	100.00
ALWAYS	238	3	3	100.00
ALWAYS	246	11	11	100.00
CONT_ASSIGN	267	1	1	100.00
ALWAYS	274	3	3	100.00
ALWAYS	279	12	12	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
73	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	1	1
145	1	1
			MISSING_ELSE
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
			MISSING_ELSE
164	1	1
165	1	1
166	1	1
167	1	1
			MISSING_ELSE
182	1	1
211	1	1
212	1	1
213	1	1
214	1	1
			MISSING_ELSE
224	1	1
225	1	1
226	1	1
228	1	1
229	1	1
238	1	1
239	1	1
241	1	1
246	1	1
248	1	1
250	1	1
252	1	1
253	1	1
254	1	1
			MISSING_ELSE
257	1	1
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
267	1	1
274	2	2
275	1	1
279	1	1
281	1	1
282	1	1
284	1	1
286	1	1
288	1	1
289	1	1
291	1	1
292	1	1
			MISSING_ELSE
297	1	1
305	2	2
			MISSING_ELSE

---

Cond Coverage for Module : spid_status

	Total	Covered	Percent
Conditions	13	13	100.00
Logical	13	13	100.00
Non-Logical	0	0
Event	0	0

 LINE       142
 EXPRESSION (sck_sw_we && (sck_sw_status[BitBusy] == 1'b0))
             ----1----    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T23,T13,T14
1	1	Covered	T23,T13,T14

 LINE       142
 SUB-EXPRESSION (sck_sw_status[BitBusy] == 1'b0)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T23,T13,T14
1	Covered	T1,T2,T5

 LINE       253
 EXPRESSION (cmd_info_idx_i == 5'(StatusCmdIdx[i]))
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T17,T6,T7
1	Covered	T17,T6,T7

 LINE       267
 EXPRESSION ((st_q == StIdle) ? sck_status_committed[(8 * byte_sel_d)+:8] : sck_status_committed[(8 * byte_sel_q)+:8])
             --------1-------

-1-	Status	Tests
0	Covered	T17,T6,T7
1	Covered	T1,T4,T2

 LINE       267
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       288
 EXPRESSION (sel_dp_i == DpReadStatus)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T17,T6,T7

---

FSM Coverage for Module : spid_status

Summary for FSM :: byte_sel_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: byte_sel_q

---

states	Line No.	Covered	Tests
'h0	250	Covered	T1,T4,T2
'h1	259	Covered	T17,T6,T7
'h2	260	Covered	T17,T6,T7

transitions	Line No.	Covered	Tests
'h0->'h1	259	Covered	T17,T6,T7
'h1->'h0	250	Covered	T6,T7,T8
'h1->'h2	260	Covered	T17,T6,T7
'h2->'h0	250	Covered	T17,T6,T7

---

Branch Coverage for Module : spid_status

	Line No.	Total	Covered	Percent
Branches		34	32	94.12
TERNARY	267	2	2	100.00
IF	140	4	4	100.00
IF	151	5	5	100.00
IF	164	3	3	100.00
IF	211	3	3	100.00
IF	224	2	2	100.00
IF	238	2	2	100.00
IF	248	6	5	83.33
IF	274	2	2	100.00
CASE	286	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	267	((st_q == StIdle)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T17,T6,T7

	LineNo.	Expression
-1-:	140	if ((!sys_rst_ni))
-2-:	142	if ((sck_sw_we && (sck_sw_status[BitBusy] == 1'b0)))
-3-:	144	if (inclk_busy_set_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T23,T13,T14
0	0	1	Covered	T6,T7,T8
0	0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	151	if ((!sys_rst_ni))
-2-:	153	if (inclk_we_set_i)
-3-:	155	if (inclk_we_clr_i)
-4-:	157	if (sck_sw_we)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T4,T2
0	1	-	-	Covered	T29,T6,T7
0	0	1	-	Covered	T29,T6,T7
0	0	0	1	Covered	T23,T13,T14
0	0	0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	164	if ((!sys_rst_ni))
-2-:	166	if (sck_sw_we)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T2
0	1	Covered	T23,T13,T14
0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	211	if ((!sys_rst_ni))
-2-:	213	if (sys_csb_deasserted_pulse_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T2
0	1	Covered	T2,T5,T9
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	224	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T2,T5,T9

	LineNo.	Expression
-1-:	238	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T2,T5,T9

	LineNo.	Expression
-1-:	248	if (byte_sel_update)
-2-:	257	if (byte_sel_inc)
-3-:	258	case (byte_sel_q)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T17,T6,T7
0	1	2'b00	Covered	T17,T6,T7
0	1	2'b01	Covered	T17,T6,T7
0	1	2'b10	Covered	T17,T6,T7
0	1	default	Not Covered
0	0	-	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	274	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T2,T5,T9

	LineNo.	Expression
-1-:	286	case (st_q)
-2-:	288	if ((sel_dp_i == DpReadStatus))
-3-:	305	if (outclk_p2s_sent_i)

Branches:

-1-	-2-	-3-	Status	Tests
StIdle	1	-	Covered	T17,T6,T7
StIdle	0	-	Covered	T1,T4,T2
StActive	-	1	Covered	T17,T6,T7
StActive	-	0	Covered	T17,T6,T7
default	-	-	Not Covered

---

Assert Coverage for Module : spid_status

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusyBitZero_A	1572	1572	0	0

BusyBitZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1572	1572	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0