Unified Coverage Report :: Module :: spi_s2p

Module : spi_s2p

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.85	100.00	85.71			73.68	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_s2p.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s2p	89.85	100.00	85.71			73.68	100.00

---

Module Instance : tb.dut.u_s2p

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.85	100.00	85.71			73.68	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.85	100.00	85.71			73.68	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_s2p

	Line No.	Total	Covered	Percent
TOTAL		20	20	100.00
ALWAYS	43	4	4	100.00
ALWAYS	63	3	3	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	75	8	8	100.00
ALWAYS	91	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_s2p.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_s2p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	1	1
45	1	1
49	1	1
53	1	1
63	1	1
64	1	1
66	1	1
71	1	1
75	1	1
76	1	1
77	1	1
78	1	1
80	1	1
81	1	1
82	1	1
83	1	1
91	1	1
92	1	1
93	1	1
94	1	1

---

Cond Coverage for Module : spi_s2p

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (order_i ? ({s_i[0], data_q[7:1]}) : ({data_q[6:0], s_i[0]}))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T9,T10

 LINE       49
 EXPRESSION (order_i ? ({s_i[1:0], data_q[7:2]}) : ({data_q[5:0], s_i[1:0]}))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Not Covered

 LINE       53
 EXPRESSION (order_i ? ({s_i[3:0], data_q[7:4]}) : ({data_q[3:0], s_i[3:0]}))
             ---1---

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Not Covered

 LINE       77
 EXPRESSION (cnt == '0)
            -----1-----

-1-	Status	Tests
0	Covered	T2,T5,T9
1	Covered	T2,T5,T9

 LINE       92
 EXPRESSION (cnt == 3'b0)
            ------1------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T5,T9

 LINE       93
 EXPRESSION (cnt == 3'b1)
            ------1------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       94
 EXPRESSION (cnt == 3'h3)
            ------1------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T14,T15,T6

---

Branch Coverage for Module : spi_s2p

	Line No.	Total	Covered	Percent
Branches		19	14	73.68
CASE	43	7	4	57.14
IF	63	2	2	100.00
IF	75	6	5	83.33
CASE	91	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_s2p.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_s2p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	43	case (io_mode_i)
-2-:	45	(order_i) ? 
-3-:	49	(order_i) ? 
-4-:	53	(order_i) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
SingleIO	1	-	-	Covered	T5,T9,T10
SingleIO	0	-	-	Covered	T1,T4,T2
DualIO	-	1	-	Not Covered
DualIO	-	0	-	Covered	T11,T12,T13
QuadIO	-	-	1	Not Covered
QuadIO	-	-	0	Covered	T13,T14,T15
default	-	-	-	Not Covered

	LineNo.	Expression
-1-:	63	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T2,T5,T9

	LineNo.	Expression
-1-:	75	if ((!rst_ni))
-2-:	77	if ((cnt == '0))
-3-:	80	case (io_mode_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T9
0	0	SingleIO	Covered	T2,T5,T9
0	0	DualIO	Covered	T11,T12,T13
0	0	QuadIO	Covered	T13,T14,T15
0	0	default	Not Covered

	LineNo.	Expression
-1-:	91	case (io_mode_i)

Branches:

-1-	Status	Tests
SingleIO	Covered	T1,T4,T2
DualIO	Covered	T11,T12,T13
QuadIO	Covered	T13,T14,T15
default	Not Covered

---

Assert Coverage for Module : spi_s2p

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoModeDefault_A	346089440	52972	0	0

IoModeDefault_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346089440	52972	0	0
T2	118977	1	0	0
T5	44962	2	0	0
T9	148130	241	0	0
T10	2878	8	0	0
T16	344642	2	0	0
T17	31168	1	0	0
T18	413697	2	0	0
T19	411073	2	0	0
T20	3745	1	0	0
T21	0	2	0	0
T22	128596	0	0	0