Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_fwmode_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
92.53	100.00

tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
90.97	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T5,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T5
1	0	Covered	T2,T5,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T9
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T2

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	4716	4716	0	0
GntImpliesReady_A	2147483647	19643314	0	0
GntImpliesValid_A	2147483647	19643314	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	19643314	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	0	0	0
ReadyAndValidImplyGrant_A	2147483647	19643314	0	0
ReqAndReadyImplyGrant_A	2147483647	19643314	0	0
ReqImpliesValid_A	2147483647	19643314	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	717	0	2272
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	19643314	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2418	2320	0	0
T2	323928	323926	0	0
T3	2384	2319	0	0
T4	662	573	0	0
T5	349026	348927	0	0
T9	2138481	2129754	0	0
T10	67661	67562	0	0
T16	709522	709514	0	0
T17	77734	77660	0	0
T18	765074	765073	0	0
T19	684396	684395	0	0
T20	3745	72835	0	0
T21	0	776416	0	0
T22	918201	660953	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4716	4716	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0
T16	3	3	0	0
T17	3	3	0	0
T22	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19643314	0	0
T1	2418	4	0	0
T2	204951	14872	0	0
T3	2384	200	0	0
T4	662	0	0	0
T5	304064	5620	0	0
T6	721030	681	0	0
T7	199602	2939	0	0
T8	657146	6253	0	0
T9	1990351	119452	0	0
T10	64783	320	0	0
T16	364880	43080	0	0
T17	46566	1024	0	0
T18	351377	51712	0	0
T19	273323	51384	0	0
T20	0	416	0	0
T21	0	48526	0	0
T22	789605	0	0	0
T24	216196	0	0	0
T28	0	5558	0	0
T33	93196	0	0	0
T41	1473	0	0	0
T42	72955	0	0	0
T50	0	5412	0	0
T60	0	1334	0	0
T61	0	3539	0	0
T62	0	388	0	0
T63	0	1560	0	0
T64	19937	0	0	0
T65	385	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19643314	0	0
T1	2418	4	0	0
T2	204951	14872	0	0
T3	2384	200	0	0
T4	662	0	0	0
T5	304064	5620	0	0
T6	721030	681	0	0
T7	199602	2939	0	0
T8	657146	6253	0	0
T9	1990351	119452	0	0
T10	64783	320	0	0
T16	364880	43080	0	0
T17	46566	1024	0	0
T18	351377	51712	0	0
T19	273323	51384	0	0
T20	0	416	0	0
T21	0	48526	0	0
T22	789605	0	0	0
T24	216196	0	0	0
T28	0	5558	0	0
T33	93196	0	0	0
T41	1473	0	0	0
T42	72955	0	0	0
T50	0	5412	0	0
T60	0	1334	0	0
T61	0	3539	0	0
T62	0	388	0	0
T63	0	1560	0	0
T64	19937	0	0	0
T65	385	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2418	2320	0	0
T2	323928	323926	0	0
T3	2384	2319	0	0
T4	662	573	0	0
T5	349026	348927	0	0
T9	2138481	2129754	0	0
T10	67661	67562	0	0
T16	709522	709514	0	0
T17	77734	77660	0	0
T18	765074	765073	0	0
T19	684396	684395	0	0
T20	3745	72835	0	0
T21	0	776416	0	0
T22	918201	660953	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2418	2320	0	0
T2	323928	323926	0	0
T3	2384	2319	0	0
T4	662	573	0	0
T5	349026	348927	0	0
T9	2138481	2129754	0	0
T10	67661	67562	0	0
T16	709522	709514	0	0
T17	77734	77660	0	0
T18	765074	765073	0	0
T19	684396	684395	0	0
T20	3745	72835	0	0
T21	0	776416	0	0
T22	918201	660953	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19643314	0	0
T1	2418	4	0	0
T2	204951	14872	0	0
T3	2384	200	0	0
T4	662	0	0	0
T5	304064	5620	0	0
T6	721030	681	0	0
T7	199602	2939	0	0
T8	657146	6253	0	0
T9	1990351	119452	0	0
T10	64783	320	0	0
T16	364880	43080	0	0
T17	46566	1024	0	0
T18	351377	51712	0	0
T19	273323	51384	0	0
T20	0	416	0	0
T21	0	48526	0	0
T22	789605	0	0	0
T24	216196	0	0	0
T28	0	5558	0	0
T33	93196	0	0	0
T41	1473	0	0	0
T42	72955	0	0	0
T50	0	5412	0	0
T60	0	1334	0	0
T61	0	3539	0	0
T62	0	388	0	0
T63	0	1560	0	0
T64	19937	0	0	0
T65	385	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19643314	0	0
T1	2418	4	0	0
T2	204951	14872	0	0
T3	2384	200	0	0
T4	662	0	0	0
T5	304064	5620	0	0
T6	721030	681	0	0
T7	199602	2939	0	0
T8	657146	6253	0	0
T9	1990351	119452	0	0
T10	64783	320	0	0
T16	364880	43080	0	0
T17	46566	1024	0	0
T18	351377	51712	0	0
T19	273323	51384	0	0
T20	0	416	0	0
T21	0	48526	0	0
T22	789605	0	0	0
T24	216196	0	0	0
T28	0	5558	0	0
T33	93196	0	0	0
T41	1473	0	0	0
T42	72955	0	0	0
T50	0	5412	0	0
T60	0	1334	0	0
T61	0	3539	0	0
T62	0	388	0	0
T63	0	1560	0	0
T64	19937	0	0	0
T65	385	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19643314	0	0
T1	2418	4	0	0
T2	204951	14872	0	0
T3	2384	200	0	0
T4	662	0	0	0
T5	304064	5620	0	0
T6	721030	681	0	0
T7	199602	2939	0	0
T8	657146	6253	0	0
T9	1990351	119452	0	0
T10	64783	320	0	0
T16	364880	43080	0	0
T17	46566	1024	0	0
T18	351377	51712	0	0
T19	273323	51384	0	0
T20	0	416	0	0
T21	0	48526	0	0
T22	789605	0	0	0
T24	216196	0	0	0
T28	0	5558	0	0
T33	93196	0	0	0
T41	1473	0	0	0
T42	72955	0	0	0
T50	0	5412	0	0
T60	0	1334	0	0
T61	0	3539	0	0
T62	0	388	0	0
T63	0	1560	0	0
T64	19937	0	0	0
T65	385	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19643314	0	0
T1	2418	4	0	0
T2	204951	14872	0	0
T3	2384	200	0	0
T4	662	0	0	0
T5	304064	5620	0	0
T6	721030	681	0	0
T7	199602	2939	0	0
T8	657146	6253	0	0
T9	1990351	119452	0	0
T10	64783	320	0	0
T16	364880	43080	0	0
T17	46566	1024	0	0
T18	351377	51712	0	0
T19	273323	51384	0	0
T20	0	416	0	0
T21	0	48526	0	0
T22	789605	0	0	0
T24	216196	0	0	0
T28	0	5558	0	0
T33	93196	0	0	0
T41	1473	0	0	0
T42	72955	0	0	0
T50	0	5412	0	0
T60	0	1334	0	0
T61	0	3539	0	0
T62	0	388	0	0
T63	0	1560	0	0
T64	19937	0	0	0
T65	385	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	717	0	2272
T9	995112	7	0	1
T10	32337	0	0	1
T13	0	0	0	0
T16	182436	0	0	1
T17	31168	0	0	0
T18	351377	0	0	1
T19	273323	0	0	1
T22	128596	0	0	0
T26	0	0	0	0
T49	395705	2	0	1
T53	0	4	0	0
T66	606866	38	0	1
T67	0	4	0	1
T68	0	2	0	0
T69	0	3	0	0
T70	0	5	0	0
T71	0	1	0	0
T72	0	30	0	0
T73	606451	0	0	1
T74	0	0	0	0
T75	0	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2418	2320	0	0
T2	323928	323926	0	0
T3	2384	2319	0	0
T4	662	573	0	0
T5	349026	348927	0	0
T9	2138481	2129754	0	0
T10	67661	67562	0	0
T16	709522	709514	0	0
T17	77734	77660	0	0
T18	765074	765073	0	0
T19	684396	684395	0	0
T20	3745	72835	0	0
T21	0	776416	0	0
T22	918201	660953	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19643314	0	0
T1	2418	4	0	0
T2	204951	14872	0	0
T3	2384	200	0	0
T4	662	0	0	0
T5	304064	5620	0	0
T6	721030	681	0	0
T7	199602	2939	0	0
T8	657146	6253	0	0
T9	1990351	119452	0	0
T10	64783	320	0	0
T16	364880	43080	0	0
T17	46566	1024	0	0
T18	351377	51712	0	0
T19	273323	51384	0	0
T20	0	416	0	0
T21	0	48526	0	0
T22	789605	0	0	0
T24	216196	0	0	0
T28	0	5558	0	0
T33	93196	0	0	0
T41	1473	0	0	0
T42	72955	0	0	0
T50	0	5412	0	0
T60	0	1334	0	0
T61	0	3539	0	0
T62	0	388	0	0
T63	0	1560	0	0
T64	19937	0	0	0
T65	385	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T9
1	0	Unreachable
1	1	Covered	T6,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T6,T7,T8
0	0	1	Unreachable
0	0	0	Covered	T2,T5,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	346089440	301921157	0	0
CheckNGreaterZero_A	1572	1572	0	0
GntImpliesReady_A	346089440	553404	0	0
GntImpliesValid_A	346089440	553404	0	0
GrantKnown_A	346089440	301921157	0	0
IdxKnown_A	346089440	301921157	0	0
IndexIsCorrect_A	346089440	553404	0	0
LockArbDecision_A	346089440	0	0	0
NoReadyValidNoGrant_A	346089440	0	0	0
ReadyAndValidImplyGrant_A	346089440	553404	0	0
ReqAndReadyImplyGrant_A	346089440	553404	0	0
ReqImpliesValid_A	346089440	553404	0	0
ReqStaysHighUntilGranted0_M	346089440	0	0	0
RoundRobin_A	346089440	0	0	0
ValidKnown_A	346089440	301921157	0	0
gen_data_port_assertion.DataFlow_A	346089440	553404	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346089440	301921157	0	0
T2	118977	118976	0	0
T5	44962	44960	0	0
T9	148130	139420	0	0
T10	2878	2869	0	0
T16	344642	344640	0	0
T17	31168	31168	0	0
T18	413697	413696	0	0
T19	411073	411072	0	0
T20	3745	3744	0	0
T21	0	776416	0	0
T22	128596	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1572	1572	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346089440	553404	0	0
T6	721030	681	0	0
T7	199602	2939	0	0
T8	657146	6253	0	0
T24	216196	0	0	0
T28	0	5558	0	0
T30	0	534	0	0
T33	93196	0	0	0
T41	1473	0	0	0
T42	72955	0	0	0
T50	154700	5412	0	0
T60	0	1334	0	0
T61	0	3539	0	0
T62	0	388	0	0
T63	0	1560	0	0
T64	19937	0	0	0
T65	385	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346089440	553404	0	0
T6	721030	681	0	0
T7	199602	2939	0	0
T8	657146	6253	0	0
T24	216196	0	0	0
T28	0	5558	0	0
T30	0	534	0	0
T33	93196	0	0	0
T41	1473	0	0	0
T42	72955	0	0	0
T50	154700	5412	0	0
T60	0	1334	0	0
T61	0	3539	0	0
T62	0	388	0	0
T63	0	1560	0	0
T64	19937	0	0	0
T65	385	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346089440	301921157	0	0
T2	118977	118976	0	0
T5	44962	44960	0	0
T9	148130	139420	0	0
T10	2878	2869	0	0
T16	344642	344640	0	0
T17	31168	31168	0	0
T18	413697	413696	0	0
T19	411073	411072	0	0
T20	3745	3744	0	0
T21	0	776416	0	0
T22	128596	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346089440	301921157	0	0
T2	118977	118976	0	0
T5	44962	44960	0	0
T9	148130	139420	0	0
T10	2878	2869	0	0
T16	344642	344640	0	0
T17	31168	31168	0	0
T18	413697	413696	0	0
T19	411073	411072	0	0
T20	3745	3744	0	0
T21	0	776416	0	0
T22	128596	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346089440	553404	0	0
T6	721030	681	0	0
T7	199602	2939	0	0
T8	657146	6253	0	0
T24	216196	0	0	0
T28	0	5558	0	0
T30	0	534	0	0
T33	93196	0	0	0
T41	1473	0	0	0
T42	72955	0	0	0
T50	154700	5412	0	0
T60	0	1334	0	0
T61	0	3539	0	0
T62	0	388	0	0
T63	0	1560	0	0
T64	19937	0	0	0
T65	385	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346089440	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346089440	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346089440	553404	0	0
T6	721030	681	0	0
T7	199602	2939	0	0
T8	657146	6253	0	0
T24	216196	0	0	0
T28	0	5558	0	0
T30	0	534	0	0
T33	93196	0	0	0
T41	1473	0	0	0
T42	72955	0	0	0
T50	154700	5412	0	0
T60	0	1334	0	0
T61	0	3539	0	0
T62	0	388	0	0
T63	0	1560	0	0
T64	19937	0	0	0
T65	385	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346089440	553404	0	0
T6	721030	681	0	0
T7	199602	2939	0	0
T8	657146	6253	0	0
T24	216196	0	0	0
T28	0	5558	0	0
T30	0	534	0	0
T33	93196	0	0	0
T41	1473	0	0	0
T42	72955	0	0	0
T50	154700	5412	0	0
T60	0	1334	0	0
T61	0	3539	0	0
T62	0	388	0	0
T63	0	1560	0	0
T64	19937	0	0	0
T65	385	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346089440	553404	0	0
T6	721030	681	0	0
T7	199602	2939	0	0
T8	657146	6253	0	0
T24	216196	0	0	0
T28	0	5558	0	0
T30	0	534	0	0
T33	93196	0	0	0
T41	1473	0	0	0
T42	72955	0	0	0
T50	154700	5412	0	0
T60	0	1334	0	0
T61	0	3539	0	0
T62	0	388	0	0
T63	0	1560	0	0
T64	19937	0	0	0
T65	385	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	346089440	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346089440	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346089440	301921157	0	0
T2	118977	118976	0	0
T5	44962	44960	0	0
T9	148130	139420	0	0
T10	2878	2869	0	0
T16	344642	344640	0	0
T17	31168	31168	0	0
T18	413697	413696	0	0
T19	411073	411072	0	0
T20	3745	3744	0	0
T21	0	776416	0	0
T22	128596	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346089440	553404	0	0
T6	721030	681	0	0
T7	199602	2939	0	0
T8	657146	6253	0	0
T24	216196	0	0	0
T28	0	5558	0	0
T30	0	534	0	0
T33	93196	0	0	0
T41	1473	0	0	0
T42	72955	0	0	0
T50	154700	5412	0	0
T60	0	1334	0	0
T61	0	3539	0	0
T62	0	388	0	0
T63	0	1560	0	0
T64	19937	0	0	0
T65	385	0	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1866834928	1866703956	0	0
CheckNGreaterZero_A	1572	1572	0	0
GntImpliesReady_A	1866834928	10691368	0	0
GntImpliesValid_A	1866834928	10691368	0	0
GrantKnown_A	1866834928	1866703956	0	0
IdxKnown_A	1866834928	1866703956	0	0
IndexIsCorrect_A	1866834928	10691368	0	0
LockArbDecision_A	1866834928	0	0	0
NoReadyValidNoGrant_A	1866834928	0	0	0
ReadyAndValidImplyGrant_A	1866834928	10691368	0	0
ReqAndReadyImplyGrant_A	1866834928	10691368	0	0
ReqImpliesValid_A	1866834928	10691368	0	0
ReqStaysHighUntilGranted0_M	1866834928	0	0	0
RoundRobin_A	1866834928	0	0	1572
ValidKnown_A	1866834928	1866703956	0	0
gen_data_port_assertion.DataFlow_A	1866834928	10691368	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1866834928	1866703956	0	0
T1	1264	1166	0	0
T2	102476	102475	0	0
T3	2384	2319	0	0
T4	662	573	0	0
T5	152086	151989	0	0
T9	995239	995222	0	0
T10	32446	32356	0	0
T16	182444	182438	0	0
T17	15398	15324	0	0
T22	661009	660953	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1572	1572	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1866834928	10691368	0	0
T1	1264	2	0	0
T2	102476	7436	0	0
T3	2384	200	0	0
T4	662	0	0	0
T5	152086	2810	0	0
T9	995239	59726	0	0
T10	32446	160	0	0
T16	182444	21540	0	0
T17	15398	1024	0	0
T18	0	25856	0	0
T19	0	25692	0	0
T22	661009	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1866834928	10691368	0	0
T1	1264	2	0	0
T2	102476	7436	0	0
T3	2384	200	0	0
T4	662	0	0	0
T5	152086	2810	0	0
T9	995239	59726	0	0
T10	32446	160	0	0
T16	182444	21540	0	0
T17	15398	1024	0	0
T18	0	25856	0	0
T19	0	25692	0	0
T22	661009	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1866834928	1866703956	0	0
T1	1264	1166	0	0
T2	102476	102475	0	0
T3	2384	2319	0	0
T4	662	573	0	0
T5	152086	151989	0	0
T9	995239	995222	0	0
T10	32446	32356	0	0
T16	182444	182438	0	0
T17	15398	15324	0	0
T22	661009	660953	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1866834928	1866703956	0	0
T1	1264	1166	0	0
T2	102476	102475	0	0
T3	2384	2319	0	0
T4	662	573	0	0
T5	152086	151989	0	0
T9	995239	995222	0	0
T10	32446	32356	0	0
T16	182444	182438	0	0
T17	15398	15324	0	0
T22	661009	660953	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1866834928	10691368	0	0
T1	1264	2	0	0
T2	102476	7436	0	0
T3	2384	200	0	0
T4	662	0	0	0
T5	152086	2810	0	0
T9	995239	59726	0	0
T10	32446	160	0	0
T16	182444	21540	0	0
T17	15398	1024	0	0
T18	0	25856	0	0
T19	0	25692	0	0
T22	661009	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1866834928	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1866834928	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1866834928	10691368	0	0
T1	1264	2	0	0
T2	102476	7436	0	0
T3	2384	200	0	0
T4	662	0	0	0
T5	152086	2810	0	0
T9	995239	59726	0	0
T10	32446	160	0	0
T16	182444	21540	0	0
T17	15398	1024	0	0
T18	0	25856	0	0
T19	0	25692	0	0
T22	661009	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1866834928	10691368	0	0
T1	1264	2	0	0
T2	102476	7436	0	0
T3	2384	200	0	0
T4	662	0	0	0
T5	152086	2810	0	0
T9	995239	59726	0	0
T10	32446	160	0	0
T16	182444	21540	0	0
T17	15398	1024	0	0
T18	0	25856	0	0
T19	0	25692	0	0
T22	661009	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1866834928	10691368	0	0
T1	1264	2	0	0
T2	102476	7436	0	0
T3	2384	200	0	0
T4	662	0	0	0
T5	152086	2810	0	0
T9	995239	59726	0	0
T10	32446	160	0	0
T16	182444	21540	0	0
T17	15398	1024	0	0
T18	0	25856	0	0
T19	0	25692	0	0
T22	661009	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1866834928	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1866834928	0	0	1572

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1866834928	1866703956	0	0
T1	1264	1166	0	0
T2	102476	102475	0	0
T3	2384	2319	0	0
T4	662	573	0	0
T5	152086	151989	0	0
T9	995239	995222	0	0
T10	32446	32356	0	0
T16	182444	182438	0	0
T17	15398	15324	0	0
T22	661009	660953	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1866834928	10691368	0	0
T1	1264	2	0	0
T2	102476	7436	0	0
T3	2384	200	0	0
T4	662	0	0	0
T5	152086	2810	0	0
T9	995239	59726	0	0
T10	32446	160	0	0
T16	182444	21540	0	0
T17	15398	1024	0	0
T18	0	25856	0	0
T19	0	25692	0	0
T22	661009	0	0	0

Line Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T5,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T5
1	0	Covered	T2,T5,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T9
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1512729737	1478650086	0	0
CheckNGreaterZero_A	1572	1572	0	0
GntImpliesReady_A	1512729737	8398542	0	0
GntImpliesValid_A	1512729737	8398542	0	0
GrantKnown_A	1512729737	1478650086	0	0
IdxKnown_A	1512729737	1478650086	0	0
IndexIsCorrect_A	1512729737	8398542	0	0
LockArbDecision_A	1512729737	0	0	0
NoReadyValidNoGrant_A	1512729737	0	0	0
ReadyAndValidImplyGrant_A	1512729737	8398542	0	0
ReqAndReadyImplyGrant_A	1512729737	8398542	0	0
ReqImpliesValid_A	1512729737	8398542	0	0
ReqStaysHighUntilGranted0_M	1512729737	0	0	0
RoundRobin_A	1512729737	717	0	700
ValidKnown_A	1512729737	1478650086	0	0
gen_data_port_assertion.DataFlow_A	1512729737	8398542	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1512729737	1478650086	0	0
T1	1154	1154	0	0
T2	102475	102475	0	0
T5	151978	151978	0	0
T9	995112	995112	0	0
T10	32337	32337	0	0
T16	182436	182436	0	0
T17	31168	31168	0	0
T18	351377	351377	0	0
T19	273323	273323	0	0
T20	0	69091	0	0
T22	128596	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1572	1572	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1512729737	8398542	0	0
T1	1154	2	0	0
T2	102475	7436	0	0
T5	151978	2810	0	0
T9	995112	59726	0	0
T10	32337	160	0	0
T16	182436	21540	0	0
T17	31168	0	0	0
T18	351377	25856	0	0
T19	273323	25692	0	0
T20	0	416	0	0
T21	0	48526	0	0
T22	128596	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1512729737	8398542	0	0
T1	1154	2	0	0
T2	102475	7436	0	0
T5	151978	2810	0	0
T9	995112	59726	0	0
T10	32337	160	0	0
T16	182436	21540	0	0
T17	31168	0	0	0
T18	351377	25856	0	0
T19	273323	25692	0	0
T20	0	416	0	0
T21	0	48526	0	0
T22	128596	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1512729737	1478650086	0	0
T1	1154	1154	0	0
T2	102475	102475	0	0
T5	151978	151978	0	0
T9	995112	995112	0	0
T10	32337	32337	0	0
T16	182436	182436	0	0
T17	31168	31168	0	0
T18	351377	351377	0	0
T19	273323	273323	0	0
T20	0	69091	0	0
T22	128596	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1512729737	1478650086	0	0
T1	1154	1154	0	0
T2	102475	102475	0	0
T5	151978	151978	0	0
T9	995112	995112	0	0
T10	32337	32337	0	0
T16	182436	182436	0	0
T17	31168	31168	0	0
T18	351377	351377	0	0
T19	273323	273323	0	0
T20	0	69091	0	0
T22	128596	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1512729737	8398542	0	0
T1	1154	2	0	0
T2	102475	7436	0	0
T5	151978	2810	0	0
T9	995112	59726	0	0
T10	32337	160	0	0
T16	182436	21540	0	0
T17	31168	0	0	0
T18	351377	25856	0	0
T19	273323	25692	0	0
T20	0	416	0	0
T21	0	48526	0	0
T22	128596	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1512729737	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1512729737	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1512729737	8398542	0	0
T1	1154	2	0	0
T2	102475	7436	0	0
T5	151978	2810	0	0
T9	995112	59726	0	0
T10	32337	160	0	0
T16	182436	21540	0	0
T17	31168	0	0	0
T18	351377	25856	0	0
T19	273323	25692	0	0
T20	0	416	0	0
T21	0	48526	0	0
T22	128596	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1512729737	8398542	0	0
T1	1154	2	0	0
T2	102475	7436	0	0
T5	151978	2810	0	0
T9	995112	59726	0	0
T10	32337	160	0	0
T16	182436	21540	0	0
T17	31168	0	0	0
T18	351377	25856	0	0
T19	273323	25692	0	0
T20	0	416	0	0
T21	0	48526	0	0
T22	128596	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1512729737	8398542	0	0
T1	1154	2	0	0
T2	102475	7436	0	0
T5	151978	2810	0	0
T9	995112	59726	0	0
T10	32337	160	0	0
T16	182436	21540	0	0
T17	31168	0	0	0
T18	351377	25856	0	0
T19	273323	25692	0	0
T20	0	416	0	0
T21	0	48526	0	0
T22	128596	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1512729737	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1512729737	717	0	700
T9	995112	7	0	1
T10	32337	0	0	1
T13	0	0	0	0
T16	182436	0	0	1
T17	31168	0	0	0
T18	351377	0	0	1
T19	273323	0	0	1
T22	128596	0	0	0
T26	0	0	0	0
T49	395705	2	0	1
T53	0	4	0	0
T66	606866	38	0	1
T67	0	4	0	1
T68	0	2	0	0
T69	0	3	0	0
T70	0	5	0	0
T71	0	1	0	0
T72	0	30	0	0
T73	606451	0	0	1
T74	0	0	0	0
T75	0	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1512729737	1478650086	0	0
T1	1154	1154	0	0
T2	102475	102475	0	0
T5	151978	151978	0	0
T9	995112	995112	0	0
T10	32337	32337	0	0
T16	182436	182436	0	0
T17	31168	31168	0	0
T18	351377	351377	0	0
T19	273323	273323	0	0
T20	0	69091	0	0
T22	128596	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1512729737	8398542	0	0
T1	1154	2	0	0
T2	102475	7436	0	0
T5	151978	2810	0	0
T9	995112	59726	0	0
T10	32337	160	0	0
T16	182436	21540	0	0
T17	31168	0	0	0
T18	351377	25856	0	0
T19	273323	25692	0	0
T20	0	416	0	0
T21	0	48526	0	0
T22	128596	0	0	0