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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.10 99.01 96.33 98.63 92.06 98.05 95.86 99.76


Total test records in report: 1747
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T1506 /workspace/coverage/default/45.spi_device_alert_test.1880372475 Dec 27 01:37:38 PM PST 23 Dec 27 01:37:45 PM PST 23 25480472 ps
T1507 /workspace/coverage/default/21.spi_device_abort.2244878737 Dec 27 01:32:31 PM PST 23 Dec 27 01:32:37 PM PST 23 46802334 ps
T1508 /workspace/coverage/default/16.spi_device_cfg_cmd.2342032994 Dec 27 01:32:26 PM PST 23 Dec 27 01:32:36 PM PST 23 96462997 ps
T1509 /workspace/coverage/default/9.spi_device_mailbox.4180311498 Dec 27 01:31:26 PM PST 23 Dec 27 01:31:34 PM PST 23 785508215 ps
T1510 /workspace/coverage/default/2.spi_device_stress_all.2321543238 Dec 27 01:30:27 PM PST 23 Dec 27 01:58:21 PM PST 23 258343890399 ps
T1511 /workspace/coverage/default/29.spi_device_bit_transfer.4253088521 Dec 27 01:33:50 PM PST 23 Dec 27 01:33:55 PM PST 23 224147733 ps
T1512 /workspace/coverage/default/23.spi_device_dummy_item_extra_dly.3514109033 Dec 27 01:32:22 PM PST 23 Dec 27 01:51:59 PM PST 23 205476022735 ps
T1513 /workspace/coverage/default/26.spi_device_mailbox.2765975005 Dec 27 01:33:15 PM PST 23 Dec 27 01:33:36 PM PST 23 11564450973 ps
T1514 /workspace/coverage/default/14.spi_device_bit_transfer.2589109270 Dec 27 01:31:34 PM PST 23 Dec 27 01:31:37 PM PST 23 736764624 ps
T1515 /workspace/coverage/default/2.spi_device_extreme_fifo_size.2654282980 Dec 27 01:30:45 PM PST 23 Dec 27 02:30:08 PM PST 23 176198380287 ps
T1516 /workspace/coverage/default/0.spi_device_tpm_all.4078691873 Dec 27 01:30:23 PM PST 23 Dec 27 01:33:22 PM PST 23 32976132324 ps
T1517 /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1434864114 Dec 27 01:33:15 PM PST 23 Dec 27 01:33:18 PM PST 23 982781915 ps
T1518 /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4153588764 Dec 27 01:36:52 PM PST 23 Dec 27 01:36:59 PM PST 23 1058135016 ps
T1519 /workspace/coverage/default/46.spi_device_rx_async_fifo_reset.1687433766 Dec 27 01:38:25 PM PST 23 Dec 27 01:38:26 PM PST 23 21102426 ps
T1520 /workspace/coverage/default/41.spi_device_rx_timeout.2844203142 Dec 27 01:36:58 PM PST 23 Dec 27 01:37:04 PM PST 23 865220936 ps
T1521 /workspace/coverage/default/5.spi_device_fifo_full.146921394 Dec 27 01:30:17 PM PST 23 Dec 27 01:34:56 PM PST 23 45027086618 ps
T1522 /workspace/coverage/default/16.spi_device_txrx.3086357405 Dec 27 01:31:42 PM PST 23 Dec 27 01:33:35 PM PST 23 47898575168 ps
T1523 /workspace/coverage/default/48.spi_device_upload.3481596740 Dec 27 01:38:25 PM PST 23 Dec 27 01:38:28 PM PST 23 487864383 ps
T1524 /workspace/coverage/default/3.spi_device_perf.1954202240 Dec 27 01:29:57 PM PST 23 Dec 27 01:34:09 PM PST 23 11909894391 ps
T1525 /workspace/coverage/default/4.spi_device_intercept.3750588954 Dec 27 01:30:37 PM PST 23 Dec 27 01:30:43 PM PST 23 1121137566 ps
T1526 /workspace/coverage/default/35.spi_device_alert_test.3737588270 Dec 27 01:36:02 PM PST 23 Dec 27 01:36:04 PM PST 23 40269043 ps
T1527 /workspace/coverage/default/40.spi_device_cfg_cmd.725903056 Dec 27 01:36:53 PM PST 23 Dec 27 01:36:58 PM PST 23 1303549019 ps
T1528 /workspace/coverage/default/12.spi_device_tx_async_fifo_reset.1771059916 Dec 27 01:32:16 PM PST 23 Dec 27 01:32:24 PM PST 23 27767002 ps
T1529 /workspace/coverage/default/21.spi_device_cfg_cmd.3171166744 Dec 27 01:32:19 PM PST 23 Dec 27 01:32:33 PM PST 23 1335317932 ps
T1530 /workspace/coverage/default/47.spi_device_rx_timeout.1535801683 Dec 27 01:37:52 PM PST 23 Dec 27 01:38:02 PM PST 23 6262807525 ps
T1531 /workspace/coverage/default/25.spi_device_tx_async_fifo_reset.2625511669 Dec 27 01:32:50 PM PST 23 Dec 27 01:32:54 PM PST 23 116067728 ps
T1532 /workspace/coverage/default/16.spi_device_dummy_item_extra_dly.1614437929 Dec 27 01:32:17 PM PST 23 Dec 27 01:35:14 PM PST 23 28416064237 ps
T1533 /workspace/coverage/default/46.spi_device_flash_mode.3027189171 Dec 27 01:37:44 PM PST 23 Dec 27 01:38:07 PM PST 23 1026185805 ps
T1534 /workspace/coverage/default/9.spi_device_dummy_item_extra_dly.3037721425 Dec 27 01:31:16 PM PST 23 Dec 27 01:35:57 PM PST 23 74064459710 ps
T113 /workspace/coverage/default/2.spi_device_sec_cm.421587928 Dec 27 01:30:09 PM PST 23 Dec 27 01:30:14 PM PST 23 38206404 ps
T1535 /workspace/coverage/default/19.spi_device_alert_test.1307634654 Dec 27 01:32:17 PM PST 23 Dec 27 01:32:33 PM PST 23 21513254 ps
T1536 /workspace/coverage/default/21.spi_device_intercept.1610356785 Dec 27 01:32:19 PM PST 23 Dec 27 01:32:32 PM PST 23 1637659077 ps
T1537 /workspace/coverage/default/28.spi_device_intercept.3325735588 Dec 27 01:33:18 PM PST 23 Dec 27 01:33:25 PM PST 23 2995728302 ps
T1538 /workspace/coverage/default/1.spi_device_bit_transfer.1942069652 Dec 27 01:30:40 PM PST 23 Dec 27 01:30:44 PM PST 23 115227382 ps
T1539 /workspace/coverage/default/12.spi_device_abort.2727119647 Dec 27 01:32:19 PM PST 23 Dec 27 01:32:28 PM PST 23 23621312 ps
T1540 /workspace/coverage/default/0.spi_device_rx_timeout.3545340575 Dec 27 01:30:20 PM PST 23 Dec 27 01:30:28 PM PST 23 3703500729 ps
T1541 /workspace/coverage/default/15.spi_device_fifo_underflow_overflow.2376441253 Dec 27 01:32:31 PM PST 23 Dec 27 01:36:54 PM PST 23 51017227512 ps
T1542 /workspace/coverage/default/21.spi_device_flash_mode.3786647911 Dec 27 01:32:25 PM PST 23 Dec 27 01:33:03 PM PST 23 24109879274 ps
T1543 /workspace/coverage/default/9.spi_device_flash_and_tpm.2892391496 Dec 27 01:31:50 PM PST 23 Dec 27 01:33:40 PM PST 23 38591092742 ps
T1544 /workspace/coverage/default/27.spi_device_abort.1308894811 Dec 27 01:33:25 PM PST 23 Dec 27 01:33:28 PM PST 23 13669320 ps
T1545 /workspace/coverage/default/43.spi_device_intercept.789061476 Dec 27 01:37:30 PM PST 23 Dec 27 01:37:33 PM PST 23 140124708 ps
T1546 /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3724726038 Dec 27 01:37:15 PM PST 23 Dec 27 01:37:17 PM PST 23 1783681685 ps
T1547 /workspace/coverage/default/46.spi_device_flash_all.322696109 Dec 27 01:37:46 PM PST 23 Dec 27 01:39:42 PM PST 23 16719882841 ps
T1548 /workspace/coverage/default/7.spi_device_tpm_sts_read.411075789 Dec 27 01:31:05 PM PST 23 Dec 27 01:31:06 PM PST 23 83043688 ps
T1549 /workspace/coverage/default/27.spi_device_read_buffer_direct.2065159468 Dec 27 01:33:18 PM PST 23 Dec 27 01:33:25 PM PST 23 817170123 ps
T1550 /workspace/coverage/default/49.spi_device_rx_async_fifo_reset.159663730 Dec 27 01:37:55 PM PST 23 Dec 27 01:37:59 PM PST 23 64570872 ps
T1551 /workspace/coverage/default/7.spi_device_tpm_all.69886455 Dec 27 01:31:07 PM PST 23 Dec 27 01:31:18 PM PST 23 1966390547 ps
T1552 /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4000848306 Dec 27 01:31:56 PM PST 23 Dec 27 01:32:00 PM PST 23 590735540 ps
T1553 /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.508546250 Dec 27 01:37:55 PM PST 23 Dec 27 01:38:07 PM PST 23 3024664485 ps
T1554 /workspace/coverage/default/41.spi_device_upload.4073165481 Dec 27 01:36:55 PM PST 23 Dec 27 01:37:12 PM PST 23 14852841937 ps
T1555 /workspace/coverage/default/13.spi_device_smoke.1386456551 Dec 27 01:32:20 PM PST 23 Dec 27 01:32:31 PM PST 23 40469015 ps
T1556 /workspace/coverage/default/12.spi_device_bit_transfer.940895069 Dec 27 01:32:48 PM PST 23 Dec 27 01:32:56 PM PST 23 641296510 ps
T1557 /workspace/coverage/default/22.spi_device_extreme_fifo_size.3565340462 Dec 27 01:32:23 PM PST 23 Dec 27 01:56:35 PM PST 23 43136795045 ps
T1558 /workspace/coverage/default/27.spi_device_alert_test.1827224113 Dec 27 01:33:46 PM PST 23 Dec 27 01:33:47 PM PST 23 10738207 ps
T1559 /workspace/coverage/default/11.spi_device_bit_transfer.1111568989 Dec 27 01:31:44 PM PST 23 Dec 27 01:31:47 PM PST 23 1088920411 ps
T1560 /workspace/coverage/default/22.spi_device_flash_and_tpm.1406717140 Dec 27 01:32:24 PM PST 23 Dec 27 01:39:35 PM PST 23 116714566355 ps
T1561 /workspace/coverage/default/0.spi_device_mailbox.3014568375 Dec 27 01:30:21 PM PST 23 Dec 27 01:30:28 PM PST 23 1108339058 ps
T1562 /workspace/coverage/default/36.spi_device_bit_transfer.2998423296 Dec 27 01:35:58 PM PST 23 Dec 27 01:36:02 PM PST 23 454832276 ps
T1563 /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2023443934 Dec 27 01:37:58 PM PST 23 Dec 27 01:39:38 PM PST 23 7419217155 ps
T1564 /workspace/coverage/default/17.spi_device_tpm_sts_read.3220370235 Dec 27 01:32:18 PM PST 23 Dec 27 01:32:26 PM PST 23 37795194 ps
T1565 /workspace/coverage/default/0.spi_device_tpm_sts_read.2999685661 Dec 27 01:30:29 PM PST 23 Dec 27 01:30:31 PM PST 23 102322036 ps
T1566 /workspace/coverage/default/17.spi_device_read_buffer_direct.2022366534 Dec 27 01:32:21 PM PST 23 Dec 27 01:32:35 PM PST 23 77948492 ps
T1567 /workspace/coverage/default/26.spi_device_rx_timeout.2190682404 Dec 27 01:33:15 PM PST 23 Dec 27 01:33:20 PM PST 23 414602969 ps
T1568 /workspace/coverage/default/16.spi_device_read_buffer_direct.476916247 Dec 27 01:32:51 PM PST 23 Dec 27 01:32:58 PM PST 23 827135385 ps
T1569 /workspace/coverage/default/15.spi_device_mailbox.1119803024 Dec 27 01:32:23 PM PST 23 Dec 27 01:32:49 PM PST 23 3282983171 ps
T1570 /workspace/coverage/default/44.spi_device_byte_transfer.153620787 Dec 27 01:37:27 PM PST 23 Dec 27 01:37:31 PM PST 23 139233967 ps
T1571 /workspace/coverage/default/35.spi_device_bit_transfer.4115110554 Dec 27 01:36:11 PM PST 23 Dec 27 01:36:15 PM PST 23 591797808 ps
T1572 /workspace/coverage/default/48.spi_device_extreme_fifo_size.2234567566 Dec 27 01:37:53 PM PST 23 Dec 27 01:38:23 PM PST 23 1858012847 ps
T1573 /workspace/coverage/default/39.spi_device_rx_timeout.4195977991 Dec 27 01:36:04 PM PST 23 Dec 27 01:36:11 PM PST 23 2196858648 ps
T1574 /workspace/coverage/default/20.spi_device_bit_transfer.3784824187 Dec 27 01:32:18 PM PST 23 Dec 27 01:32:29 PM PST 23 422141172 ps
T1575 /workspace/coverage/default/9.spi_device_fifo_underflow_overflow.2364563110 Dec 27 01:30:55 PM PST 23 Dec 27 01:34:59 PM PST 23 158969814790 ps
T1576 /workspace/coverage/default/18.spi_device_byte_transfer.180066548 Dec 27 01:32:19 PM PST 23 Dec 27 01:32:29 PM PST 23 472480741 ps
T1577 /workspace/coverage/default/11.spi_device_intr.1404000709 Dec 27 01:32:14 PM PST 23 Dec 27 01:33:11 PM PST 23 7928728120 ps
T1578 /workspace/coverage/default/42.spi_device_rx_timeout.1159954914 Dec 27 01:37:30 PM PST 23 Dec 27 01:37:35 PM PST 23 643428574 ps
T1579 /workspace/coverage/default/4.spi_device_fifo_underflow_overflow.458744691 Dec 27 01:30:22 PM PST 23 Dec 27 01:33:37 PM PST 23 18562301927 ps
T1580 /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3234566858 Dec 27 01:30:19 PM PST 23 Dec 27 01:30:27 PM PST 23 2119303851 ps
T1581 /workspace/coverage/default/37.spi_device_tx_async_fifo_reset.1802338302 Dec 27 01:35:48 PM PST 23 Dec 27 01:35:49 PM PST 23 78173769 ps
T1582 /workspace/coverage/default/0.spi_device_cfg_cmd.2656393738 Dec 27 01:30:23 PM PST 23 Dec 27 01:30:28 PM PST 23 291033730 ps
T1583 /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1430655571 Dec 27 01:32:16 PM PST 23 Dec 27 01:32:49 PM PST 23 30643639606 ps
T1584 /workspace/coverage/default/35.spi_device_abort.3495402378 Dec 27 01:36:03 PM PST 23 Dec 27 01:36:05 PM PST 23 14707420 ps
T1585 /workspace/coverage/default/26.spi_device_rx_async_fifo_reset.3534647175 Dec 27 01:33:24 PM PST 23 Dec 27 01:33:25 PM PST 23 18295062 ps
T1586 /workspace/coverage/default/49.spi_device_mailbox.1183736919 Dec 27 01:37:57 PM PST 23 Dec 27 01:39:01 PM PST 23 222601039518 ps
T1587 /workspace/coverage/default/2.spi_device_flash_and_tpm.946219106 Dec 27 01:30:34 PM PST 23 Dec 27 01:32:15 PM PST 23 26704648728 ps
T1588 /workspace/coverage/default/17.spi_device_fifo_underflow_overflow.3887573458 Dec 27 01:31:25 PM PST 23 Dec 27 01:45:17 PM PST 23 202805695343 ps
T1589 /workspace/coverage/default/33.spi_device_rx_timeout.2383322888 Dec 27 01:34:31 PM PST 23 Dec 27 01:34:37 PM PST 23 883422945 ps
T1590 /workspace/coverage/default/4.spi_device_ram_cfg.862933566 Dec 27 01:30:21 PM PST 23 Dec 27 01:30:23 PM PST 23 28772865 ps
T1591 /workspace/coverage/default/42.spi_device_stress_all.512990999 Dec 27 01:36:55 PM PST 23 Dec 27 01:55:15 PM PST 23 169733644425 ps
T1592 /workspace/coverage/default/23.spi_device_upload.2493746230 Dec 27 01:32:52 PM PST 23 Dec 27 01:33:06 PM PST 23 2661592666 ps
T1593 /workspace/coverage/default/35.spi_device_perf.186592628 Dec 27 01:35:34 PM PST 23 Dec 27 01:42:03 PM PST 23 70844758481 ps
T1594 /workspace/coverage/default/3.spi_device_intr.2416326644 Dec 27 01:30:29 PM PST 23 Dec 27 01:30:47 PM PST 23 3447955962 ps
T1595 /workspace/coverage/default/34.spi_device_tpm_rw.1197820849 Dec 27 01:34:57 PM PST 23 Dec 27 01:34:59 PM PST 23 29700083 ps
T1596 /workspace/coverage/default/38.spi_device_intercept.1118427246 Dec 27 01:36:16 PM PST 23 Dec 27 01:36:23 PM PST 23 1423412974 ps
T1597 /workspace/coverage/default/6.spi_device_tpm_sts_read.1611641636 Dec 27 01:30:57 PM PST 23 Dec 27 01:30:58 PM PST 23 50123674 ps
T1598 /workspace/coverage/default/5.spi_device_abort.4119961117 Dec 27 01:30:37 PM PST 23 Dec 27 01:30:39 PM PST 23 46434612 ps
T1599 /workspace/coverage/default/8.spi_device_alert_test.338263356 Dec 27 01:31:24 PM PST 23 Dec 27 01:31:25 PM PST 23 20570234 ps
T1600 /workspace/coverage/default/40.spi_device_tpm_sts_read.447852219 Dec 27 01:36:32 PM PST 23 Dec 27 01:36:34 PM PST 23 110515973 ps
T1601 /workspace/coverage/default/37.spi_device_extreme_fifo_size.4246026426 Dec 27 01:35:28 PM PST 23 Dec 27 01:41:27 PM PST 23 33530048035 ps
T1602 /workspace/coverage/default/11.spi_device_upload.62716710 Dec 27 01:32:18 PM PST 23 Dec 27 01:32:32 PM PST 23 941251492 ps
T1603 /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2271117962 Dec 27 01:37:25 PM PST 23 Dec 27 01:37:36 PM PST 23 15966483333 ps
T1604 /workspace/coverage/default/20.spi_device_tpm_all.300445680 Dec 27 01:32:39 PM PST 23 Dec 27 01:33:19 PM PST 23 2148083792 ps
T1605 /workspace/coverage/default/11.spi_device_flash_mode.3980996282 Dec 27 01:31:12 PM PST 23 Dec 27 01:31:20 PM PST 23 213792709 ps
T1606 /workspace/coverage/default/42.spi_device_abort.2993594839 Dec 27 01:37:14 PM PST 23 Dec 27 01:37:16 PM PST 23 208871726 ps
T1607 /workspace/coverage/default/12.spi_device_byte_transfer.1570261280 Dec 27 01:32:17 PM PST 23 Dec 27 01:32:26 PM PST 23 143002883 ps
T1608 /workspace/coverage/default/47.spi_device_rx_async_fifo_reset.3759997448 Dec 27 01:37:53 PM PST 23 Dec 27 01:37:58 PM PST 23 84310139 ps
T1609 /workspace/coverage/default/12.spi_device_smoke.1888019680 Dec 27 01:31:41 PM PST 23 Dec 27 01:31:43 PM PST 23 618914216 ps
T1610 /workspace/coverage/default/1.spi_device_flash_mode.1978838404 Dec 27 01:30:18 PM PST 23 Dec 27 01:31:04 PM PST 23 30673142062 ps
T1611 /workspace/coverage/default/11.spi_device_rx_async_fifo_reset.2690352496 Dec 27 01:31:30 PM PST 23 Dec 27 01:31:32 PM PST 23 21302744 ps
T1612 /workspace/coverage/default/49.spi_device_tpm_all.874184625 Dec 27 01:38:49 PM PST 23 Dec 27 01:39:00 PM PST 23 2453633554 ps
T1613 /workspace/coverage/default/18.spi_device_tpm_rw.3180440725 Dec 27 01:32:23 PM PST 23 Dec 27 01:32:34 PM PST 23 589846003 ps
T1614 /workspace/coverage/default/48.spi_device_bit_transfer.2131011691 Dec 27 01:37:54 PM PST 23 Dec 27 01:38:01 PM PST 23 1170950286 ps
T1615 /workspace/coverage/default/0.spi_device_stress_all.4032011414 Dec 27 01:30:03 PM PST 23 Dec 27 01:52:21 PM PST 23 119471673002 ps
T1616 /workspace/coverage/default/44.spi_device_alert_test.1584334889 Dec 27 01:37:42 PM PST 23 Dec 27 01:37:48 PM PST 23 27838290 ps
T1617 /workspace/coverage/default/2.spi_device_txrx.1438111094 Dec 27 01:30:16 PM PST 23 Dec 27 01:40:30 PM PST 23 758267422456 ps
T1618 /workspace/coverage/default/33.spi_device_smoke.2982085281 Dec 27 01:35:00 PM PST 23 Dec 27 01:35:02 PM PST 23 32421803 ps
T1619 /workspace/coverage/default/17.spi_device_alert_test.2801977128 Dec 27 01:32:23 PM PST 23 Dec 27 01:32:33 PM PST 23 19814555 ps
T1620 /workspace/coverage/default/23.spi_device_smoke.1682386583 Dec 27 01:32:27 PM PST 23 Dec 27 01:32:35 PM PST 23 164096108 ps
T337 /workspace/coverage/default/20.spi_device_flash_and_tpm.4020487117 Dec 27 01:32:42 PM PST 23 Dec 27 01:39:10 PM PST 23 172885131325 ps
T1621 /workspace/coverage/default/22.spi_device_bit_transfer.688004648 Dec 27 01:32:20 PM PST 23 Dec 27 01:32:32 PM PST 23 172382556 ps
T1622 /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.444999952 Dec 27 01:32:29 PM PST 23 Dec 27 01:34:27 PM PST 23 55372945698 ps
T1623 /workspace/coverage/default/38.spi_device_rx_timeout.3836729497 Dec 27 01:35:29 PM PST 23 Dec 27 01:35:36 PM PST 23 2447378244 ps
T1624 /workspace/coverage/default/18.spi_device_csb_read.1456388612 Dec 27 01:32:18 PM PST 23 Dec 27 01:32:24 PM PST 23 32145437 ps
T1625 /workspace/coverage/default/22.spi_device_rx_timeout.2230001412 Dec 27 01:32:38 PM PST 23 Dec 27 01:32:44 PM PST 23 1158180873 ps
T1626 /workspace/coverage/default/24.spi_device_dummy_item_extra_dly.1987899796 Dec 27 01:33:18 PM PST 23 Dec 27 01:36:40 PM PST 23 52843097232 ps
T1627 /workspace/coverage/default/6.spi_device_intercept.2151064014 Dec 27 01:30:53 PM PST 23 Dec 27 01:30:56 PM PST 23 130220485 ps
T1628 /workspace/coverage/default/23.spi_device_extreme_fifo_size.451230502 Dec 27 01:32:21 PM PST 23 Dec 27 02:00:14 PM PST 23 202023323796 ps
T1629 /workspace/coverage/default/4.spi_device_rx_timeout.674259567 Dec 27 01:30:30 PM PST 23 Dec 27 01:30:38 PM PST 23 3144006627 ps
T328 /workspace/coverage/default/6.spi_device_flash_all.90470218 Dec 27 01:30:37 PM PST 23 Dec 27 01:31:04 PM PST 23 2533770684 ps
T1630 /workspace/coverage/default/0.spi_device_dummy_item_extra_dly.1714644880 Dec 27 01:29:57 PM PST 23 Dec 27 01:46:03 PM PST 23 43624216231 ps
T1631 /workspace/coverage/default/1.spi_device_mailbox.3693530979 Dec 27 01:30:17 PM PST 23 Dec 27 01:30:43 PM PST 23 26537875173 ps
T1632 /workspace/coverage/default/35.spi_device_tpm_sts_read.3050044565 Dec 27 01:36:03 PM PST 23 Dec 27 01:36:04 PM PST 23 15821030 ps
T1633 /workspace/coverage/default/34.spi_device_read_buffer_direct.876244498 Dec 27 01:34:36 PM PST 23 Dec 27 01:34:43 PM PST 23 2935698883 ps
T1634 /workspace/coverage/default/16.spi_device_upload.1543761917 Dec 27 01:32:08 PM PST 23 Dec 27 01:32:12 PM PST 23 169957476 ps
T1635 /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3096630994 Dec 27 01:33:52 PM PST 23 Dec 27 01:33:57 PM PST 23 902504155 ps
T1636 /workspace/coverage/default/13.spi_device_txrx.535365952 Dec 27 01:32:34 PM PST 23 Dec 27 01:33:55 PM PST 23 20158425858 ps
T1637 /workspace/coverage/default/31.spi_device_fifo_full.2968391568 Dec 27 01:33:56 PM PST 23 Dec 27 01:50:01 PM PST 23 33442666400 ps
T1638 /workspace/coverage/default/20.spi_device_intercept.2950513945 Dec 27 01:32:28 PM PST 23 Dec 27 01:32:38 PM PST 23 224309596 ps
T1639 /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3932470919 Dec 27 01:33:16 PM PST 23 Dec 27 01:34:01 PM PST 23 15713097004 ps
T1640 /workspace/coverage/default/47.spi_device_tx_async_fifo_reset.2523986749 Dec 27 01:37:35 PM PST 23 Dec 27 01:37:37 PM PST 23 40677205 ps
T1641 /workspace/coverage/default/30.spi_device_rx_async_fifo_reset.1852969550 Dec 27 01:33:39 PM PST 23 Dec 27 01:33:41 PM PST 23 160312994 ps
T1642 /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1582854937 Dec 27 01:32:13 PM PST 23 Dec 27 01:33:19 PM PST 23 7882699718 ps
T1643 /workspace/coverage/default/15.spi_device_csb_read.2491386913 Dec 27 01:31:20 PM PST 23 Dec 27 01:31:21 PM PST 23 15027474 ps
T1644 /workspace/coverage/default/7.spi_device_tpm_rw.3183048640 Dec 27 01:31:11 PM PST 23 Dec 27 01:31:16 PM PST 23 655239040 ps
T1645 /workspace/coverage/default/38.spi_device_bit_transfer.1188096753 Dec 27 01:36:01 PM PST 23 Dec 27 01:36:04 PM PST 23 114503884 ps
T1646 /workspace/coverage/default/10.spi_device_txrx.3055996768 Dec 27 01:31:15 PM PST 23 Dec 27 01:34:42 PM PST 23 42859283126 ps
T1647 /workspace/coverage/default/12.spi_device_read_buffer_direct.4180425503 Dec 27 01:32:14 PM PST 23 Dec 27 01:32:29 PM PST 23 2051577360 ps
T1648 /workspace/coverage/default/32.spi_device_csb_read.3435067127 Dec 27 01:34:33 PM PST 23 Dec 27 01:34:35 PM PST 23 21925518 ps
T1649 /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.228094906 Dec 27 01:33:21 PM PST 23 Dec 27 01:33:27 PM PST 23 828711799 ps
T1650 /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1380169718 Dec 27 01:38:29 PM PST 23 Dec 27 01:38:36 PM PST 23 665444442 ps
T1651 /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1163234934 Dec 27 01:36:13 PM PST 23 Dec 27 01:36:25 PM PST 23 6757255958 ps
T1652 /workspace/coverage/default/35.spi_device_tx_async_fifo_reset.2364193350 Dec 27 01:35:55 PM PST 23 Dec 27 01:35:57 PM PST 23 45260591 ps
T1653 /workspace/coverage/default/43.spi_device_tx_async_fifo_reset.2134012405 Dec 27 01:37:08 PM PST 23 Dec 27 01:37:10 PM PST 23 17887599 ps
T1654 /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.940892437 Dec 27 01:32:58 PM PST 23 Dec 27 01:33:02 PM PST 23 158639328 ps
T1655 /workspace/coverage/default/30.spi_device_tx_async_fifo_reset.963544188 Dec 27 01:33:49 PM PST 23 Dec 27 01:33:51 PM PST 23 17754611 ps
T1656 /workspace/coverage/default/49.spi_device_flash_and_tpm.3232480703 Dec 27 01:38:21 PM PST 23 Dec 27 01:38:53 PM PST 23 49503537029 ps
T1657 /workspace/coverage/default/13.spi_device_mem_parity.2116084506 Dec 27 01:32:26 PM PST 23 Dec 27 01:32:34 PM PST 23 15012012 ps
T1658 /workspace/coverage/default/15.spi_device_tpm_rw.2339489117 Dec 27 01:31:38 PM PST 23 Dec 27 01:31:41 PM PST 23 73920037 ps
T1659 /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3225854894 Dec 27 01:33:34 PM PST 23 Dec 27 01:33:44 PM PST 23 1995505651 ps
T1660 /workspace/coverage/default/17.spi_device_rx_async_fifo_reset.542223959 Dec 27 01:32:15 PM PST 23 Dec 27 01:32:24 PM PST 23 81679860 ps
T1661 /workspace/coverage/default/1.spi_device_upload.3568877311 Dec 27 01:30:12 PM PST 23 Dec 27 01:30:30 PM PST 23 14953307086 ps
T1662 /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2946624167 Dec 27 01:32:18 PM PST 23 Dec 27 01:32:30 PM PST 23 2286325019 ps
T1663 /workspace/coverage/default/2.spi_device_mem_parity.1717669550 Dec 27 01:30:31 PM PST 23 Dec 27 01:30:33 PM PST 23 18437959 ps
T1664 /workspace/coverage/default/9.spi_device_rx_async_fifo_reset.401653779 Dec 27 01:31:20 PM PST 23 Dec 27 01:31:22 PM PST 23 53255467 ps
T1665 /workspace/coverage/default/28.spi_device_rx_async_fifo_reset.1849675308 Dec 27 01:33:20 PM PST 23 Dec 27 01:33:22 PM PST 23 104580369 ps
T1666 /workspace/coverage/default/48.spi_device_txrx.2744536411 Dec 27 01:37:54 PM PST 23 Dec 27 01:41:48 PM PST 23 23588568777 ps
T1667 /workspace/coverage/default/5.spi_device_tpm_sts_read.1699406346 Dec 27 01:30:37 PM PST 23 Dec 27 01:30:39 PM PST 23 81424863 ps
T1668 /workspace/coverage/default/0.spi_device_ram_cfg.3072678896 Dec 27 01:29:57 PM PST 23 Dec 27 01:30:00 PM PST 23 16038241 ps
T1669 /workspace/coverage/default/37.spi_device_txrx.2717609409 Dec 27 01:35:02 PM PST 23 Dec 27 01:47:54 PM PST 23 76533201625 ps
T1670 /workspace/coverage/default/26.spi_device_smoke.2193556205 Dec 27 01:32:54 PM PST 23 Dec 27 01:32:58 PM PST 23 13301386 ps
T1671 /workspace/coverage/default/28.spi_device_mailbox.1512255931 Dec 27 01:34:09 PM PST 23 Dec 27 01:34:21 PM PST 23 3522082821 ps
T1672 /workspace/coverage/default/48.spi_device_abort.2399706921 Dec 27 01:37:50 PM PST 23 Dec 27 01:37:54 PM PST 23 23123437 ps
T1673 /workspace/coverage/default/15.spi_device_flash_mode.2589716378 Dec 27 01:32:09 PM PST 23 Dec 27 01:32:22 PM PST 23 434550496 ps
T1674 /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1272085575 Dec 27 01:33:49 PM PST 23 Dec 27 01:33:54 PM PST 23 530640084 ps
T1675 /workspace/coverage/default/20.spi_device_fifo_full.1412914229 Dec 27 01:32:10 PM PST 23 Dec 27 02:17:59 PM PST 23 188898855521 ps
T1676 /workspace/coverage/default/42.spi_device_fifo_underflow_overflow.2156208363 Dec 27 01:37:19 PM PST 23 Dec 27 01:42:20 PM PST 23 13890160270 ps
T1677 /workspace/coverage/default/7.spi_device_flash_and_tpm.2315725440 Dec 27 01:31:08 PM PST 23 Dec 27 01:32:15 PM PST 23 33860613083 ps
T1678 /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2067357617 Dec 27 01:30:21 PM PST 23 Dec 27 01:33:53 PM PST 23 44325134345 ps
T1679 /workspace/coverage/default/37.spi_device_mailbox.4208780436 Dec 27 01:36:01 PM PST 23 Dec 27 01:36:25 PM PST 23 20064326888 ps
T1680 /workspace/coverage/default/8.spi_device_bit_transfer.2299142759 Dec 27 01:32:39 PM PST 23 Dec 27 01:32:48 PM PST 23 1055741252 ps
T1681 /workspace/coverage/default/32.spi_device_bit_transfer.941363979 Dec 27 01:33:53 PM PST 23 Dec 27 01:33:56 PM PST 23 410929800 ps
T1682 /workspace/coverage/default/46.spi_device_tpm_sts_read.793046581 Dec 27 01:38:30 PM PST 23 Dec 27 01:38:33 PM PST 23 47145507 ps
T1683 /workspace/coverage/default/34.spi_device_rx_timeout.3786591278 Dec 27 01:34:32 PM PST 23 Dec 27 01:34:39 PM PST 23 7214071652 ps
T1684 /workspace/coverage/default/7.spi_device_smoke.1710811438 Dec 27 01:30:40 PM PST 23 Dec 27 01:30:42 PM PST 23 14751094 ps
T1685 /workspace/coverage/default/34.spi_device_smoke.2597370543 Dec 27 01:34:10 PM PST 23 Dec 27 01:34:11 PM PST 23 31987670 ps
T1686 /workspace/coverage/default/46.spi_device_abort.3413695792 Dec 27 01:37:56 PM PST 23 Dec 27 01:37:59 PM PST 23 13291656 ps
T1687 /workspace/coverage/default/10.spi_device_alert_test.2780607391 Dec 27 01:32:19 PM PST 23 Dec 27 01:32:28 PM PST 23 54810100 ps
T1688 /workspace/coverage/default/24.spi_device_mailbox.2059156406 Dec 27 01:33:59 PM PST 23 Dec 27 01:34:24 PM PST 23 21366410657 ps
T1689 /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3001692769 Dec 27 01:32:27 PM PST 23 Dec 27 01:32:42 PM PST 23 2425282885 ps
T1690 /workspace/coverage/default/29.spi_device_intr.922104846 Dec 27 01:33:55 PM PST 23 Dec 27 01:34:22 PM PST 23 18728475086 ps
T1691 /workspace/coverage/default/16.spi_device_csb_read.2602221779 Dec 27 01:32:11 PM PST 23 Dec 27 01:32:13 PM PST 23 27505022 ps
T1692 /workspace/coverage/default/30.spi_device_tpm_rw.2863088241 Dec 27 01:33:54 PM PST 23 Dec 27 01:33:58 PM PST 23 213715587 ps
T1693 /workspace/coverage/default/9.spi_device_smoke.3909743798 Dec 27 01:31:29 PM PST 23 Dec 27 01:31:30 PM PST 23 16811808 ps
T1694 /workspace/coverage/default/7.spi_device_intr.1841137093 Dec 27 01:31:14 PM PST 23 Dec 27 01:33:08 PM PST 23 29548082774 ps
T1695 /workspace/coverage/default/43.spi_device_rx_timeout.710833919 Dec 27 01:36:52 PM PST 23 Dec 27 01:36:58 PM PST 23 687651927 ps
T1696 /workspace/coverage/default/32.spi_device_tpm_all.895924601 Dec 27 01:33:50 PM PST 23 Dec 27 01:34:33 PM PST 23 10409627915 ps
T1697 /workspace/coverage/default/22.spi_device_tpm_rw.1687605703 Dec 27 01:32:31 PM PST 23 Dec 27 01:32:37 PM PST 23 52883521 ps
T1698 /workspace/coverage/default/11.spi_device_fifo_underflow_overflow.1702324343 Dec 27 01:32:37 PM PST 23 Dec 27 01:39:41 PM PST 23 50758839802 ps
T1699 /workspace/coverage/default/5.spi_device_tpm_rw.4201516697 Dec 27 01:30:39 PM PST 23 Dec 27 01:30:43 PM PST 23 79426071 ps
T1700 /workspace/coverage/default/29.spi_device_fifo_full.686274724 Dec 27 01:33:50 PM PST 23 Dec 27 01:43:51 PM PST 23 29675464055 ps
T1701 /workspace/coverage/default/20.spi_device_dummy_item_extra_dly.726303101 Dec 27 01:32:28 PM PST 23 Dec 27 01:36:26 PM PST 23 97027882698 ps
T1702 /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.326596044 Dec 27 01:31:56 PM PST 23 Dec 27 01:32:10 PM PST 23 9759185820 ps
T1703 /workspace/coverage/default/40.spi_device_stress_all.2377498287 Dec 27 01:37:34 PM PST 23 Dec 27 02:23:27 PM PST 23 649021752687 ps
T1704 /workspace/coverage/default/45.spi_device_intr.1728566258 Dec 27 01:38:04 PM PST 23 Dec 27 01:39:19 PM PST 23 25469235098 ps
T1705 /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2439928544 Dec 27 01:38:26 PM PST 23 Dec 27 01:39:13 PM PST 23 174161857106 ps
T1706 /workspace/coverage/default/9.spi_device_mem_parity.2163968417 Dec 27 01:31:08 PM PST 23 Dec 27 01:31:10 PM PST 23 114951127 ps
T1707 /workspace/coverage/default/15.spi_device_flash_all.4176162450 Dec 27 01:32:02 PM PST 23 Dec 27 01:32:41 PM PST 23 29100592925 ps
T1708 /workspace/coverage/default/27.spi_device_csb_read.1449216135 Dec 27 01:33:31 PM PST 23 Dec 27 01:33:33 PM PST 23 62196916 ps
T1709 /workspace/coverage/default/25.spi_device_extreme_fifo_size.330741108 Dec 27 01:33:38 PM PST 23 Dec 27 01:41:37 PM PST 23 171825936904 ps
T1710 /workspace/coverage/default/29.spi_device_flash_all.395163529 Dec 27 01:33:52 PM PST 23 Dec 27 01:34:49 PM PST 23 11548453673 ps
T1711 /workspace/coverage/default/40.spi_device_read_buffer_direct.4072602607 Dec 27 01:37:28 PM PST 23 Dec 27 01:37:33 PM PST 23 389894664 ps
T1712 /workspace/coverage/default/40.spi_device_rx_async_fifo_reset.3782068761 Dec 27 01:36:21 PM PST 23 Dec 27 01:36:23 PM PST 23 425220895 ps
T1713 /workspace/coverage/default/40.spi_device_intr.2554585112 Dec 27 01:36:33 PM PST 23 Dec 27 01:37:01 PM PST 23 10966794613 ps
T1714 /workspace/coverage/default/27.spi_device_tpm_rw.2872612006 Dec 27 01:33:46 PM PST 23 Dec 27 01:33:49 PM PST 23 149957972 ps
T1715 /workspace/coverage/default/39.spi_device_bit_transfer.1229234583 Dec 27 01:36:00 PM PST 23 Dec 27 01:36:03 PM PST 23 1692807768 ps
T1716 /workspace/coverage/default/46.spi_device_perf.1022418353 Dec 27 01:37:56 PM PST 23 Dec 27 02:21:27 PM PST 23 86741634469 ps
T1717 /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2777553866 Dec 27 01:32:24 PM PST 23 Dec 27 01:32:51 PM PST 23 10512603539 ps
T1718 /workspace/coverage/default/34.spi_device_rx_async_fifo_reset.3347294212 Dec 27 01:34:28 PM PST 23 Dec 27 01:34:30 PM PST 23 59445475 ps
T1719 /workspace/coverage/default/37.spi_device_tpm_sts_read.2300991975 Dec 27 01:36:07 PM PST 23 Dec 27 01:36:09 PM PST 23 440049051 ps
T1720 /workspace/coverage/default/48.spi_device_flash_mode.730425791 Dec 27 01:37:50 PM PST 23 Dec 27 01:38:14 PM PST 23 22859694555 ps
T1721 /workspace/coverage/default/45.spi_device_extreme_fifo_size.2302514169 Dec 27 01:37:41 PM PST 23 Dec 27 01:48:00 PM PST 23 55513257502 ps
T1722 /workspace/coverage/default/0.spi_device_byte_transfer.3469024767 Dec 27 01:29:27 PM PST 23 Dec 27 01:29:31 PM PST 23 636828739 ps
T326 /workspace/coverage/default/16.spi_device_flash_and_tpm.3299938268 Dec 27 01:32:13 PM PST 23 Dec 27 01:39:10 PM PST 23 103185531636 ps
T1723 /workspace/coverage/default/31.spi_device_intr.3523088910 Dec 27 01:34:17 PM PST 23 Dec 27 01:34:57 PM PST 23 9934308125 ps
T1724 /workspace/coverage/default/14.spi_device_intr.1895256807 Dec 27 01:32:31 PM PST 23 Dec 27 01:33:09 PM PST 23 6145164329 ps
T1725 /workspace/coverage/default/15.spi_device_tpm_all.2117819555 Dec 27 01:31:30 PM PST 23 Dec 27 01:32:02 PM PST 23 49354959224 ps
T1726 /workspace/coverage/default/14.spi_device_extreme_fifo_size.4010193161 Dec 27 01:31:29 PM PST 23 Dec 27 01:32:39 PM PST 23 3136634255 ps
T1727 /workspace/coverage/default/9.spi_device_flash_mode.672102577 Dec 27 01:31:29 PM PST 23 Dec 27 01:31:39 PM PST 23 595926860 ps
T1728 /workspace/coverage/default/33.spi_device_tpm_rw.2321812483 Dec 27 01:34:36 PM PST 23 Dec 27 01:34:38 PM PST 23 33933319 ps
T203 /workspace/coverage/default/25.spi_device_flash_and_tpm.1646181632 Dec 27 01:32:56 PM PST 23 Dec 27 01:41:27 PM PST 23 384009265108 ps
T1729 /workspace/coverage/default/6.spi_device_read_buffer_direct.2547924681 Dec 27 01:31:00 PM PST 23 Dec 27 01:31:05 PM PST 23 571769874 ps
T1730 /workspace/coverage/default/31.spi_device_byte_transfer.2465916637 Dec 27 01:33:41 PM PST 23 Dec 27 01:33:44 PM PST 23 246272780 ps
T1731 /workspace/coverage/default/38.spi_device_byte_transfer.2108882622 Dec 27 01:35:51 PM PST 23 Dec 27 01:35:56 PM PST 23 393872866 ps
T1732 /workspace/coverage/default/1.spi_device_txrx.628107642 Dec 27 01:30:14 PM PST 23 Dec 27 01:33:07 PM PST 23 49364336268 ps
T1733 /workspace/coverage/default/33.spi_device_alert_test.1204883782 Dec 27 01:35:40 PM PST 23 Dec 27 01:35:42 PM PST 23 46189583 ps
T1734 /workspace/coverage/default/41.spi_device_dummy_item_extra_dly.3702104249 Dec 27 01:37:22 PM PST 23 Dec 27 01:41:01 PM PST 23 53735791732 ps
T1735 /workspace/coverage/default/44.spi_device_csb_read.4094583110 Dec 27 01:37:10 PM PST 23 Dec 27 01:37:12 PM PST 23 13740966 ps
T1736 /workspace/coverage/default/21.spi_device_bit_transfer.3024709176 Dec 27 01:32:19 PM PST 23 Dec 27 01:32:31 PM PST 23 150159873 ps
T1737 /workspace/coverage/default/40.spi_device_tx_async_fifo_reset.735192894 Dec 27 01:36:12 PM PST 23 Dec 27 01:36:13 PM PST 23 25463912 ps
T1738 /workspace/coverage/default/36.spi_device_fifo_underflow_overflow.3474405495 Dec 27 01:35:58 PM PST 23 Dec 27 01:38:41 PM PST 23 123142108011 ps
T1739 /workspace/coverage/default/2.spi_device_fifo_underflow_overflow.461469140 Dec 27 01:30:11 PM PST 23 Dec 27 01:36:51 PM PST 23 75593472630 ps
T1740 /workspace/coverage/default/36.spi_device_tpm_rw.2484005498 Dec 27 01:36:09 PM PST 23 Dec 27 01:36:12 PM PST 23 80367025 ps
T1741 /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2123630503 Dec 27 01:30:50 PM PST 23 Dec 27 01:30:55 PM PST 23 252565626 ps
T1742 /workspace/coverage/default/33.spi_device_byte_transfer.1370246551 Dec 27 01:34:21 PM PST 23 Dec 27 01:34:24 PM PST 23 131524479 ps
T1743 /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3283360886 Dec 27 01:32:03 PM PST 23 Dec 27 01:32:17 PM PST 23 2444859767 ps
T1744 /workspace/coverage/default/4.spi_device_alert_test.4235306222 Dec 27 01:30:22 PM PST 23 Dec 27 01:30:24 PM PST 23 11359717 ps
T1745 /workspace/coverage/default/21.spi_device_tpm_rw.3556436586 Dec 27 01:32:08 PM PST 23 Dec 27 01:32:12 PM PST 23 269228715 ps
T1746 /workspace/coverage/default/17.spi_device_mailbox.2027657287 Dec 27 01:32:11 PM PST 23 Dec 27 01:32:22 PM PST 23 3439520665 ps
T1747 /workspace/coverage/default/12.spi_device_flash_all.4171129776 Dec 27 01:32:24 PM PST 23 Dec 27 01:33:03 PM PST 23 20126207026 ps

Test location /workspace/coverage/default/37.spi_device_upload.1474535311
Short name T17
Test name
Test status
Simulation time 770016088 ps
CPU time 3.49 seconds
Started Dec 27 01:35:52 PM PST 23
Finished Dec 27 01:35:56 PM PST 23
Peak memory 218276 kb
Host smart-9cc49aa4-9845-47cc-aba3-87610347be3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474535311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1474535311
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1879990714
Short name T6
Test name
Test status
Simulation time 88260227133 ps
CPU time 1039.34 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:49:47 PM PST 23
Peak memory 315660 kb
Host smart-00273e51-0ea8-468a-992f-7cf1805ae577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879990714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1879990714
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.40532502
Short name T9
Test name
Test status
Simulation time 207338318015 ps
CPU time 1109.45 seconds
Started Dec 27 01:31:49 PM PST 23
Finished Dec 27 01:50:19 PM PST 23
Peak memory 419852 kb
Host smart-d9929994-ac16-45d8-a784-4d0f7d95bcf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40532502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress
_all.40532502
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3136597690
Short name T139
Test name
Test status
Simulation time 10682213511 ps
CPU time 24.03 seconds
Started Dec 27 12:57:04 PM PST 23
Finished Dec 27 12:57:37 PM PST 23
Peak memory 215976 kb
Host smart-4c1516e4-8931-4f49-bb0e-edf4b43e5d9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136597690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3136597690
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1341449755
Short name T28
Test name
Test status
Simulation time 6175895125 ps
CPU time 137.86 seconds
Started Dec 27 01:32:12 PM PST 23
Finished Dec 27 01:34:31 PM PST 23
Peak memory 269276 kb
Host smart-6acc6582-0182-449c-9bdc-eeedd0c036b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341449755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1341449755
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3726265360
Short name T218
Test name
Test status
Simulation time 133453632459 ps
CPU time 248.93 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:36:32 PM PST 23
Peak memory 262532 kb
Host smart-8d593f48-57f0-4ca8-a52f-91e702bd580e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726265360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3726265360
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3481639661
Short name T85
Test name
Test status
Simulation time 24930650 ps
CPU time 0.73 seconds
Started Dec 27 12:57:26 PM PST 23
Finished Dec 27 12:57:33 PM PST 23
Peak memory 204892 kb
Host smart-b1b810ba-8803-4b32-a163-3750f7c6637c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481639661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3481639661
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3297617564
Short name T40
Test name
Test status
Simulation time 273003822354 ps
CPU time 505.86 seconds
Started Dec 27 01:34:07 PM PST 23
Finished Dec 27 01:42:33 PM PST 23
Peak memory 270084 kb
Host smart-814160ec-95ed-41ec-b248-dc88e04dad7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297617564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3297617564
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3527065161
Short name T131
Test name
Test status
Simulation time 76822239885 ps
CPU time 257.42 seconds
Started Dec 27 01:30:15 PM PST 23
Finished Dec 27 01:34:36 PM PST 23
Peak memory 257432 kb
Host smart-0b42a8a4-17bb-46ee-a967-13f95df2e442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527065161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3527065161
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1192989345
Short name T132
Test name
Test status
Simulation time 265319521513 ps
CPU time 1065.18 seconds
Started Dec 27 01:32:31 PM PST 23
Finished Dec 27 01:50:22 PM PST 23
Peak memory 298896 kb
Host smart-86e5200f-abfe-449d-9a8c-9cda6b32a7f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192989345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1192989345
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.1078194922
Short name T997
Test name
Test status
Simulation time 38856166 ps
CPU time 0.73 seconds
Started Dec 27 01:30:06 PM PST 23
Finished Dec 27 01:30:12 PM PST 23
Peak memory 216732 kb
Host smart-3292750c-7a46-417d-939c-cc9bdc39f50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078194922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.1078194922
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2189376067
Short name T36
Test name
Test status
Simulation time 41246308890 ps
CPU time 127.78 seconds
Started Dec 27 01:34:24 PM PST 23
Finished Dec 27 01:36:32 PM PST 23
Peak memory 249872 kb
Host smart-125bbf38-c621-41ed-b8e6-85aa15cfb091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189376067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2189376067
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.425950560
Short name T141
Test name
Test status
Simulation time 429158425 ps
CPU time 2.65 seconds
Started Dec 27 12:57:22 PM PST 23
Finished Dec 27 12:57:32 PM PST 23
Peak memory 215976 kb
Host smart-e0d11e6b-e334-4fbc-82e8-995d2a232462
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425950560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.425950560
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3121161510
Short name T237
Test name
Test status
Simulation time 20612401703 ps
CPU time 113.71 seconds
Started Dec 27 01:35:00 PM PST 23
Finished Dec 27 01:36:56 PM PST 23
Peak memory 269492 kb
Host smart-e44ceeac-ed58-43cd-bfa5-3ad01d28de76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121161510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3121161510
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1378691658
Short name T13
Test name
Test status
Simulation time 30833435640 ps
CPU time 68.2 seconds
Started Dec 27 01:37:21 PM PST 23
Finished Dec 27 01:38:30 PM PST 23
Peak memory 257824 kb
Host smart-146217e5-b961-46cb-9af3-a1b46995c980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378691658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1378691658
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_rx_timeout.622386627
Short name T57
Test name
Test status
Simulation time 488467706 ps
CPU time 5.16 seconds
Started Dec 27 01:32:21 PM PST 23
Finished Dec 27 01:32:36 PM PST 23
Peak memory 216848 kb
Host smart-cc3bc1f8-c4c4-4646-87f0-fac2a5637869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622386627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_rx_timeout.622386627
Directory /workspace/19.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.4184558724
Short name T154
Test name
Test status
Simulation time 136924746636 ps
CPU time 292.7 seconds
Started Dec 27 01:32:10 PM PST 23
Finished Dec 27 01:37:04 PM PST 23
Peak memory 266132 kb
Host smart-bf2d9e29-945d-4682-b647-ab10e26bc7ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184558724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.4184558724
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2792582642
Short name T177
Test name
Test status
Simulation time 27670612 ps
CPU time 1.84 seconds
Started Dec 27 12:57:35 PM PST 23
Finished Dec 27 12:57:41 PM PST 23
Peak memory 215868 kb
Host smart-d570603a-ece9-4326-b392-1e7b9c530f16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792582642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2792582642
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.4171245783
Short name T38
Test name
Test status
Simulation time 112600039811 ps
CPU time 412.3 seconds
Started Dec 27 01:31:03 PM PST 23
Finished Dec 27 01:37:56 PM PST 23
Peak memory 273404 kb
Host smart-4379e30b-5041-4418-afdf-20372c7c88cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171245783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.4171245783
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1087578271
Short name T329
Test name
Test status
Simulation time 126910847203 ps
CPU time 440.06 seconds
Started Dec 27 01:36:19 PM PST 23
Finished Dec 27 01:43:41 PM PST 23
Peak memory 274280 kb
Host smart-9c482122-d59a-4a3d-9050-8f9280e9c3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087578271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1087578271
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1411668865
Short name T212
Test name
Test status
Simulation time 13902411 ps
CPU time 0.74 seconds
Started Dec 27 12:57:24 PM PST 23
Finished Dec 27 12:57:31 PM PST 23
Peak memory 204808 kb
Host smart-4e73c825-1471-4331-8e66-7ef4223a8280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411668865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1411668865
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2085800478
Short name T231
Test name
Test status
Simulation time 63193177904 ps
CPU time 519.24 seconds
Started Dec 27 01:31:11 PM PST 23
Finished Dec 27 01:39:51 PM PST 23
Peak memory 273384 kb
Host smart-b81ebe03-5033-4011-af5e-455d769baafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085800478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2085800478
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2444898485
Short name T42
Test name
Test status
Simulation time 4808591772 ps
CPU time 6.14 seconds
Started Dec 27 01:31:30 PM PST 23
Finished Dec 27 01:31:37 PM PST 23
Peak memory 216932 kb
Host smart-ee429fea-6234-4d3f-b0e4-78fdc3ccb8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444898485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2444898485
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.904951086
Short name T266
Test name
Test status
Simulation time 35734785348 ps
CPU time 141.59 seconds
Started Dec 27 01:31:00 PM PST 23
Finished Dec 27 01:33:23 PM PST 23
Peak memory 265144 kb
Host smart-c24d0c59-6989-448f-9f3b-c01fba552d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904951086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
904951086
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.692799575
Short name T110
Test name
Test status
Simulation time 125758877 ps
CPU time 1.06 seconds
Started Dec 27 01:29:50 PM PST 23
Finished Dec 27 01:29:55 PM PST 23
Peak memory 238056 kb
Host smart-592b9a77-502d-4d15-95d5-295f826afd40
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692799575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.692799575
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.855292520
Short name T338
Test name
Test status
Simulation time 6191605276 ps
CPU time 131.44 seconds
Started Dec 27 01:36:59 PM PST 23
Finished Dec 27 01:39:11 PM PST 23
Peak memory 266232 kb
Host smart-9ddb6758-e1f0-41c1-b34b-8e7aa5feeb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855292520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.855292520
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.197293558
Short name T253
Test name
Test status
Simulation time 215212671210 ps
CPU time 404.5 seconds
Started Dec 27 01:37:17 PM PST 23
Finished Dec 27 01:44:03 PM PST 23
Peak memory 257012 kb
Host smart-07236445-2fcc-422f-8275-3338432b43dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197293558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.197293558
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.826233878
Short name T367
Test name
Test status
Simulation time 110450005 ps
CPU time 2.74 seconds
Started Dec 27 12:57:23 PM PST 23
Finished Dec 27 12:57:33 PM PST 23
Peak memory 218812 kb
Host smart-1fc3a6a6-dfa8-4bc1-b28b-d3229056ed9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826233878 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.826233878
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/16.spi_device_bit_transfer.4270136931
Short name T10
Test name
Test status
Simulation time 1707843038 ps
CPU time 3.4 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:32:35 PM PST 23
Peak memory 216888 kb
Host smart-f66e99d5-5d1d-4e53-8133-3c853024e299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270136931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_bit_transfer.4270136931
Directory /workspace/16.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.55971790
Short name T30
Test name
Test status
Simulation time 262677524183 ps
CPU time 411.85 seconds
Started Dec 27 01:32:31 PM PST 23
Finished Dec 27 01:39:28 PM PST 23
Peak memory 266100 kb
Host smart-1c787f01-4322-4371-84c3-092cccbd4d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55971790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.55971790
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.937754718
Short name T311
Test name
Test status
Simulation time 21317226072 ps
CPU time 88.32 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:33:51 PM PST 23
Peak memory 267696 kb
Host smart-ffd758bf-802d-4533-95d8-7752d8f6d5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937754718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.937754718
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3259735915
Short name T59
Test name
Test status
Simulation time 24469702 ps
CPU time 1 seconds
Started Dec 27 01:30:32 PM PST 23
Finished Dec 27 01:30:34 PM PST 23
Peak memory 218828 kb
Host smart-2a743157-996b-493b-83b6-ab6c25ff6431
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259735915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3259735915
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_extreme_fifo_size.201794949
Short name T2
Test name
Test status
Simulation time 683179931339 ps
CPU time 1355.63 seconds
Started Dec 27 01:32:02 PM PST 23
Finished Dec 27 01:54:38 PM PST 23
Peak memory 222124 kb
Host smart-4da839d5-853c-4066-9558-299588b60f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201794949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_extreme_fifo_size.201794949
Directory /workspace/15.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.625252519
Short name T150
Test name
Test status
Simulation time 380624496 ps
CPU time 5.48 seconds
Started Dec 27 12:57:08 PM PST 23
Finished Dec 27 12:57:21 PM PST 23
Peak memory 216016 kb
Host smart-080cc536-e651-4690-81bd-2a2f83c481aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625252519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.625252519
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.142279134
Short name T83
Test name
Test status
Simulation time 13060559 ps
CPU time 0.76 seconds
Started Dec 27 12:57:03 PM PST 23
Finished Dec 27 12:57:12 PM PST 23
Peak memory 204848 kb
Host smart-e1d00f5b-33c0-41e4-ac8e-94530c37ba38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142279134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.142279134
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1321041276
Short name T221
Test name
Test status
Simulation time 625629001 ps
CPU time 19.16 seconds
Started Dec 27 12:57:09 PM PST 23
Finished Dec 27 12:57:36 PM PST 23
Peak memory 215860 kb
Host smart-6bc60266-6fd5-4a5c-9905-32e1d844ec5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321041276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1321041276
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3675277016
Short name T321
Test name
Test status
Simulation time 148219513748 ps
CPU time 504.13 seconds
Started Dec 27 01:32:39 PM PST 23
Finished Dec 27 01:41:06 PM PST 23
Peak memory 267512 kb
Host smart-3d6156f5-1432-4d82-a7a2-af4f09b12884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675277016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3675277016
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.4020487117
Short name T337
Test name
Test status
Simulation time 172885131325 ps
CPU time 387.28 seconds
Started Dec 27 01:32:42 PM PST 23
Finished Dec 27 01:39:10 PM PST 23
Peak memory 272304 kb
Host smart-d720131f-08d5-456c-bcf1-284c87d6f0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020487117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.4020487117
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1443392501
Short name T333
Test name
Test status
Simulation time 135163702547 ps
CPU time 1206.62 seconds
Started Dec 27 01:33:38 PM PST 23
Finished Dec 27 01:53:46 PM PST 23
Peak memory 336616 kb
Host smart-911b7194-d3a0-4365-b779-1054aeedb91e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443392501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1443392501
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.176543523
Short name T219
Test name
Test status
Simulation time 5750351328 ps
CPU time 82.95 seconds
Started Dec 27 01:37:13 PM PST 23
Finished Dec 27 01:38:36 PM PST 23
Peak memory 249912 kb
Host smart-0b2bc91e-c2e6-4fc3-96ab-d771f98d8ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176543523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.176543523
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.657885890
Short name T324
Test name
Test status
Simulation time 99068848293 ps
CPU time 381.07 seconds
Started Dec 27 01:38:34 PM PST 23
Finished Dec 27 01:44:56 PM PST 23
Peak memory 282572 kb
Host smart-2e76de8c-0b36-4368-a51c-ae1b2532a089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657885890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.657885890
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2836500752
Short name T89
Test name
Test status
Simulation time 543168481080 ps
CPU time 2611.31 seconds
Started Dec 27 01:32:14 PM PST 23
Finished Dec 27 02:15:54 PM PST 23
Peak memory 315544 kb
Host smart-e64b614f-95ea-4ae7-b13b-a64489bb2e22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836500752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2836500752
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_extreme_fifo_size.3739355981
Short name T49
Test name
Test status
Simulation time 82439497963 ps
CPU time 1888.29 seconds
Started Dec 27 01:31:12 PM PST 23
Finished Dec 27 02:02:41 PM PST 23
Peak memory 217968 kb
Host smart-8ac49af8-fe16-43f8-9f17-2c8563f56e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739355981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_extreme_fifo_size.3739355981
Directory /workspace/10.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/28.spi_device_extreme_fifo_size.2655663392
Short name T205
Test name
Test status
Simulation time 4075195783 ps
CPU time 24.06 seconds
Started Dec 27 01:33:47 PM PST 23
Finished Dec 27 01:34:12 PM PST 23
Peak memory 231912 kb
Host smart-336861de-928c-4305-9c62-aa55ee177794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655663392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_extreme_fifo_size.2655663392
Directory /workspace/28.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4288666203
Short name T354
Test name
Test status
Simulation time 34210277350 ps
CPU time 50.84 seconds
Started Dec 27 01:33:29 PM PST 23
Finished Dec 27 01:34:21 PM PST 23
Peak memory 257244 kb
Host smart-6ce05a50-25fc-461f-9864-11c1e3736e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288666203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.4288666203
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3231923193
Short name T961
Test name
Test status
Simulation time 7544436808 ps
CPU time 31.55 seconds
Started Dec 27 01:34:04 PM PST 23
Finished Dec 27 01:34:36 PM PST 23
Peak memory 247244 kb
Host smart-8ab534c0-dcce-40a1-9f0c-7b438ae21452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231923193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3231923193
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1879875318
Short name T234
Test name
Test status
Simulation time 7831036794 ps
CPU time 107.24 seconds
Started Dec 27 01:36:55 PM PST 23
Finished Dec 27 01:38:43 PM PST 23
Peak memory 274376 kb
Host smart-578af06d-cc6a-4d7b-851b-49db03d184f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879875318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1879875318
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.163025315
Short name T227
Test name
Test status
Simulation time 64732051077 ps
CPU time 152.84 seconds
Started Dec 27 01:38:29 PM PST 23
Finished Dec 27 01:41:04 PM PST 23
Peak memory 282572 kb
Host smart-f4e9940f-77f0-4b33-b986-945382433ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163025315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.163025315
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1073069903
Short name T23
Test name
Test status
Simulation time 2645068936 ps
CPU time 6.68 seconds
Started Dec 27 01:39:20 PM PST 23
Finished Dec 27 01:39:27 PM PST 23
Peak memory 222536 kb
Host smart-f7863496-fd04-40db-9e96-7777f8832cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073069903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1073069903
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_intr.2922592655
Short name T207
Test name
Test status
Simulation time 59481455905 ps
CPU time 79.67 seconds
Started Dec 27 01:35:02 PM PST 23
Finished Dec 27 01:36:28 PM PST 23
Peak memory 249748 kb
Host smart-cc1673a3-36ff-4d4a-b482-8be9fed23fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922592655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intr.2922592655
Directory /workspace/35.spi_device_intr/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3748399359
Short name T87
Test name
Test status
Simulation time 1172176200 ps
CPU time 6.65 seconds
Started Dec 27 12:57:23 PM PST 23
Finished Dec 27 12:57:36 PM PST 23
Peak memory 215784 kb
Host smart-bbb70fd1-3f6a-463e-9106-ad924d8aa9bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748399359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3748399359
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/34.spi_device_fifo_full.163640415
Short name T480
Test name
Test status
Simulation time 31571046029 ps
CPU time 536.57 seconds
Started Dec 27 01:34:25 PM PST 23
Finished Dec 27 01:43:22 PM PST 23
Peak memory 248980 kb
Host smart-ebc4e24d-5542-4357-b4a8-eafcc0416948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163640415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_fifo_full.163640415
Directory /workspace/34.spi_device_fifo_full/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2026888406
Short name T340
Test name
Test status
Simulation time 6722267410 ps
CPU time 166.07 seconds
Started Dec 27 01:32:15 PM PST 23
Finished Dec 27 01:35:09 PM PST 23
Peak memory 274540 kb
Host smart-a9db2eaa-a00b-4578-9dbf-06fca53ccd3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026888406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2026888406
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_fifo_full.1554430986
Short name T977
Test name
Test status
Simulation time 11615557664 ps
CPU time 209.11 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:35:52 PM PST 23
Peak memory 273596 kb
Host smart-8b0cebbf-7e6f-4da9-afbb-e1d2199687a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554430986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_fifo_full.1554430986
Directory /workspace/15.spi_device_fifo_full/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3299938268
Short name T326
Test name
Test status
Simulation time 103185531636 ps
CPU time 409.79 seconds
Started Dec 27 01:32:13 PM PST 23
Finished Dec 27 01:39:10 PM PST 23
Peak memory 266260 kb
Host smart-20a18db5-94c0-479e-936d-d35f0330daf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299938268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3299938268
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_fifo_underflow_overflow.103052897
Short name T1414
Test name
Test status
Simulation time 110668351343 ps
CPU time 872.48 seconds
Started Dec 27 01:32:31 PM PST 23
Finished Dec 27 01:47:09 PM PST 23
Peak memory 711732 kb
Host smart-21355160-15fd-4525-92c1-077e487e4260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103052897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_fifo_underflow_overfl
ow.103052897
Directory /workspace/21.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2489960242
Short name T345
Test name
Test status
Simulation time 615319461 ps
CPU time 6.67 seconds
Started Dec 27 01:30:29 PM PST 23
Finished Dec 27 01:30:37 PM PST 23
Peak memory 222436 kb
Host smart-e20b637c-39bf-4767-a753-781735a10216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489960242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2489960242
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3075194385
Short name T273
Test name
Test status
Simulation time 35473948211 ps
CPU time 163.51 seconds
Started Dec 27 01:37:52 PM PST 23
Finished Dec 27 01:40:40 PM PST 23
Peak memory 253900 kb
Host smart-e184edb3-181e-4551-a8d1-e2da4026d820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075194385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3075194385
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_abort.4099562877
Short name T93
Test name
Test status
Simulation time 94522951 ps
CPU time 0.76 seconds
Started Dec 27 01:30:16 PM PST 23
Finished Dec 27 01:30:20 PM PST 23
Peak memory 206652 kb
Host smart-4119bccd-898b-4746-8327-d3cad2a2e6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099562877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_abort.4099562877
Directory /workspace/1.spi_device_abort/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1873169361
Short name T540
Test name
Test status
Simulation time 35513470 ps
CPU time 0.7 seconds
Started Dec 27 01:31:15 PM PST 23
Finished Dec 27 01:31:16 PM PST 23
Peak memory 206428 kb
Host smart-fea392e9-8f70-4682-be2b-8be787ed68b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873169361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1873169361
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1172101013
Short name T81
Test name
Test status
Simulation time 390265732 ps
CPU time 3.19 seconds
Started Dec 27 12:57:28 PM PST 23
Finished Dec 27 12:57:38 PM PST 23
Peak memory 215832 kb
Host smart-eec6a95c-f30c-4b7c-be57-57cfa08b1788
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172101013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1172101013
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.spi_device_rx_async_fifo_reset.615014693
Short name T709
Test name
Test status
Simulation time 22554548 ps
CPU time 0.85 seconds
Started Dec 27 01:32:06 PM PST 23
Finished Dec 27 01:32:08 PM PST 23
Peak memory 208404 kb
Host smart-cf37ebf6-7459-43ba-86af-ce4260ce7d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615014693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_rx_async_fifo_reset.615014693
Directory /workspace/13.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/13.spi_device_tx_async_fifo_reset.462372328
Short name T558
Test name
Test status
Simulation time 52725392 ps
CPU time 0.81 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:29 PM PST 23
Peak memory 208396 kb
Host smart-dd1b288e-6360-44b1-85cc-bf75fb6d67f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462372328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tx_async_fifo_reset.462372328
Directory /workspace/13.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1646181632
Short name T203
Test name
Test status
Simulation time 384009265108 ps
CPU time 510.05 seconds
Started Dec 27 01:32:56 PM PST 23
Finished Dec 27 01:41:27 PM PST 23
Peak memory 273416 kb
Host smart-56f2c8ad-a8c9-476b-80c7-cbadb9efed8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646181632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1646181632
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3832885057
Short name T464
Test name
Test status
Simulation time 2210310389 ps
CPU time 28.16 seconds
Started Dec 27 12:57:06 PM PST 23
Finished Dec 27 12:57:43 PM PST 23
Peak memory 215824 kb
Host smart-790fbdb8-0252-476c-b9fd-bce8332635f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832885057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3832885057
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1871653731
Short name T165
Test name
Test status
Simulation time 5595467603 ps
CPU time 14.43 seconds
Started Dec 27 12:57:10 PM PST 23
Finished Dec 27 12:57:33 PM PST 23
Peak memory 215928 kb
Host smart-b2bd2fb1-cf89-4b7c-844d-73e48382671a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871653731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1871653731
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3399655165
Short name T148
Test name
Test status
Simulation time 36793943 ps
CPU time 1.22 seconds
Started Dec 27 12:57:01 PM PST 23
Finished Dec 27 12:57:09 PM PST 23
Peak memory 215776 kb
Host smart-86bc2383-b904-43be-ad6e-09e763d15c7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399655165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3399655165
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2938456869
Short name T407
Test name
Test status
Simulation time 23660742 ps
CPU time 1.28 seconds
Started Dec 27 12:57:11 PM PST 23
Finished Dec 27 12:57:20 PM PST 23
Peak memory 217116 kb
Host smart-a1993ad7-828b-495f-9a11-a76ad81cebfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938456869 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2938456869
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3231045631
Short name T172
Test name
Test status
Simulation time 200893335 ps
CPU time 1.77 seconds
Started Dec 27 12:57:07 PM PST 23
Finished Dec 27 12:57:17 PM PST 23
Peak memory 215780 kb
Host smart-80e05d65-3859-4c3f-9c55-00251c67decc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231045631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
231045631
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3177023029
Short name T441
Test name
Test status
Simulation time 224498318 ps
CPU time 6.41 seconds
Started Dec 27 12:57:35 PM PST 23
Finished Dec 27 12:57:46 PM PST 23
Peak memory 215796 kb
Host smart-93caf57c-cc03-42dd-a4a0-e76ce775596d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177023029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3177023029
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4004506159
Short name T394
Test name
Test status
Simulation time 466255188 ps
CPU time 10.41 seconds
Started Dec 27 12:57:18 PM PST 23
Finished Dec 27 12:57:39 PM PST 23
Peak memory 215716 kb
Host smart-19e3d19f-b8d4-4bcd-a373-38ed8b47ab4b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004506159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.4004506159
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.242312807
Short name T420
Test name
Test status
Simulation time 264786248 ps
CPU time 4.8 seconds
Started Dec 27 12:57:21 PM PST 23
Finished Dec 27 12:57:32 PM PST 23
Peak memory 215836 kb
Host smart-b08f557a-2939-4f4c-86b7-fc14055e07ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242312807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.242312807
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1806607576
Short name T168
Test name
Test status
Simulation time 3497177527 ps
CPU time 21.87 seconds
Started Dec 27 12:57:19 PM PST 23
Finished Dec 27 12:57:48 PM PST 23
Peak memory 215976 kb
Host smart-6957c8d8-1d6d-41c4-b5fc-439cf0bb7e02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806607576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1806607576
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2556317597
Short name T431
Test name
Test status
Simulation time 723769216 ps
CPU time 25.85 seconds
Started Dec 27 12:57:46 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 215780 kb
Host smart-0b32077b-47d2-42f8-b5a0-fe5907c879fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556317597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2556317597
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2404864284
Short name T436
Test name
Test status
Simulation time 4246097460 ps
CPU time 28.24 seconds
Started Dec 27 12:57:24 PM PST 23
Finished Dec 27 12:57:59 PM PST 23
Peak memory 215732 kb
Host smart-a1f6ca46-7d78-49cb-b211-62fafeecfa87
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404864284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2404864284
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4227267646
Short name T465
Test name
Test status
Simulation time 118014767 ps
CPU time 1.18 seconds
Started Dec 27 12:57:22 PM PST 23
Finished Dec 27 12:57:29 PM PST 23
Peak memory 207588 kb
Host smart-c6cb0260-b48f-4f75-9e80-5191fda16406
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227267646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.4227267646
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4224982287
Short name T195
Test name
Test status
Simulation time 339341032 ps
CPU time 1.29 seconds
Started Dec 27 12:57:26 PM PST 23
Finished Dec 27 12:57:33 PM PST 23
Peak memory 217152 kb
Host smart-bf368209-d3c4-4921-af01-b1bf400a5b5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224982287 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4224982287
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1517609934
Short name T435
Test name
Test status
Simulation time 30970869 ps
CPU time 1.97 seconds
Started Dec 27 12:57:26 PM PST 23
Finished Dec 27 12:57:34 PM PST 23
Peak memory 215776 kb
Host smart-0d774d33-2405-4673-bed7-cab9358ad814
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517609934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
517609934
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2447091939
Short name T381
Test name
Test status
Simulation time 50691618 ps
CPU time 0.77 seconds
Started Dec 27 12:57:12 PM PST 23
Finished Dec 27 12:57:21 PM PST 23
Peak memory 204900 kb
Host smart-8b10b88c-527c-4454-a169-1ff6b6ebcdb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447091939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
447091939
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3608217226
Short name T449
Test name
Test status
Simulation time 72432547 ps
CPU time 5.74 seconds
Started Dec 27 12:57:08 PM PST 23
Finished Dec 27 12:57:21 PM PST 23
Peak memory 215736 kb
Host smart-2c66d83d-77b8-4970-a991-5b85b2b5cb6f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608217226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3608217226
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1336588588
Short name T427
Test name
Test status
Simulation time 3671632823 ps
CPU time 5.46 seconds
Started Dec 27 12:57:22 PM PST 23
Finished Dec 27 12:57:34 PM PST 23
Peak memory 215780 kb
Host smart-ff896a95-76be-4960-bf11-07adee7a1ad4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336588588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1336588588
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1976553290
Short name T414
Test name
Test status
Simulation time 30767234 ps
CPU time 1.88 seconds
Started Dec 27 12:57:19 PM PST 23
Finished Dec 27 12:57:28 PM PST 23
Peak memory 215804 kb
Host smart-3c070976-50f9-42e5-953d-4613868e7506
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976553290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1976553290
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3203741673
Short name T142
Test name
Test status
Simulation time 779210415 ps
CPU time 3.79 seconds
Started Dec 27 12:57:08 PM PST 23
Finished Dec 27 12:57:20 PM PST 23
Peak memory 215980 kb
Host smart-86c62b02-eef9-4e4a-8f0a-4363dc39b91e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203741673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
203741673
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1353688504
Short name T451
Test name
Test status
Simulation time 71555625 ps
CPU time 1.91 seconds
Started Dec 27 12:57:22 PM PST 23
Finished Dec 27 12:57:30 PM PST 23
Peak memory 217764 kb
Host smart-53e378c1-9328-4756-9e70-97964be5fe4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353688504 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1353688504
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1696041404
Short name T174
Test name
Test status
Simulation time 118913104 ps
CPU time 2.8 seconds
Started Dec 27 12:57:13 PM PST 23
Finished Dec 27 12:57:24 PM PST 23
Peak memory 207600 kb
Host smart-0dae120b-8190-45cf-801c-f5f564cf31be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696041404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1696041404
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4056864226
Short name T409
Test name
Test status
Simulation time 263146143 ps
CPU time 1.89 seconds
Started Dec 27 12:57:24 PM PST 23
Finished Dec 27 12:57:32 PM PST 23
Peak memory 215792 kb
Host smart-113ee603-286e-4cbd-ad2c-ef6795665470
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056864226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4056864226
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4281673557
Short name T453
Test name
Test status
Simulation time 117029054 ps
CPU time 2.34 seconds
Started Dec 27 12:57:14 PM PST 23
Finished Dec 27 12:57:24 PM PST 23
Peak memory 215940 kb
Host smart-76503777-ef69-4401-873b-d568954e0220
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281673557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4281673557
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1917335972
Short name T404
Test name
Test status
Simulation time 421570799 ps
CPU time 6.61 seconds
Started Dec 27 12:57:28 PM PST 23
Finished Dec 27 12:57:41 PM PST 23
Peak memory 215740 kb
Host smart-78de86ec-6a63-436c-bab3-fdb20ca01952
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917335972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1917335972
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3363403083
Short name T161
Test name
Test status
Simulation time 37426423 ps
CPU time 3.22 seconds
Started Dec 27 12:57:25 PM PST 23
Finished Dec 27 12:57:34 PM PST 23
Peak memory 219284 kb
Host smart-74d1cbe5-fcb1-4bfc-98b1-e7b2d1b40594
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363403083 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3363403083
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2441212979
Short name T171
Test name
Test status
Simulation time 274368912 ps
CPU time 1.93 seconds
Started Dec 27 12:57:13 PM PST 23
Finished Dec 27 12:57:23 PM PST 23
Peak memory 220856 kb
Host smart-422c6dee-0903-4d7d-b487-7996e5c30610
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441212979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2441212979
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4164699143
Short name T384
Test name
Test status
Simulation time 31723616 ps
CPU time 0.76 seconds
Started Dec 27 12:57:31 PM PST 23
Finished Dec 27 12:57:37 PM PST 23
Peak memory 204872 kb
Host smart-16726ca1-daae-4002-b8fc-473ce77bd930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164699143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
4164699143
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.946834820
Short name T457
Test name
Test status
Simulation time 84839839 ps
CPU time 2.07 seconds
Started Dec 27 12:57:40 PM PST 23
Finished Dec 27 12:57:45 PM PST 23
Peak memory 215776 kb
Host smart-d0e707c2-21e2-4843-bbe3-88a9123675f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946834820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.946834820
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3813160244
Short name T389
Test name
Test status
Simulation time 270461771 ps
CPU time 3.39 seconds
Started Dec 27 12:57:52 PM PST 23
Finished Dec 27 12:57:57 PM PST 23
Peak memory 216060 kb
Host smart-e2a646a2-a1bc-4bea-981a-6f8aab420d77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813160244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3813160244
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1495256726
Short name T223
Test name
Test status
Simulation time 224859441 ps
CPU time 7.32 seconds
Started Dec 27 12:57:22 PM PST 23
Finished Dec 27 12:57:39 PM PST 23
Peak memory 215752 kb
Host smart-57a9e0a2-7426-414e-a92b-99bed30fdf4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495256726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1495256726
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1117117066
Short name T397
Test name
Test status
Simulation time 24421699 ps
CPU time 1.37 seconds
Started Dec 27 12:57:29 PM PST 23
Finished Dec 27 12:57:36 PM PST 23
Peak memory 216916 kb
Host smart-7d027e78-6b61-45b5-8882-92a3b13e7ee6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117117066 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1117117066
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2608244531
Short name T390
Test name
Test status
Simulation time 162925867 ps
CPU time 1.9 seconds
Started Dec 27 12:57:27 PM PST 23
Finished Dec 27 12:57:35 PM PST 23
Peak memory 207532 kb
Host smart-71a3ea0a-0b1a-45b6-ba8e-a3ef46fd3df7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608244531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2608244531
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4062607953
Short name T377
Test name
Test status
Simulation time 34909183 ps
CPU time 0.7 seconds
Started Dec 27 12:57:11 PM PST 23
Finished Dec 27 12:57:20 PM PST 23
Peak memory 204952 kb
Host smart-662aafc6-73ec-4d2b-92a9-e399dc9006a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062607953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
4062607953
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3645837983
Short name T402
Test name
Test status
Simulation time 679334927 ps
CPU time 4.15 seconds
Started Dec 27 12:57:22 PM PST 23
Finished Dec 27 12:57:33 PM PST 23
Peak memory 215740 kb
Host smart-c8ed708c-f6cd-4400-8e76-3d13d6279227
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645837983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3645837983
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4042926965
Short name T145
Test name
Test status
Simulation time 91432979 ps
CPU time 2.42 seconds
Started Dec 27 12:57:16 PM PST 23
Finished Dec 27 12:57:26 PM PST 23
Peak memory 215920 kb
Host smart-7e4c71cf-992a-47f4-815d-f2de1c8de5a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042926965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
4042926965
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3355252645
Short name T162
Test name
Test status
Simulation time 2346076104 ps
CPU time 17.7 seconds
Started Dec 27 12:57:22 PM PST 23
Finished Dec 27 12:57:46 PM PST 23
Peak memory 224052 kb
Host smart-cc50f3a8-784b-4c5c-a802-47ecef1f5bd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355252645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3355252645
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4269421121
Short name T433
Test name
Test status
Simulation time 243894202 ps
CPU time 2.99 seconds
Started Dec 27 12:57:23 PM PST 23
Finished Dec 27 12:57:32 PM PST 23
Peak memory 218472 kb
Host smart-324a61c9-da28-4f4a-8647-8ffbe35167fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269421121 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.4269421121
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.4226008201
Short name T471
Test name
Test status
Simulation time 79606340 ps
CPU time 2.13 seconds
Started Dec 27 12:57:20 PM PST 23
Finished Dec 27 12:57:29 PM PST 23
Peak memory 207704 kb
Host smart-271918aa-961a-4268-bd29-24d2eb5c988c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226008201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
4226008201
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3429027879
Short name T86
Test name
Test status
Simulation time 75761482 ps
CPU time 0.74 seconds
Started Dec 27 12:57:13 PM PST 23
Finished Dec 27 12:57:22 PM PST 23
Peak memory 204824 kb
Host smart-78367c8c-afce-4878-8ae2-04e496f3f6db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429027879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3429027879
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1261427130
Short name T454
Test name
Test status
Simulation time 259029836 ps
CPU time 2 seconds
Started Dec 27 12:57:33 PM PST 23
Finished Dec 27 12:57:40 PM PST 23
Peak memory 217136 kb
Host smart-5ceecde2-2ab7-4513-8dc9-cd550f42f778
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261427130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1261427130
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.683892027
Short name T455
Test name
Test status
Simulation time 1510056156 ps
CPU time 17.91 seconds
Started Dec 27 12:57:11 PM PST 23
Finished Dec 27 12:57:37 PM PST 23
Peak memory 215776 kb
Host smart-275954cb-9698-4222-baf6-46f862138518
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683892027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.683892027
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1000417598
Short name T197
Test name
Test status
Simulation time 123082251 ps
CPU time 1.86 seconds
Started Dec 27 12:57:25 PM PST 23
Finished Dec 27 12:57:33 PM PST 23
Peak memory 218192 kb
Host smart-92688448-403d-4cff-94ef-bf61d73f7696
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000417598 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1000417598
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2371090599
Short name T180
Test name
Test status
Simulation time 148278824 ps
CPU time 2.5 seconds
Started Dec 27 12:57:23 PM PST 23
Finished Dec 27 12:57:32 PM PST 23
Peak memory 215856 kb
Host smart-14b9494b-a5c0-4625-8e2d-f0bd2a765f61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371090599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2371090599
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1611390676
Short name T376
Test name
Test status
Simulation time 17791025 ps
CPU time 0.82 seconds
Started Dec 27 12:57:12 PM PST 23
Finished Dec 27 12:57:21 PM PST 23
Peak memory 204884 kb
Host smart-c486c74f-dfcd-48c8-a269-c91e88355e82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611390676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1611390676
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.578385881
Short name T373
Test name
Test status
Simulation time 225713080 ps
CPU time 1.99 seconds
Started Dec 27 12:57:26 PM PST 23
Finished Dec 27 12:57:34 PM PST 23
Peak memory 215736 kb
Host smart-0d10ae56-e1b5-4187-bdf4-1dd16ed3379a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578385881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.578385881
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1491042780
Short name T458
Test name
Test status
Simulation time 261670522 ps
CPU time 1.87 seconds
Started Dec 27 12:57:29 PM PST 23
Finished Dec 27 12:57:37 PM PST 23
Peak memory 215888 kb
Host smart-b212eddf-a6cb-4dfc-9bf9-4a00dc874ccc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491042780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1491042780
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1064822721
Short name T392
Test name
Test status
Simulation time 285378943 ps
CPU time 6.93 seconds
Started Dec 27 12:57:23 PM PST 23
Finished Dec 27 12:57:37 PM PST 23
Peak memory 215700 kb
Host smart-fd962c39-f5e1-4036-9b8c-33fd61f3c6be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064822721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1064822721
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.413006694
Short name T448
Test name
Test status
Simulation time 44146371 ps
CPU time 1.52 seconds
Started Dec 27 12:57:35 PM PST 23
Finished Dec 27 12:57:40 PM PST 23
Peak memory 217208 kb
Host smart-a86f49a0-8257-4feb-9804-e3cf6226a38f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413006694 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.413006694
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.506636550
Short name T428
Test name
Test status
Simulation time 261167278 ps
CPU time 1.91 seconds
Started Dec 27 12:57:48 PM PST 23
Finished Dec 27 12:57:51 PM PST 23
Peak memory 215848 kb
Host smart-2399e1aa-c88a-4ce9-8b01-d2b093ab993b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506636550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.506636550
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3348415962
Short name T386
Test name
Test status
Simulation time 25433056 ps
CPU time 0.74 seconds
Started Dec 27 12:57:13 PM PST 23
Finished Dec 27 12:57:22 PM PST 23
Peak memory 204936 kb
Host smart-4d137a53-7451-43c0-b060-a13db7b097a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348415962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3348415962
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2043637271
Short name T412
Test name
Test status
Simulation time 466303870 ps
CPU time 3.36 seconds
Started Dec 27 12:57:22 PM PST 23
Finished Dec 27 12:57:31 PM PST 23
Peak memory 215744 kb
Host smart-64aee5cd-8b39-4682-a25a-86bd87b9e6cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043637271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2043637271
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3114009848
Short name T443
Test name
Test status
Simulation time 281135760 ps
CPU time 4.12 seconds
Started Dec 27 12:57:42 PM PST 23
Finished Dec 27 12:57:48 PM PST 23
Peak memory 215832 kb
Host smart-51a41edd-778e-4e1a-afef-4980cb0ae714
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114009848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3114009848
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1850461298
Short name T176
Test name
Test status
Simulation time 115792712 ps
CPU time 7.02 seconds
Started Dec 27 12:57:26 PM PST 23
Finished Dec 27 12:57:39 PM PST 23
Peak memory 215836 kb
Host smart-724e8820-a7c9-4d59-b347-189bb4d61715
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850461298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1850461298
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1100087182
Short name T417
Test name
Test status
Simulation time 80211313 ps
CPU time 2.35 seconds
Started Dec 27 12:57:41 PM PST 23
Finished Dec 27 12:57:50 PM PST 23
Peak memory 217904 kb
Host smart-fc3c1b25-4269-4348-95a7-2a9a6a2b9586
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100087182 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1100087182
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2763599197
Short name T450
Test name
Test status
Simulation time 40445099 ps
CPU time 0.77 seconds
Started Dec 27 12:57:24 PM PST 23
Finished Dec 27 12:57:32 PM PST 23
Peak memory 204872 kb
Host smart-453c808a-29c5-4f0b-8def-c55c3943134e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763599197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2763599197
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1997119744
Short name T187
Test name
Test status
Simulation time 61426783 ps
CPU time 4.15 seconds
Started Dec 27 12:57:54 PM PST 23
Finished Dec 27 12:57:59 PM PST 23
Peak memory 215828 kb
Host smart-a0438af3-1788-41b3-b0e5-897f088f51b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997119744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1997119744
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2839534340
Short name T462
Test name
Test status
Simulation time 2261435039 ps
CPU time 4 seconds
Started Dec 27 12:57:30 PM PST 23
Finished Dec 27 12:57:39 PM PST 23
Peak memory 216100 kb
Host smart-6bf28e45-42ce-4d6c-851a-0dfb9b2d2cb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839534340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2839534340
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3443746448
Short name T445
Test name
Test status
Simulation time 894260249 ps
CPU time 23.53 seconds
Started Dec 27 12:57:32 PM PST 23
Finished Dec 27 12:58:01 PM PST 23
Peak memory 215720 kb
Host smart-7f1eb75c-8ccc-4086-878f-c273dd7aa972
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443746448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3443746448
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3902124058
Short name T80
Test name
Test status
Simulation time 53888601 ps
CPU time 1.4 seconds
Started Dec 27 12:57:24 PM PST 23
Finished Dec 27 12:57:32 PM PST 23
Peak memory 216924 kb
Host smart-7fd483bb-fd5a-4818-9e43-391c67783e32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902124058 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3902124058
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3915586472
Short name T416
Test name
Test status
Simulation time 67033045 ps
CPU time 1.3 seconds
Started Dec 27 12:57:40 PM PST 23
Finished Dec 27 12:57:44 PM PST 23
Peak memory 215804 kb
Host smart-7cdea63e-97a0-49e0-bc06-7ce9219ae20e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915586472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3915586472
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2120597096
Short name T362
Test name
Test status
Simulation time 254154992 ps
CPU time 1.89 seconds
Started Dec 27 12:57:34 PM PST 23
Finished Dec 27 12:57:40 PM PST 23
Peak memory 207696 kb
Host smart-3fd0c300-a28f-4cf8-bfa3-56e308cf6e0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120597096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2120597096
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.753716089
Short name T396
Test name
Test status
Simulation time 75442981 ps
CPU time 1.75 seconds
Started Dec 27 12:57:28 PM PST 23
Finished Dec 27 12:57:37 PM PST 23
Peak memory 215876 kb
Host smart-9724e899-9a3c-4562-a893-818e09ab1147
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753716089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.753716089
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3808823686
Short name T170
Test name
Test status
Simulation time 5883305413 ps
CPU time 16.03 seconds
Started Dec 27 12:57:25 PM PST 23
Finished Dec 27 12:57:48 PM PST 23
Peak memory 215880 kb
Host smart-546d6720-c777-4942-b5f1-93617d39792f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808823686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3808823686
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2242887858
Short name T439
Test name
Test status
Simulation time 53036387 ps
CPU time 2.49 seconds
Started Dec 27 12:57:26 PM PST 23
Finished Dec 27 12:57:35 PM PST 23
Peak memory 219828 kb
Host smart-5e831983-82e8-4742-a537-e7c60c555d28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242887858 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2242887858
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2087841158
Short name T434
Test name
Test status
Simulation time 102219133 ps
CPU time 2.34 seconds
Started Dec 27 12:57:14 PM PST 23
Finished Dec 27 12:57:24 PM PST 23
Peak memory 215848 kb
Host smart-70681f55-4e5f-44c7-a020-c5a99489e84f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087841158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2087841158
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4078529913
Short name T380
Test name
Test status
Simulation time 50327698 ps
CPU time 0.72 seconds
Started Dec 27 12:57:40 PM PST 23
Finished Dec 27 12:57:44 PM PST 23
Peak memory 204880 kb
Host smart-bac2b687-200c-4b1d-8dc0-ffe931080c79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078529913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
4078529913
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1962764856
Short name T198
Test name
Test status
Simulation time 212098661 ps
CPU time 4.52 seconds
Started Dec 27 12:57:26 PM PST 23
Finished Dec 27 12:57:37 PM PST 23
Peak memory 215640 kb
Host smart-9067ac95-cd69-4561-a4ab-a3ff89536096
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962764856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1962764856
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2567836537
Short name T398
Test name
Test status
Simulation time 204960150 ps
CPU time 6.33 seconds
Started Dec 27 12:57:34 PM PST 23
Finished Dec 27 12:57:45 PM PST 23
Peak memory 216000 kb
Host smart-75fa4488-fe43-46bc-9409-2b8483e1788d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567836537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2567836537
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3548465842
Short name T440
Test name
Test status
Simulation time 212248885 ps
CPU time 13.45 seconds
Started Dec 27 12:57:38 PM PST 23
Finished Dec 27 12:57:55 PM PST 23
Peak memory 215780 kb
Host smart-9dd9d44c-b841-4613-b728-8c725a10cede
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548465842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3548465842
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3428064137
Short name T437
Test name
Test status
Simulation time 30057502 ps
CPU time 1.5 seconds
Started Dec 27 12:57:28 PM PST 23
Finished Dec 27 12:57:37 PM PST 23
Peak memory 217100 kb
Host smart-5b7acd9f-b090-4d2a-840a-01fc2e53dd0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428064137 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3428064137
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2949763432
Short name T400
Test name
Test status
Simulation time 31083693 ps
CPU time 1.97 seconds
Started Dec 27 12:57:40 PM PST 23
Finished Dec 27 12:57:45 PM PST 23
Peak memory 215764 kb
Host smart-14670590-856d-468f-a385-4733b7d671a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949763432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2949763432
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3448865270
Short name T199
Test name
Test status
Simulation time 50868644 ps
CPU time 0.75 seconds
Started Dec 27 12:57:27 PM PST 23
Finished Dec 27 12:57:35 PM PST 23
Peak memory 204956 kb
Host smart-d0809a22-4d2e-453d-b59e-a84480f55673
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448865270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3448865270
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2686820977
Short name T137
Test name
Test status
Simulation time 295337511 ps
CPU time 2.12 seconds
Started Dec 27 12:57:56 PM PST 23
Finished Dec 27 12:58:00 PM PST 23
Peak memory 215744 kb
Host smart-ed12ab8d-814f-44db-bc94-1e95cb539f7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686820977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2686820977
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2162351875
Short name T146
Test name
Test status
Simulation time 49300555 ps
CPU time 3.84 seconds
Started Dec 27 12:57:26 PM PST 23
Finished Dec 27 12:57:36 PM PST 23
Peak memory 215952 kb
Host smart-0c000ffb-57c1-45ff-aa4a-f218b0adf1b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162351875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2162351875
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4064204374
Short name T461
Test name
Test status
Simulation time 1205035629 ps
CPU time 8.37 seconds
Started Dec 27 12:58:08 PM PST 23
Finished Dec 27 12:58:25 PM PST 23
Peak memory 215800 kb
Host smart-e72c96ba-abf0-4a00-9393-0b6eadb7693b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064204374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.4064204374
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3144862010
Short name T366
Test name
Test status
Simulation time 142270383 ps
CPU time 9.31 seconds
Started Dec 27 12:57:15 PM PST 23
Finished Dec 27 12:57:32 PM PST 23
Peak memory 215760 kb
Host smart-8705d097-9dc3-42a4-9dff-611c8f2eed29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144862010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3144862010
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.414554601
Short name T425
Test name
Test status
Simulation time 1397591979 ps
CPU time 14.15 seconds
Started Dec 27 12:57:10 PM PST 23
Finished Dec 27 12:57:32 PM PST 23
Peak memory 207564 kb
Host smart-b1093be1-a9bb-4383-add3-b858c2784b60
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414554601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.414554601
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2993523079
Short name T149
Test name
Test status
Simulation time 18470852 ps
CPU time 0.97 seconds
Started Dec 27 12:57:30 PM PST 23
Finished Dec 27 12:57:37 PM PST 23
Peak memory 207400 kb
Host smart-b3c7b21c-c80c-48e9-99f0-14023883bd1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993523079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2993523079
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.769390456
Short name T473
Test name
Test status
Simulation time 122738499 ps
CPU time 3.21 seconds
Started Dec 27 12:57:07 PM PST 23
Finished Dec 27 12:57:18 PM PST 23
Peak memory 218592 kb
Host smart-4589c7e4-15b2-4ca2-891c-b0e651a99447
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769390456 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.769390456
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.961285037
Short name T421
Test name
Test status
Simulation time 339317611 ps
CPU time 2.12 seconds
Started Dec 27 12:57:10 PM PST 23
Finished Dec 27 12:57:20 PM PST 23
Peak memory 215856 kb
Host smart-14109c4d-338f-48d2-95bf-1be564793771
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961285037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.961285037
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4196540451
Short name T466
Test name
Test status
Simulation time 41941447 ps
CPU time 0.78 seconds
Started Dec 27 12:57:27 PM PST 23
Finished Dec 27 12:57:34 PM PST 23
Peak memory 204804 kb
Host smart-1fb2cc00-d9bd-4e87-9a14-257d622c633a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196540451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.4
196540451
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3529159262
Short name T173
Test name
Test status
Simulation time 223372622 ps
CPU time 4.5 seconds
Started Dec 27 12:57:05 PM PST 23
Finished Dec 27 12:57:18 PM PST 23
Peak memory 215788 kb
Host smart-50ceb353-75af-47da-b8c9-2caae459b606
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529159262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3529159262
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3098554013
Short name T403
Test name
Test status
Simulation time 1737881844 ps
CPU time 14.49 seconds
Started Dec 27 12:57:17 PM PST 23
Finished Dec 27 12:57:38 PM PST 23
Peak memory 215768 kb
Host smart-f4ba4e88-875f-46da-9b83-d44ac0b9a801
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098554013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3098554013
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.747550558
Short name T385
Test name
Test status
Simulation time 28320953 ps
CPU time 1.73 seconds
Started Dec 27 12:57:24 PM PST 23
Finished Dec 27 12:57:33 PM PST 23
Peak memory 215796 kb
Host smart-191e455c-8ecb-48d5-8da9-b27e74f8796c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747550558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.747550558
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1377562448
Short name T147
Test name
Test status
Simulation time 60320322 ps
CPU time 2.1 seconds
Started Dec 27 12:57:26 PM PST 23
Finished Dec 27 12:57:34 PM PST 23
Peak memory 215848 kb
Host smart-6688bf18-701b-4da0-bb8d-586a4323012d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377562448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
377562448
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.637483456
Short name T430
Test name
Test status
Simulation time 443839915 ps
CPU time 7.34 seconds
Started Dec 27 12:57:24 PM PST 23
Finished Dec 27 12:57:38 PM PST 23
Peak memory 215616 kb
Host smart-720f3c10-9a5a-4ca0-8e84-fff44a4240fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637483456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.637483456
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3585772078
Short name T419
Test name
Test status
Simulation time 14568645 ps
CPU time 0.68 seconds
Started Dec 27 12:57:27 PM PST 23
Finished Dec 27 12:57:34 PM PST 23
Peak memory 204864 kb
Host smart-1fac4ba8-91cd-493f-90d5-3f1245f4e172
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585772078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3585772078
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3045057801
Short name T368
Test name
Test status
Simulation time 43656162 ps
CPU time 0.77 seconds
Started Dec 27 12:57:25 PM PST 23
Finished Dec 27 12:57:33 PM PST 23
Peak memory 204836 kb
Host smart-056a4c1b-7347-482d-a042-0ac48a20987a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045057801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3045057801
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1171487005
Short name T365
Test name
Test status
Simulation time 25281816 ps
CPU time 0.73 seconds
Started Dec 27 12:57:34 PM PST 23
Finished Dec 27 12:57:39 PM PST 23
Peak memory 204828 kb
Host smart-ea9e249f-7a56-4129-9c4a-978ec61fa4b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171487005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1171487005
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2178208950
Short name T405
Test name
Test status
Simulation time 38580009 ps
CPU time 0.69 seconds
Started Dec 27 12:58:10 PM PST 23
Finished Dec 27 12:58:21 PM PST 23
Peak memory 204936 kb
Host smart-47bf386c-b87a-43be-bfc0-04564fbba513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178208950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2178208950
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1708177619
Short name T84
Test name
Test status
Simulation time 12720192 ps
CPU time 0.71 seconds
Started Dec 27 12:57:48 PM PST 23
Finished Dec 27 12:57:50 PM PST 23
Peak memory 204872 kb
Host smart-76df6ea7-7ff1-4b5f-a641-30865af9bff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708177619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1708177619
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1575001215
Short name T472
Test name
Test status
Simulation time 171634906 ps
CPU time 0.69 seconds
Started Dec 27 12:58:20 PM PST 23
Finished Dec 27 12:58:34 PM PST 23
Peak memory 204940 kb
Host smart-f7248f0a-4a20-4362-9505-0a63c555ae75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575001215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1575001215
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3586088916
Short name T388
Test name
Test status
Simulation time 37771385 ps
CPU time 0.68 seconds
Started Dec 27 12:57:28 PM PST 23
Finished Dec 27 12:57:36 PM PST 23
Peak memory 204960 kb
Host smart-c659ec96-3345-4567-b3bd-6128910d902a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586088916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3586088916
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.186543754
Short name T438
Test name
Test status
Simulation time 33222748 ps
CPU time 0.76 seconds
Started Dec 27 12:57:47 PM PST 23
Finished Dec 27 12:57:49 PM PST 23
Peak memory 204952 kb
Host smart-8807fd0c-728f-4bd7-a475-b8c531950e44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186543754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.186543754
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2357370014
Short name T406
Test name
Test status
Simulation time 72556293 ps
CPU time 0.74 seconds
Started Dec 27 12:57:55 PM PST 23
Finished Dec 27 12:57:57 PM PST 23
Peak memory 204936 kb
Host smart-5b01507f-9045-451c-8095-ca7539cc26f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357370014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2357370014
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.425953953
Short name T200
Test name
Test status
Simulation time 47771131 ps
CPU time 0.73 seconds
Started Dec 27 12:57:55 PM PST 23
Finished Dec 27 12:57:57 PM PST 23
Peak memory 204872 kb
Host smart-b78dc8ff-c2e2-475c-a55f-dcc0cf7ea3c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425953953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.425953953
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2367766671
Short name T202
Test name
Test status
Simulation time 11704283126 ps
CPU time 18.63 seconds
Started Dec 27 12:57:16 PM PST 23
Finished Dec 27 12:57:42 PM PST 23
Peak memory 207768 kb
Host smart-c60f344e-0a1f-4fc1-85cd-733f8c9116b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367766671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2367766671
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.831308504
Short name T361
Test name
Test status
Simulation time 2784706664 ps
CPU time 14.23 seconds
Started Dec 27 12:57:13 PM PST 23
Finished Dec 27 12:57:35 PM PST 23
Peak memory 207772 kb
Host smart-0650e386-d2ae-4603-bed6-a77c70d3d803
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831308504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.831308504
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1436845680
Short name T82
Test name
Test status
Simulation time 317884575 ps
CPU time 1.22 seconds
Started Dec 27 12:57:14 PM PST 23
Finished Dec 27 12:57:23 PM PST 23
Peak memory 207552 kb
Host smart-be31dcf4-720b-4d32-9e95-6ab856964b2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436845680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1436845680
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.319476336
Short name T379
Test name
Test status
Simulation time 21058873 ps
CPU time 1.29 seconds
Started Dec 27 12:57:07 PM PST 23
Finished Dec 27 12:57:17 PM PST 23
Peak memory 217328 kb
Host smart-e75bad12-274b-4b3a-9d0b-610a1af25f00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319476336 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.319476336
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1347581496
Short name T183
Test name
Test status
Simulation time 41178494 ps
CPU time 2.41 seconds
Started Dec 27 12:57:12 PM PST 23
Finished Dec 27 12:57:23 PM PST 23
Peak memory 215780 kb
Host smart-2ae5eebb-ac38-4bbe-9461-fd68381a956f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347581496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
347581496
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3277357581
Short name T432
Test name
Test status
Simulation time 88861338 ps
CPU time 0.71 seconds
Started Dec 27 12:57:19 PM PST 23
Finished Dec 27 12:57:27 PM PST 23
Peak memory 204928 kb
Host smart-26a3434a-22be-41e9-aa8d-50f141737651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277357581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
277357581
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1891717102
Short name T178
Test name
Test status
Simulation time 106171736 ps
CPU time 2.66 seconds
Started Dec 27 12:57:06 PM PST 23
Finished Dec 27 12:57:17 PM PST 23
Peak memory 215760 kb
Host smart-27fc5ac2-d945-4357-abdf-803d052a1be9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891717102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1891717102
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.556361116
Short name T175
Test name
Test status
Simulation time 884492979 ps
CPU time 10.21 seconds
Started Dec 27 12:57:14 PM PST 23
Finished Dec 27 12:57:32 PM PST 23
Peak memory 215708 kb
Host smart-bbd660bd-df00-4b6c-b429-d4c851115fc9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556361116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.556361116
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2219686606
Short name T391
Test name
Test status
Simulation time 117909700 ps
CPU time 3.07 seconds
Started Dec 27 12:57:04 PM PST 23
Finished Dec 27 12:57:15 PM PST 23
Peak memory 216912 kb
Host smart-9070f022-d368-42b8-84b2-fca47cde1a20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219686606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2219686606
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3103514518
Short name T408
Test name
Test status
Simulation time 325000552 ps
CPU time 4.83 seconds
Started Dec 27 12:57:19 PM PST 23
Finished Dec 27 12:57:31 PM PST 23
Peak memory 216020 kb
Host smart-f7dee83d-b00c-4ea2-bf43-43d66f832597
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103514518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
103514518
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1864291487
Short name T418
Test name
Test status
Simulation time 2121849398 ps
CPU time 19.78 seconds
Started Dec 27 12:57:22 PM PST 23
Finished Dec 27 12:57:49 PM PST 23
Peak memory 216428 kb
Host smart-52c0e5d5-01f7-4ce0-bdb8-9f3e717edb73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864291487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1864291487
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.995041276
Short name T456
Test name
Test status
Simulation time 19677579 ps
CPU time 0.8 seconds
Started Dec 27 12:57:59 PM PST 23
Finished Dec 27 12:58:03 PM PST 23
Peak memory 204940 kb
Host smart-c6955f51-ce76-43a8-a70f-ec5ebad02482
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995041276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.995041276
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.755343998
Short name T393
Test name
Test status
Simulation time 37294377 ps
CPU time 0.7 seconds
Started Dec 27 12:57:46 PM PST 23
Finished Dec 27 12:57:48 PM PST 23
Peak memory 204944 kb
Host smart-79fba85d-aa02-4b62-b14b-6ec53d18871d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755343998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.755343998
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1720844574
Short name T378
Test name
Test status
Simulation time 24259110 ps
CPU time 0.77 seconds
Started Dec 27 12:57:48 PM PST 23
Finished Dec 27 12:57:50 PM PST 23
Peak memory 204940 kb
Host smart-8609652e-fb1b-49cf-809b-018478f6d3f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720844574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1720844574
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2441690643
Short name T444
Test name
Test status
Simulation time 15717011 ps
CPU time 0.75 seconds
Started Dec 27 12:57:44 PM PST 23
Finished Dec 27 12:57:47 PM PST 23
Peak memory 204932 kb
Host smart-72772e9c-f8c2-44dc-bb9e-5af84c930031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441690643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2441690643
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2362510875
Short name T423
Test name
Test status
Simulation time 12906313 ps
CPU time 0.74 seconds
Started Dec 27 12:57:55 PM PST 23
Finished Dec 27 12:57:58 PM PST 23
Peak memory 204900 kb
Host smart-751d369c-586f-4b88-af31-2ac05179e659
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362510875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2362510875
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1070499090
Short name T369
Test name
Test status
Simulation time 20436878 ps
CPU time 0.68 seconds
Started Dec 27 12:57:53 PM PST 23
Finished Dec 27 12:57:55 PM PST 23
Peak memory 204948 kb
Host smart-d4c53193-5bff-449e-b480-1e714548a26e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070499090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1070499090
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4037799518
Short name T401
Test name
Test status
Simulation time 36157639 ps
CPU time 0.83 seconds
Started Dec 27 12:57:49 PM PST 23
Finished Dec 27 12:57:51 PM PST 23
Peak memory 204900 kb
Host smart-5e2194bc-157a-435c-8fb9-e72d52866914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037799518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
4037799518
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1986880642
Short name T422
Test name
Test status
Simulation time 47348014 ps
CPU time 0.71 seconds
Started Dec 27 12:57:59 PM PST 23
Finished Dec 27 12:58:03 PM PST 23
Peak memory 204900 kb
Host smart-980c3a76-5bd9-42f6-9e1c-7d940080bc85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986880642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1986880642
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2404340690
Short name T363
Test name
Test status
Simulation time 11703725 ps
CPU time 0.71 seconds
Started Dec 27 12:57:40 PM PST 23
Finished Dec 27 12:57:43 PM PST 23
Peak memory 204904 kb
Host smart-1e4bb232-6853-4d49-a464-7a8e9310dcf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404340690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2404340690
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2448946135
Short name T371
Test name
Test status
Simulation time 17974575 ps
CPU time 0.83 seconds
Started Dec 27 12:57:30 PM PST 23
Finished Dec 27 12:57:36 PM PST 23
Peak memory 204876 kb
Host smart-132c428e-2e02-4302-ba94-c091ebfe82fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448946135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2448946135
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3979670464
Short name T185
Test name
Test status
Simulation time 736362845 ps
CPU time 18.73 seconds
Started Dec 27 12:57:11 PM PST 23
Finished Dec 27 12:57:38 PM PST 23
Peak memory 215832 kb
Host smart-7cec5ae1-e794-45a6-988f-95373d9978a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979670464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3979670464
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2962077982
Short name T181
Test name
Test status
Simulation time 580138874 ps
CPU time 34.18 seconds
Started Dec 27 12:57:19 PM PST 23
Finished Dec 27 12:58:01 PM PST 23
Peak memory 215756 kb
Host smart-09dce021-ebc6-4edc-a0be-d84026d1c72e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962077982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2962077982
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.675963054
Short name T446
Test name
Test status
Simulation time 191875418 ps
CPU time 1.41 seconds
Started Dec 27 12:57:21 PM PST 23
Finished Dec 27 12:57:29 PM PST 23
Peak memory 207492 kb
Host smart-4ecf05c1-16be-49fa-a78d-fe3b292ab848
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675963054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.675963054
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1451422364
Short name T375
Test name
Test status
Simulation time 89813404 ps
CPU time 2.82 seconds
Started Dec 27 12:57:21 PM PST 23
Finished Dec 27 12:57:30 PM PST 23
Peak memory 218312 kb
Host smart-656b46ed-8f69-4451-a8f4-3b78a9e3d4a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451422364 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1451422364
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3624835211
Short name T447
Test name
Test status
Simulation time 38265341 ps
CPU time 2.54 seconds
Started Dec 27 12:57:19 PM PST 23
Finished Dec 27 12:57:29 PM PST 23
Peak memory 215792 kb
Host smart-cfb0f944-bf23-454e-ad37-4668198afd86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624835211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
624835211
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3870179613
Short name T370
Test name
Test status
Simulation time 49128647 ps
CPU time 0.73 seconds
Started Dec 27 12:57:03 PM PST 23
Finished Dec 27 12:57:12 PM PST 23
Peak memory 204904 kb
Host smart-97cf2c24-08fe-43ec-8924-d57a859ab65e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870179613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
870179613
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3366181386
Short name T184
Test name
Test status
Simulation time 563827365 ps
CPU time 5.93 seconds
Started Dec 27 12:57:11 PM PST 23
Finished Dec 27 12:57:25 PM PST 23
Peak memory 215720 kb
Host smart-64c3fc02-a5ab-4be1-adaa-7c9a0bd0d25c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366181386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3366181386
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1784341908
Short name T372
Test name
Test status
Simulation time 2726884325 ps
CPU time 15.78 seconds
Started Dec 27 12:57:16 PM PST 23
Finished Dec 27 12:57:39 PM PST 23
Peak memory 215800 kb
Host smart-3e875134-aa36-4f8b-a242-b0a06d8fcf15
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784341908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1784341908
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4041023876
Short name T163
Test name
Test status
Simulation time 66527929 ps
CPU time 2.16 seconds
Started Dec 27 12:57:21 PM PST 23
Finished Dec 27 12:57:29 PM PST 23
Peak memory 215716 kb
Host smart-d1558b9e-e458-43f6-95f9-54475a0c0f55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041023876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.4041023876
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.617440477
Short name T429
Test name
Test status
Simulation time 283363282 ps
CPU time 2.09 seconds
Started Dec 27 12:57:19 PM PST 23
Finished Dec 27 12:57:28 PM PST 23
Peak memory 215968 kb
Host smart-83e42b74-f634-4aa7-907b-0d26757cd3cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617440477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.617440477
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.776593613
Short name T222
Test name
Test status
Simulation time 580940926 ps
CPU time 18.4 seconds
Started Dec 27 12:57:10 PM PST 23
Finished Dec 27 12:57:37 PM PST 23
Peak memory 215736 kb
Host smart-06e4a735-d06c-4485-afac-9add3b5076d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776593613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.776593613
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2087274246
Short name T442
Test name
Test status
Simulation time 32443627 ps
CPU time 0.78 seconds
Started Dec 27 12:57:31 PM PST 23
Finished Dec 27 12:57:37 PM PST 23
Peak memory 204884 kb
Host smart-bd8ff2b3-e7d0-4968-9c6e-6d032ce75267
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087274246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2087274246
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3182707772
Short name T463
Test name
Test status
Simulation time 26467484 ps
CPU time 0.74 seconds
Started Dec 27 12:57:38 PM PST 23
Finished Dec 27 12:57:41 PM PST 23
Peak memory 204884 kb
Host smart-5764ba5d-1211-4055-8331-3c4dcef8dd55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182707772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3182707772
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2048480704
Short name T411
Test name
Test status
Simulation time 34497890 ps
CPU time 0.7 seconds
Started Dec 27 12:57:54 PM PST 23
Finished Dec 27 12:57:56 PM PST 23
Peak memory 204952 kb
Host smart-e2dfbc7a-d534-45e7-92a5-75c75f9743e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048480704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2048480704
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1637374826
Short name T410
Test name
Test status
Simulation time 14026812 ps
CPU time 0.8 seconds
Started Dec 27 12:57:53 PM PST 23
Finished Dec 27 12:57:55 PM PST 23
Peak memory 204892 kb
Host smart-d3101cc9-67db-4617-815d-6e9cca88c199
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637374826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1637374826
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1432739704
Short name T201
Test name
Test status
Simulation time 48146306 ps
CPU time 0.72 seconds
Started Dec 27 12:57:27 PM PST 23
Finished Dec 27 12:57:34 PM PST 23
Peak memory 204936 kb
Host smart-57de464c-bcfe-49d6-8f55-f8da84c8b81b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432739704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1432739704
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3062363752
Short name T364
Test name
Test status
Simulation time 83141159 ps
CPU time 0.8 seconds
Started Dec 27 12:57:58 PM PST 23
Finished Dec 27 12:58:02 PM PST 23
Peak memory 204896 kb
Host smart-e66de810-39b3-42aa-ad4b-13c9f250be6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062363752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3062363752
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2666370808
Short name T469
Test name
Test status
Simulation time 24827136 ps
CPU time 0.71 seconds
Started Dec 27 12:57:29 PM PST 23
Finished Dec 27 12:57:36 PM PST 23
Peak memory 204876 kb
Host smart-1fb0a8e7-7394-4f17-8169-15c2dcfe0c2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666370808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2666370808
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2467510147
Short name T383
Test name
Test status
Simulation time 65196129 ps
CPU time 0.77 seconds
Started Dec 27 12:57:34 PM PST 23
Finished Dec 27 12:57:39 PM PST 23
Peak memory 204944 kb
Host smart-05f8fbed-2dfe-4aac-8e6c-80e31e5f3ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467510147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2467510147
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.912401120
Short name T426
Test name
Test status
Simulation time 21359934 ps
CPU time 0.74 seconds
Started Dec 27 12:57:26 PM PST 23
Finished Dec 27 12:57:41 PM PST 23
Peak memory 204964 kb
Host smart-52f7e051-81e9-4da3-90ba-ee56e0217abc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912401120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.912401120
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3563612987
Short name T387
Test name
Test status
Simulation time 43704673 ps
CPU time 0.78 seconds
Started Dec 27 12:57:28 PM PST 23
Finished Dec 27 12:57:36 PM PST 23
Peak memory 204928 kb
Host smart-8ac4ca36-0d9e-4605-aba0-29de65fadc88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563612987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3563612987
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1555059401
Short name T166
Test name
Test status
Simulation time 183550695 ps
CPU time 1.73 seconds
Started Dec 27 12:57:21 PM PST 23
Finished Dec 27 12:57:29 PM PST 23
Peak memory 218548 kb
Host smart-59b490be-af36-491e-979f-db8faf3bc8a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555059401 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1555059401
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4007591879
Short name T186
Test name
Test status
Simulation time 19538151 ps
CPU time 1.37 seconds
Started Dec 27 12:57:19 PM PST 23
Finished Dec 27 12:57:28 PM PST 23
Peak memory 207508 kb
Host smart-c0bcbeaa-4bfb-4fc9-b9be-00f6282929a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007591879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.4
007591879
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.592035973
Short name T459
Test name
Test status
Simulation time 46741644 ps
CPU time 0.73 seconds
Started Dec 27 12:57:13 PM PST 23
Finished Dec 27 12:57:21 PM PST 23
Peak memory 204924 kb
Host smart-4bdc8ed6-dd94-432d-bac0-d9d86c30e87b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592035973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.592035973
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3562412653
Short name T474
Test name
Test status
Simulation time 111888064 ps
CPU time 1.95 seconds
Started Dec 27 12:57:05 PM PST 23
Finished Dec 27 12:57:16 PM PST 23
Peak memory 215776 kb
Host smart-c540971b-eac8-471a-9777-314ff78c1eab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562412653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3562412653
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2073507622
Short name T106
Test name
Test status
Simulation time 571973899 ps
CPU time 13.99 seconds
Started Dec 27 12:57:17 PM PST 23
Finished Dec 27 12:57:39 PM PST 23
Peak memory 215824 kb
Host smart-0ba65dc0-ed61-4885-b110-972078967070
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073507622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2073507622
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2674564830
Short name T415
Test name
Test status
Simulation time 91518242 ps
CPU time 1.76 seconds
Started Dec 27 12:57:06 PM PST 23
Finished Dec 27 12:57:16 PM PST 23
Peak memory 218004 kb
Host smart-10906015-fe92-4de0-b8c7-690453ff016e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674564830 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2674564830
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3162262376
Short name T467
Test name
Test status
Simulation time 51466352 ps
CPU time 1.74 seconds
Started Dec 27 12:57:10 PM PST 23
Finished Dec 27 12:57:20 PM PST 23
Peak memory 215848 kb
Host smart-fb06d74c-edb4-4793-9ff0-495257a2e752
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162262376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
162262376
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.978168643
Short name T424
Test name
Test status
Simulation time 46026269 ps
CPU time 0.69 seconds
Started Dec 27 12:57:22 PM PST 23
Finished Dec 27 12:57:29 PM PST 23
Peak memory 204856 kb
Host smart-9c552504-c023-4d34-9326-8e62c4eac5dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978168643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.978168643
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.364581258
Short name T196
Test name
Test status
Simulation time 152581731 ps
CPU time 3.32 seconds
Started Dec 27 12:57:09 PM PST 23
Finished Dec 27 12:57:20 PM PST 23
Peak memory 215752 kb
Host smart-7d42f09b-f7a2-484e-8b79-97e3efa63d46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364581258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.364581258
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2323949106
Short name T151
Test name
Test status
Simulation time 272633977 ps
CPU time 4.89 seconds
Started Dec 27 12:57:28 PM PST 23
Finished Dec 27 12:57:40 PM PST 23
Peak memory 216012 kb
Host smart-2e6874ca-b2ac-4062-9904-645642311647
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323949106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
323949106
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2779230763
Short name T182
Test name
Test status
Simulation time 43659645 ps
CPU time 1.33 seconds
Started Dec 27 12:57:26 PM PST 23
Finished Dec 27 12:57:33 PM PST 23
Peak memory 215788 kb
Host smart-c9f8e1f5-8b50-426f-a888-59ab7e585f0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779230763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
779230763
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2142704084
Short name T395
Test name
Test status
Simulation time 18379131 ps
CPU time 0.79 seconds
Started Dec 27 12:57:15 PM PST 23
Finished Dec 27 12:57:24 PM PST 23
Peak memory 204928 kb
Host smart-3817965d-3cef-44fb-b68c-c0c727d632e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142704084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
142704084
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4048290484
Short name T167
Test name
Test status
Simulation time 459054632 ps
CPU time 3.02 seconds
Started Dec 27 12:57:27 PM PST 23
Finished Dec 27 12:57:37 PM PST 23
Peak memory 215784 kb
Host smart-e44e02c1-09bc-48a2-884f-42160e2ed023
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048290484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.4048290484
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1439881607
Short name T468
Test name
Test status
Simulation time 316754819 ps
CPU time 4.47 seconds
Started Dec 27 12:57:16 PM PST 23
Finished Dec 27 12:57:28 PM PST 23
Peak memory 215924 kb
Host smart-37c671a3-b49c-4662-95b7-d73b21f55d31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439881607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
439881607
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1217409141
Short name T460
Test name
Test status
Simulation time 789988387 ps
CPU time 12.09 seconds
Started Dec 27 12:57:32 PM PST 23
Finished Dec 27 12:57:50 PM PST 23
Peak memory 215824 kb
Host smart-731713b2-7186-49a0-bf90-221b54142eda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217409141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1217409141
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.788452664
Short name T413
Test name
Test status
Simulation time 134602132 ps
CPU time 2.56 seconds
Started Dec 27 12:57:15 PM PST 23
Finished Dec 27 12:57:25 PM PST 23
Peak memory 218600 kb
Host smart-282d1b10-f69d-41c4-961c-de6ea384e167
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788452664 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.788452664
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3120939200
Short name T179
Test name
Test status
Simulation time 254238956 ps
CPU time 2.08 seconds
Started Dec 27 12:57:18 PM PST 23
Finished Dec 27 12:57:28 PM PST 23
Peak memory 215868 kb
Host smart-f7598720-c832-497c-aa1b-97d07e1ce09c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120939200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
120939200
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3892286923
Short name T374
Test name
Test status
Simulation time 58308504 ps
CPU time 0.73 seconds
Started Dec 27 12:57:18 PM PST 23
Finished Dec 27 12:57:26 PM PST 23
Peak memory 204924 kb
Host smart-9a2cf6e4-1c22-4293-9930-30dc7be78062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892286923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
892286923
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2919891741
Short name T382
Test name
Test status
Simulation time 260890570 ps
CPU time 4.43 seconds
Started Dec 27 12:57:28 PM PST 23
Finished Dec 27 12:57:39 PM PST 23
Peak memory 215784 kb
Host smart-64101406-f2d7-431d-aa99-45b88d5ced7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919891741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2919891741
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.754594291
Short name T399
Test name
Test status
Simulation time 155904385 ps
CPU time 4.49 seconds
Started Dec 27 12:57:16 PM PST 23
Finished Dec 27 12:57:28 PM PST 23
Peak memory 215944 kb
Host smart-6e7e0d83-165a-4fc2-957f-86e3e061eea3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754594291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.754594291
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3704444543
Short name T140
Test name
Test status
Simulation time 29926517 ps
CPU time 2.54 seconds
Started Dec 27 12:57:22 PM PST 23
Finished Dec 27 12:57:31 PM PST 23
Peak memory 218304 kb
Host smart-bb80c0c7-87ff-4802-9e15-7db9c2f45b46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704444543 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3704444543
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3089209192
Short name T452
Test name
Test status
Simulation time 105627828 ps
CPU time 2.56 seconds
Started Dec 27 12:57:18 PM PST 23
Finished Dec 27 12:57:29 PM PST 23
Peak memory 207664 kb
Host smart-fa0ef7df-8927-4dab-a283-2606abcd9814
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089209192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
089209192
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1194698692
Short name T164
Test name
Test status
Simulation time 12383953 ps
CPU time 0.68 seconds
Started Dec 27 12:57:15 PM PST 23
Finished Dec 27 12:57:24 PM PST 23
Peak memory 204956 kb
Host smart-fcc0f645-aea5-4ae3-8be6-bd335e64cdf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194698692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
194698692
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.919770340
Short name T470
Test name
Test status
Simulation time 325538605 ps
CPU time 3.01 seconds
Started Dec 27 12:57:07 PM PST 23
Finished Dec 27 12:57:18 PM PST 23
Peak memory 215692 kb
Host smart-68e1f441-3977-427d-bb44-cb30b01a8a7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919770340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.919770340
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2139210298
Short name T144
Test name
Test status
Simulation time 110543842 ps
CPU time 1.89 seconds
Started Dec 27 12:57:40 PM PST 23
Finished Dec 27 12:57:44 PM PST 23
Peak memory 216032 kb
Host smart-f63afcd4-b949-4eea-bac8-3e4136a2ff2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139210298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
139210298
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.4063345375
Short name T169
Test name
Test status
Simulation time 631632981 ps
CPU time 8.11 seconds
Started Dec 27 12:57:23 PM PST 23
Finished Dec 27 12:57:38 PM PST 23
Peak memory 215804 kb
Host smart-49579a30-bc1e-4995-9124-a7c4b0a35737
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063345375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.4063345375
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_abort.2695354883
Short name T1450
Test name
Test status
Simulation time 43465812 ps
CPU time 0.72 seconds
Started Dec 27 01:30:27 PM PST 23
Finished Dec 27 01:30:29 PM PST 23
Peak memory 206616 kb
Host smart-494a1d81-43d0-4f40-a1b1-2f0f47bd9e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695354883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_abort.2695354883
Directory /workspace/0.spi_device_abort/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3476317158
Short name T1040
Test name
Test status
Simulation time 14163445 ps
CPU time 0.71 seconds
Started Dec 27 01:29:54 PM PST 23
Finished Dec 27 01:29:59 PM PST 23
Peak memory 206540 kb
Host smart-f476f151-1fd3-4ee1-8ef2-2f1bebca5249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476317158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
476317158
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_bit_transfer.1379441746
Short name T1201
Test name
Test status
Simulation time 3661201632 ps
CPU time 2.15 seconds
Started Dec 27 01:30:38 PM PST 23
Finished Dec 27 01:30:42 PM PST 23
Peak memory 216856 kb
Host smart-98406fc6-9722-4e26-a6f5-741bfb70eb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379441746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_bit_transfer.1379441746
Directory /workspace/0.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/0.spi_device_byte_transfer.3469024767
Short name T1722
Test name
Test status
Simulation time 636828739 ps
CPU time 2.68 seconds
Started Dec 27 01:29:27 PM PST 23
Finished Dec 27 01:29:31 PM PST 23
Peak memory 216868 kb
Host smart-d501ae75-3e71-4302-8b5d-cc90674348e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469024767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_byte_transfer.3469024767
Directory /workspace/0.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2656393738
Short name T1582
Test name
Test status
Simulation time 291033730 ps
CPU time 3.75 seconds
Started Dec 27 01:30:23 PM PST 23
Finished Dec 27 01:30:28 PM PST 23
Peak memory 239776 kb
Host smart-77df77c1-ae3c-48b1-9e68-0521fb98feb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656393738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2656393738
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2635435342
Short name T839
Test name
Test status
Simulation time 25598770 ps
CPU time 0.75 seconds
Started Dec 27 01:29:44 PM PST 23
Finished Dec 27 01:29:46 PM PST 23
Peak memory 206576 kb
Host smart-2405e40f-12bb-4bf5-9fcb-9b8f78fc7659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635435342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2635435342
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_dummy_item_extra_dly.1714644880
Short name T1630
Test name
Test status
Simulation time 43624216231 ps
CPU time 963.33 seconds
Started Dec 27 01:29:57 PM PST 23
Finished Dec 27 01:46:03 PM PST 23
Peak memory 260800 kb
Host smart-ee83a5b0-23c3-4e67-8a2d-f361cc70265a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714644880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_dummy_item_extra_dly.1714644880
Directory /workspace/0.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/0.spi_device_extreme_fifo_size.3783700897
Short name T1249
Test name
Test status
Simulation time 60151812451 ps
CPU time 736.8 seconds
Started Dec 27 01:30:16 PM PST 23
Finished Dec 27 01:42:36 PM PST 23
Peak memory 218784 kb
Host smart-3048b33e-3e53-4641-84a3-e8a49310c414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783700897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_extreme_fifo_size.3783700897
Directory /workspace/0.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/0.spi_device_fifo_full.3985325401
Short name T476
Test name
Test status
Simulation time 27410936437 ps
CPU time 320.28 seconds
Started Dec 27 01:30:06 PM PST 23
Finished Dec 27 01:35:32 PM PST 23
Peak memory 268788 kb
Host smart-2f2fc227-e84d-42d2-80cc-266e9f9b50b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985325401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_fifo_full.3985325401
Directory /workspace/0.spi_device_fifo_full/latest

Test location /workspace/coverage/default/0.spi_device_fifo_underflow_overflow.3036811038
Short name T612
Test name
Test status
Simulation time 15534872275 ps
CPU time 161.79 seconds
Started Dec 27 01:30:15 PM PST 23
Finished Dec 27 01:33:01 PM PST 23
Peak memory 343556 kb
Host smart-5f7af9e8-78ab-4484-943e-f2a436b498f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036811038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_fifo_underflow_overfl
ow.3036811038
Directory /workspace/0.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2216961261
Short name T78
Test name
Test status
Simulation time 85717678003 ps
CPU time 113.3 seconds
Started Dec 27 01:30:14 PM PST 23
Finished Dec 27 01:32:12 PM PST 23
Peak memory 262964 kb
Host smart-e22cbd61-4291-40a7-977d-38bed4a99a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216961261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2216961261
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1476650002
Short name T233
Test name
Test status
Simulation time 58533971196 ps
CPU time 43.83 seconds
Started Dec 27 01:30:03 PM PST 23
Finished Dec 27 01:30:48 PM PST 23
Peak memory 257164 kb
Host smart-6986f713-7ba4-4470-9ded-bf98c3cf431c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476650002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1476650002
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2067357617
Short name T1678
Test name
Test status
Simulation time 44325134345 ps
CPU time 209.68 seconds
Started Dec 27 01:30:21 PM PST 23
Finished Dec 27 01:33:53 PM PST 23
Peak memory 267140 kb
Host smart-7a21930f-6b10-4bda-9e37-f671fcecaf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067357617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2067357617
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.861886149
Short name T51
Test name
Test status
Simulation time 1685224497 ps
CPU time 8.97 seconds
Started Dec 27 01:30:25 PM PST 23
Finished Dec 27 01:30:36 PM PST 23
Peak memory 239528 kb
Host smart-3882a176-80d5-481c-a2ee-294bb25a3eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861886149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.861886149
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2695420935
Short name T1315
Test name
Test status
Simulation time 1762176379 ps
CPU time 7.86 seconds
Started Dec 27 01:30:19 PM PST 23
Finished Dec 27 01:30:29 PM PST 23
Peak memory 241348 kb
Host smart-bef423f6-2ec4-441d-910a-9afe0207a38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695420935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2695420935
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_intr.3059282567
Short name T846
Test name
Test status
Simulation time 14617892464 ps
CPU time 14.68 seconds
Started Dec 27 01:30:09 PM PST 23
Finished Dec 27 01:30:27 PM PST 23
Peak memory 218788 kb
Host smart-d0c5e49c-291b-4f00-b08b-32c7491c1a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059282567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intr.3059282567
Directory /workspace/0.spi_device_intr/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3014568375
Short name T1561
Test name
Test status
Simulation time 1108339058 ps
CPU time 5.78 seconds
Started Dec 27 01:30:21 PM PST 23
Finished Dec 27 01:30:28 PM PST 23
Peak memory 241416 kb
Host smart-cfac6ea5-a726-43c5-9941-4b1bc7e2089d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014568375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3014568375
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1223730264
Short name T1338
Test name
Test status
Simulation time 117255728 ps
CPU time 1.09 seconds
Started Dec 27 01:30:01 PM PST 23
Finished Dec 27 01:30:04 PM PST 23
Peak memory 218864 kb
Host smart-3bd72b37-5720-43ee-b522-1b5be7834e26
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223730264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1223730264
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.710762763
Short name T1443
Test name
Test status
Simulation time 6065946206 ps
CPU time 7.42 seconds
Started Dec 27 01:30:14 PM PST 23
Finished Dec 27 01:30:26 PM PST 23
Peak memory 223496 kb
Host smart-424985fd-b95f-4e70-8cbc-6158924b126f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710762763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
710762763
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3234566858
Short name T1580
Test name
Test status
Simulation time 2119303851 ps
CPU time 5.83 seconds
Started Dec 27 01:30:19 PM PST 23
Finished Dec 27 01:30:27 PM PST 23
Peak memory 219484 kb
Host smart-f3512cb2-0d82-4161-bdea-2a69a28ccfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234566858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3234566858
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_perf.3075435973
Short name T1455
Test name
Test status
Simulation time 46864473846 ps
CPU time 779.64 seconds
Started Dec 27 01:30:04 PM PST 23
Finished Dec 27 01:43:05 PM PST 23
Peak memory 264392 kb
Host smart-2f966948-2fd4-415d-acf2-4c70c74a8821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075435973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_perf.3075435973
Directory /workspace/0.spi_device_perf/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3072678896
Short name T1668
Test name
Test status
Simulation time 16038241 ps
CPU time 0.72 seconds
Started Dec 27 01:29:57 PM PST 23
Finished Dec 27 01:30:00 PM PST 23
Peak memory 216728 kb
Host smart-52320e1c-45aa-43ff-ac62-1aea6859ac9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072678896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3072678896
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3988582608
Short name T869
Test name
Test status
Simulation time 464095160 ps
CPU time 3.45 seconds
Started Dec 27 01:30:32 PM PST 23
Finished Dec 27 01:30:36 PM PST 23
Peak memory 219972 kb
Host smart-b1bf86d4-05df-44cf-a5f0-3f2abd5362f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3988582608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3988582608
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_rx_async_fifo_reset.514630161
Short name T1157
Test name
Test status
Simulation time 179246102 ps
CPU time 0.95 seconds
Started Dec 27 01:30:19 PM PST 23
Finished Dec 27 01:30:22 PM PST 23
Peak memory 208448 kb
Host smart-11581e85-00b5-439a-a209-91c20b835d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514630161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_rx_async_fifo_reset.514630161
Directory /workspace/0.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/0.spi_device_rx_timeout.3545340575
Short name T1540
Test name
Test status
Simulation time 3703500729 ps
CPU time 6.25 seconds
Started Dec 27 01:30:20 PM PST 23
Finished Dec 27 01:30:28 PM PST 23
Peak memory 216748 kb
Host smart-25ce84ba-5128-438f-841f-5880a59f154c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545340575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_rx_timeout.3545340575
Directory /workspace/0.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/0.spi_device_smoke.310767439
Short name T874
Test name
Test status
Simulation time 107714485 ps
CPU time 1.25 seconds
Started Dec 27 01:30:00 PM PST 23
Finished Dec 27 01:30:03 PM PST 23
Peak memory 216832 kb
Host smart-afa8c735-0952-47a0-a749-52c20a518e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310767439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_smoke.310767439
Directory /workspace/0.spi_device_smoke/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.4032011414
Short name T1615
Test name
Test status
Simulation time 119471673002 ps
CPU time 1337.02 seconds
Started Dec 27 01:30:03 PM PST 23
Finished Dec 27 01:52:21 PM PST 23
Peak memory 266216 kb
Host smart-6f8120cb-0605-47b8-9a3a-8ead7a59f91e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032011414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.4032011414
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.4078691873
Short name T1516
Test name
Test status
Simulation time 32976132324 ps
CPU time 177.58 seconds
Started Dec 27 01:30:23 PM PST 23
Finished Dec 27 01:33:22 PM PST 23
Peak memory 222728 kb
Host smart-4560c088-03db-4da8-b9cf-441ab5921bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078691873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4078691873
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2434255925
Short name T595
Test name
Test status
Simulation time 33732825644 ps
CPU time 25.45 seconds
Started Dec 27 01:30:06 PM PST 23
Finished Dec 27 01:30:35 PM PST 23
Peak memory 216912 kb
Host smart-d1ae42d1-5c08-4af1-8c12-4b62cb2626e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434255925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2434255925
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1195069047
Short name T126
Test name
Test status
Simulation time 116424975 ps
CPU time 1.42 seconds
Started Dec 27 01:30:26 PM PST 23
Finished Dec 27 01:30:29 PM PST 23
Peak memory 216784 kb
Host smart-0f233779-9da1-4e1c-a0e8-8b35b371c219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195069047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1195069047
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2999685661
Short name T1565
Test name
Test status
Simulation time 102322036 ps
CPU time 0.8 seconds
Started Dec 27 01:30:29 PM PST 23
Finished Dec 27 01:30:31 PM PST 23
Peak memory 206840 kb
Host smart-23ce8491-4c34-491b-ab29-40491f9964ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999685661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2999685661
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_tx_async_fifo_reset.2503559483
Short name T1063
Test name
Test status
Simulation time 31170835 ps
CPU time 0.76 seconds
Started Dec 27 01:30:03 PM PST 23
Finished Dec 27 01:30:06 PM PST 23
Peak memory 208448 kb
Host smart-2c7c1b44-4828-4f1d-9c53-7e8bd81dbe20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503559483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tx_async_fifo_reset.2503559483
Directory /workspace/0.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/0.spi_device_txrx.3383659451
Short name T600
Test name
Test status
Simulation time 62867089992 ps
CPU time 865.19 seconds
Started Dec 27 01:29:49 PM PST 23
Finished Dec 27 01:44:19 PM PST 23
Peak memory 297980 kb
Host smart-fcfcbe0b-7148-4798-b4b3-a7f545550209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383659451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_txrx.3383659451
Directory /workspace/0.spi_device_txrx/latest

Test location /workspace/coverage/default/0.spi_device_upload.4084308107
Short name T934
Test name
Test status
Simulation time 1120653814 ps
CPU time 8.41 seconds
Started Dec 27 01:30:24 PM PST 23
Finished Dec 27 01:30:33 PM PST 23
Peak memory 234700 kb
Host smart-31098281-0824-4a14-96c6-a3943873286f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084308107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.4084308107
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2426333525
Short name T1057
Test name
Test status
Simulation time 12988599 ps
CPU time 0.78 seconds
Started Dec 27 01:30:37 PM PST 23
Finished Dec 27 01:30:39 PM PST 23
Peak memory 206428 kb
Host smart-da1b9b6f-4ed3-4b8a-a790-2b5e821bcf32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426333525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
426333525
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_bit_transfer.1942069652
Short name T1538
Test name
Test status
Simulation time 115227382 ps
CPU time 2.61 seconds
Started Dec 27 01:30:40 PM PST 23
Finished Dec 27 01:30:44 PM PST 23
Peak memory 216796 kb
Host smart-2e9bae9e-e762-46bd-9052-20e15ad2d9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942069652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_bit_transfer.1942069652
Directory /workspace/1.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/1.spi_device_byte_transfer.3652978163
Short name T1281
Test name
Test status
Simulation time 185012240 ps
CPU time 2.77 seconds
Started Dec 27 01:30:11 PM PST 23
Finished Dec 27 01:30:16 PM PST 23
Peak memory 216772 kb
Host smart-565c99da-9ed3-4f56-83b9-3900cbe78e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652978163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_byte_transfer.3652978163
Directory /workspace/1.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.909969577
Short name T1361
Test name
Test status
Simulation time 3393621926 ps
CPU time 11.62 seconds
Started Dec 27 01:30:26 PM PST 23
Finished Dec 27 01:30:39 PM PST 23
Peak memory 221124 kb
Host smart-9e5e4658-6b93-48fe-bf06-f6f7e6e55538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909969577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.909969577
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_dummy_item_extra_dly.4022726412
Short name T1445
Test name
Test status
Simulation time 51268960780 ps
CPU time 108.36 seconds
Started Dec 27 01:30:18 PM PST 23
Finished Dec 27 01:32:09 PM PST 23
Peak memory 249680 kb
Host smart-4707a28e-0cdb-427a-b508-6d8df49e9876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022726412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_dummy_item_extra_dly.4022726412
Directory /workspace/1.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/1.spi_device_extreme_fifo_size.1587614518
Short name T1394
Test name
Test status
Simulation time 71199591409 ps
CPU time 1195.87 seconds
Started Dec 27 01:30:03 PM PST 23
Finished Dec 27 01:50:01 PM PST 23
Peak memory 221224 kb
Host smart-35a2280b-6f26-44b9-9863-3fb44a8385d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587614518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_extreme_fifo_size.1587614518
Directory /workspace/1.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/1.spi_device_fifo_full.3311825934
Short name T1179
Test name
Test status
Simulation time 184133887335 ps
CPU time 845.57 seconds
Started Dec 27 01:30:07 PM PST 23
Finished Dec 27 01:44:18 PM PST 23
Peak memory 248116 kb
Host smart-1925c480-14cb-4c70-b13b-5d3d024b6c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311825934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_fifo_full.3311825934
Directory /workspace/1.spi_device_fifo_full/latest

Test location /workspace/coverage/default/1.spi_device_fifo_underflow_overflow.3705635768
Short name T1280
Test name
Test status
Simulation time 161620846388 ps
CPU time 715.47 seconds
Started Dec 27 01:30:04 PM PST 23
Finished Dec 27 01:42:01 PM PST 23
Peak memory 519056 kb
Host smart-85d0d0e9-4b9f-467a-bcc6-9f389e9d266d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705635768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_fifo_underflow_overfl
ow.3705635768
Directory /workspace/1.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2156089992
Short name T894
Test name
Test status
Simulation time 108182501898 ps
CPU time 105.49 seconds
Started Dec 27 01:30:09 PM PST 23
Finished Dec 27 01:31:58 PM PST 23
Peak memory 274344 kb
Host smart-fcfc4fd4-e549-4137-98e3-13fa0bcd105b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156089992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2156089992
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1978838404
Short name T1610
Test name
Test status
Simulation time 30673142062 ps
CPU time 43.31 seconds
Started Dec 27 01:30:18 PM PST 23
Finished Dec 27 01:31:04 PM PST 23
Peak memory 232592 kb
Host smart-1286eb05-7c9a-47a4-8378-f6a9ff80fdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978838404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1978838404
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3112325645
Short name T143
Test name
Test status
Simulation time 320988253 ps
CPU time 3.98 seconds
Started Dec 27 01:29:55 PM PST 23
Finished Dec 27 01:30:02 PM PST 23
Peak memory 219832 kb
Host smart-f7e6668e-cd21-4d32-8071-fb2da19c2b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112325645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3112325645
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_intr.2030848206
Short name T75
Test name
Test status
Simulation time 18974174857 ps
CPU time 76.53 seconds
Started Dec 27 01:29:55 PM PST 23
Finished Dec 27 01:31:15 PM PST 23
Peak memory 232424 kb
Host smart-238e549d-4d83-49cf-a9a6-1beed8c1299a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030848206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intr.2030848206
Directory /workspace/1.spi_device_intr/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3693530979
Short name T1631
Test name
Test status
Simulation time 26537875173 ps
CPU time 23.3 seconds
Started Dec 27 01:30:17 PM PST 23
Finished Dec 27 01:30:43 PM PST 23
Peak memory 247676 kb
Host smart-daaf4e5d-55f1-4820-ad40-93d5edd715f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693530979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3693530979
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1503085360
Short name T1088
Test name
Test status
Simulation time 861379603 ps
CPU time 5.31 seconds
Started Dec 27 01:30:09 PM PST 23
Finished Dec 27 01:30:18 PM PST 23
Peak memory 241116 kb
Host smart-35603849-9c02-44dc-a84e-d948d3790a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503085360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1503085360
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_perf.493500380
Short name T1371
Test name
Test status
Simulation time 20697124430 ps
CPU time 390.36 seconds
Started Dec 27 01:30:08 PM PST 23
Finished Dec 27 01:36:43 PM PST 23
Peak memory 266192 kb
Host smart-b2c6d84c-889a-4380-994d-7c584b14ec8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493500380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_perf.493500380
Directory /workspace/1.spi_device_perf/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2792959024
Short name T769
Test name
Test status
Simulation time 2018135003 ps
CPU time 5.82 seconds
Started Dec 27 01:30:15 PM PST 23
Finished Dec 27 01:30:24 PM PST 23
Peak memory 219896 kb
Host smart-f8d22e47-e032-4891-a4ef-ac69612cd3e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2792959024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2792959024
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_rx_async_fifo_reset.2144512358
Short name T1132
Test name
Test status
Simulation time 22025368 ps
CPU time 0.84 seconds
Started Dec 27 01:30:33 PM PST 23
Finished Dec 27 01:30:35 PM PST 23
Peak memory 208384 kb
Host smart-0a51ad16-fc73-46af-b369-f93ac4bbad37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144512358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_rx_async_fifo_reset.2144512358
Directory /workspace/1.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/1.spi_device_rx_timeout.4014628017
Short name T847
Test name
Test status
Simulation time 1772410722 ps
CPU time 4.74 seconds
Started Dec 27 01:30:03 PM PST 23
Finished Dec 27 01:30:09 PM PST 23
Peak memory 216720 kb
Host smart-37cf1a60-542f-46e4-b674-1af342b4efc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014628017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_rx_timeout.4014628017
Directory /workspace/1.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2759197097
Short name T109
Test name
Test status
Simulation time 64829141 ps
CPU time 1.09 seconds
Started Dec 27 01:30:41 PM PST 23
Finished Dec 27 01:30:43 PM PST 23
Peak memory 238156 kb
Host smart-b796cfa1-cd2f-4975-b7f2-3d5a15d8f9a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759197097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2759197097
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_smoke.1243561831
Short name T834
Test name
Test status
Simulation time 60240470 ps
CPU time 1.18 seconds
Started Dec 27 01:29:55 PM PST 23
Finished Dec 27 01:30:00 PM PST 23
Peak memory 216432 kb
Host smart-509c8a01-a255-41d2-9022-c1275b26d1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243561831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_smoke.1243561831
Directory /workspace/1.spi_device_smoke/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3888798498
Short name T824
Test name
Test status
Simulation time 5243046497 ps
CPU time 39.64 seconds
Started Dec 27 01:29:55 PM PST 23
Finished Dec 27 01:30:38 PM PST 23
Peak memory 218216 kb
Host smart-643c9daa-14c8-489a-9f03-bdaf5bdff399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888798498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3888798498
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2697518
Short name T714
Test name
Test status
Simulation time 4719213770 ps
CPU time 9.08 seconds
Started Dec 27 01:30:11 PM PST 23
Finished Dec 27 01:30:23 PM PST 23
Peak memory 216860 kb
Host smart-ee6a62a4-b569-4661-92fa-162c530c3f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2697518
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2676578964
Short name T1493
Test name
Test status
Simulation time 494720521 ps
CPU time 8.16 seconds
Started Dec 27 01:30:01 PM PST 23
Finished Dec 27 01:30:11 PM PST 23
Peak memory 216848 kb
Host smart-a5784808-de27-4e66-a8a1-7e579915222a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676578964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2676578964
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.368029391
Short name T705
Test name
Test status
Simulation time 91474349 ps
CPU time 0.94 seconds
Started Dec 27 01:30:28 PM PST 23
Finished Dec 27 01:30:30 PM PST 23
Peak memory 206896 kb
Host smart-4b21256f-ddf5-4bfb-bf91-86833714b5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368029391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.368029391
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_tx_async_fifo_reset.3585729671
Short name T741
Test name
Test status
Simulation time 13497730 ps
CPU time 0.79 seconds
Started Dec 27 01:30:12 PM PST 23
Finished Dec 27 01:30:17 PM PST 23
Peak memory 208452 kb
Host smart-a9b6b4ae-0e55-4379-b127-8eab72705e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585729671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tx_async_fifo_reset.3585729671
Directory /workspace/1.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/1.spi_device_txrx.628107642
Short name T1732
Test name
Test status
Simulation time 49364336268 ps
CPU time 168.49 seconds
Started Dec 27 01:30:14 PM PST 23
Finished Dec 27 01:33:07 PM PST 23
Peak memory 288576 kb
Host smart-7b8a41a8-f746-4fb3-aeaf-58c6a819eb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628107642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_txrx.628107642
Directory /workspace/1.spi_device_txrx/latest

Test location /workspace/coverage/default/1.spi_device_upload.3568877311
Short name T1661
Test name
Test status
Simulation time 14953307086 ps
CPU time 14.12 seconds
Started Dec 27 01:30:12 PM PST 23
Finished Dec 27 01:30:30 PM PST 23
Peak memory 239592 kb
Host smart-c778e035-6754-4acb-a612-014141ebcc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568877311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3568877311
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_abort.3468444617
Short name T1332
Test name
Test status
Simulation time 60071767 ps
CPU time 0.73 seconds
Started Dec 27 01:31:46 PM PST 23
Finished Dec 27 01:31:48 PM PST 23
Peak memory 206632 kb
Host smart-a276fde5-137d-460a-8d43-c7d5e46a30ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468444617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_abort.3468444617
Directory /workspace/10.spi_device_abort/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2780607391
Short name T1687
Test name
Test status
Simulation time 54810100 ps
CPU time 0.7 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:28 PM PST 23
Peak memory 206460 kb
Host smart-290b7b44-d83f-45c4-81c9-c6f2c1a99566
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780607391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2780607391
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_bit_transfer.1410057267
Short name T945
Test name
Test status
Simulation time 363652196 ps
CPU time 2.27 seconds
Started Dec 27 01:32:27 PM PST 23
Finished Dec 27 01:32:36 PM PST 23
Peak memory 216892 kb
Host smart-c5863b5a-75fe-454c-887e-349e78c97fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410057267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_bit_transfer.1410057267
Directory /workspace/10.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/10.spi_device_byte_transfer.2832257921
Short name T1461
Test name
Test status
Simulation time 174941595 ps
CPU time 2.36 seconds
Started Dec 27 01:31:50 PM PST 23
Finished Dec 27 01:31:53 PM PST 23
Peak memory 216756 kb
Host smart-3ab00fdb-df06-46b8-93b6-d7ac7d489c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832257921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_byte_transfer.2832257921
Directory /workspace/10.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.4070545609
Short name T283
Test name
Test status
Simulation time 359409809 ps
CPU time 2.59 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:29 PM PST 23
Peak memory 218156 kb
Host smart-85b5e17d-a1a1-48a4-bdde-028cec8d2907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070545609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.4070545609
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3087585462
Short name T102
Test name
Test status
Simulation time 15543313 ps
CPU time 0.75 seconds
Started Dec 27 01:31:13 PM PST 23
Finished Dec 27 01:31:15 PM PST 23
Peak memory 206556 kb
Host smart-3fa749eb-aa77-4c69-8543-14c566958c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087585462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3087585462
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_dummy_item_extra_dly.1405277061
Short name T638
Test name
Test status
Simulation time 128762300445 ps
CPU time 492.08 seconds
Started Dec 27 01:32:12 PM PST 23
Finished Dec 27 01:40:26 PM PST 23
Peak memory 319548 kb
Host smart-567d6e06-b1f0-445b-86bb-1c27d7ee8a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405277061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_dummy_item_extra_dly.1405277061
Directory /workspace/10.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/10.spi_device_fifo_full.2264757536
Short name T896
Test name
Test status
Simulation time 144262164658 ps
CPU time 420.94 seconds
Started Dec 27 01:31:12 PM PST 23
Finished Dec 27 01:38:13 PM PST 23
Peak memory 290628 kb
Host smart-2ec28bf8-75ce-49ca-b7e9-80be5abc2c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264757536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_fifo_full.2264757536
Directory /workspace/10.spi_device_fifo_full/latest

Test location /workspace/coverage/default/10.spi_device_fifo_underflow_overflow.3387301411
Short name T1267
Test name
Test status
Simulation time 153275161280 ps
CPU time 601.54 seconds
Started Dec 27 01:31:34 PM PST 23
Finished Dec 27 01:41:37 PM PST 23
Peak memory 439364 kb
Host smart-3d34abb1-455d-47b4-859d-34feafb48191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387301411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_fifo_underflow_overf
low.3387301411
Directory /workspace/10.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1060959434
Short name T255
Test name
Test status
Simulation time 7402302390 ps
CPU time 101.75 seconds
Started Dec 27 01:32:28 PM PST 23
Finished Dec 27 01:34:16 PM PST 23
Peak memory 254356 kb
Host smart-70372eb6-31f0-4fcb-b97b-323a24a31369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060959434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1060959434
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2942691958
Short name T1488
Test name
Test status
Simulation time 16711476026 ps
CPU time 130.45 seconds
Started Dec 27 01:31:28 PM PST 23
Finished Dec 27 01:33:39 PM PST 23
Peak memory 242004 kb
Host smart-1bb5e594-7add-46dc-94f1-38d22031ff11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942691958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2942691958
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.65269763
Short name T1421
Test name
Test status
Simulation time 67188222769 ps
CPU time 145.55 seconds
Started Dec 27 01:32:34 PM PST 23
Finished Dec 27 01:35:03 PM PST 23
Peak memory 257576 kb
Host smart-977707c8-f261-4083-ac06-cf5fa8bb1be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65269763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.65269763
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.997219814
Short name T1374
Test name
Test status
Simulation time 1682365021 ps
CPU time 9.37 seconds
Started Dec 27 01:32:30 PM PST 23
Finished Dec 27 01:32:45 PM PST 23
Peak memory 230172 kb
Host smart-b06719f9-ea8f-43e6-8e2b-813612bc1f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997219814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.997219814
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1151373585
Short name T1171
Test name
Test status
Simulation time 9211031297 ps
CPU time 8.89 seconds
Started Dec 27 01:32:31 PM PST 23
Finished Dec 27 01:32:45 PM PST 23
Peak memory 219848 kb
Host smart-b9c5e56e-d5f1-468b-94f2-0abd051370c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151373585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1151373585
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_intr.4220037098
Short name T524
Test name
Test status
Simulation time 38771811636 ps
CPU time 20.42 seconds
Started Dec 27 01:32:04 PM PST 23
Finished Dec 27 01:32:26 PM PST 23
Peak memory 222444 kb
Host smart-c86ef819-1b8b-4297-8e91-6af4411f69ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220037098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intr.4220037098
Directory /workspace/10.spi_device_intr/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3891442165
Short name T748
Test name
Test status
Simulation time 48399265443 ps
CPU time 38.51 seconds
Started Dec 27 01:32:52 PM PST 23
Finished Dec 27 01:33:34 PM PST 23
Peak memory 249792 kb
Host smart-236fadf0-d741-4101-b58a-6fdf675305f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891442165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3891442165
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.243087126
Short name T1392
Test name
Test status
Simulation time 55984341 ps
CPU time 0.97 seconds
Started Dec 27 01:31:53 PM PST 23
Finished Dec 27 01:31:54 PM PST 23
Peak memory 217876 kb
Host smart-9f5f0115-263b-4d23-b1f9-d9083af4c90b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243087126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.243087126
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1263391697
Short name T1019
Test name
Test status
Simulation time 38392011189 ps
CPU time 12.86 seconds
Started Dec 27 01:32:33 PM PST 23
Finished Dec 27 01:32:50 PM PST 23
Peak memory 243588 kb
Host smart-7afcf5d2-b011-449d-8d5c-cbc4fc81ef86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263391697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1263391697
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2883973111
Short name T1372
Test name
Test status
Simulation time 2323363372 ps
CPU time 4.76 seconds
Started Dec 27 01:32:12 PM PST 23
Finished Dec 27 01:32:23 PM PST 23
Peak memory 225152 kb
Host smart-9c5c481e-e708-4027-a5ae-971985100536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883973111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2883973111
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_perf.4288699520
Short name T1104
Test name
Test status
Simulation time 74294415901 ps
CPU time 1005.82 seconds
Started Dec 27 01:31:41 PM PST 23
Finished Dec 27 01:48:27 PM PST 23
Peak memory 289168 kb
Host smart-24342dc2-41df-467a-a044-5086da71c511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288699520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_perf.4288699520
Directory /workspace/10.spi_device_perf/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.3257994934
Short name T875
Test name
Test status
Simulation time 23002204 ps
CPU time 0.72 seconds
Started Dec 27 01:32:13 PM PST 23
Finished Dec 27 01:32:22 PM PST 23
Peak memory 216740 kb
Host smart-cd47bf5b-ddb6-45d6-94a2-15b48054a371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257994934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.3257994934
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.668255166
Short name T192
Test name
Test status
Simulation time 1641772087 ps
CPU time 7.32 seconds
Started Dec 27 01:32:24 PM PST 23
Finished Dec 27 01:32:40 PM PST 23
Peak memory 221288 kb
Host smart-1e519017-7a33-49a6-b654-aede70cc45af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=668255166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.668255166
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_rx_async_fifo_reset.549221730
Short name T955
Test name
Test status
Simulation time 18244052 ps
CPU time 0.85 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:29 PM PST 23
Peak memory 208476 kb
Host smart-9b1374ae-853b-480c-9d68-a0955db949da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549221730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_rx_async_fifo_reset.549221730
Directory /workspace/10.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/10.spi_device_rx_timeout.2514332457
Short name T752
Test name
Test status
Simulation time 575106940 ps
CPU time 5.14 seconds
Started Dec 27 01:31:34 PM PST 23
Finished Dec 27 01:31:40 PM PST 23
Peak memory 216816 kb
Host smart-cc5d01ec-1b9f-4a5a-8099-a46399db7545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514332457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_rx_timeout.2514332457
Directory /workspace/10.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/10.spi_device_smoke.2481128088
Short name T759
Test name
Test status
Simulation time 46671137 ps
CPU time 1.29 seconds
Started Dec 27 01:31:48 PM PST 23
Finished Dec 27 01:31:50 PM PST 23
Peak memory 216748 kb
Host smart-e7350a56-ddd9-489a-99b5-28114ad854f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481128088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_smoke.2481128088
Directory /workspace/10.spi_device_smoke/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1430420339
Short name T953
Test name
Test status
Simulation time 3117195241 ps
CPU time 35.2 seconds
Started Dec 27 01:32:24 PM PST 23
Finished Dec 27 01:33:08 PM PST 23
Peak memory 216912 kb
Host smart-d05c6390-86ed-4371-b114-c726fd9254c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430420339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1430420339
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3666576818
Short name T1068
Test name
Test status
Simulation time 1795242103 ps
CPU time 10.67 seconds
Started Dec 27 01:32:26 PM PST 23
Finished Dec 27 01:32:44 PM PST 23
Peak memory 216816 kb
Host smart-8bedfe40-bcd6-4a56-b21b-e54e5dd9afab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666576818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3666576818
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2585219543
Short name T724
Test name
Test status
Simulation time 84460717 ps
CPU time 1.3 seconds
Started Dec 27 01:32:20 PM PST 23
Finished Dec 27 01:32:31 PM PST 23
Peak memory 216824 kb
Host smart-da765b32-e8ca-42c0-9b69-fa8112253cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585219543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2585219543
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1716611463
Short name T904
Test name
Test status
Simulation time 68098873 ps
CPU time 1.03 seconds
Started Dec 27 01:32:14 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 206860 kb
Host smart-e005a35c-d247-42aa-b510-48baff36f26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716611463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1716611463
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_tx_async_fifo_reset.3233347431
Short name T1122
Test name
Test status
Simulation time 46069288 ps
CPU time 0.76 seconds
Started Dec 27 01:32:32 PM PST 23
Finished Dec 27 01:32:38 PM PST 23
Peak memory 208488 kb
Host smart-26bad72f-277c-4273-837f-a2a84ab662ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233347431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tx_async_fifo_reset.3233347431
Directory /workspace/10.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/10.spi_device_txrx.3055996768
Short name T1646
Test name
Test status
Simulation time 42859283126 ps
CPU time 205.71 seconds
Started Dec 27 01:31:15 PM PST 23
Finished Dec 27 01:34:42 PM PST 23
Peak memory 257820 kb
Host smart-ecb664d7-165d-4218-9e5e-eecdda5ebcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055996768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_txrx.3055996768
Directory /workspace/10.spi_device_txrx/latest

Test location /workspace/coverage/default/10.spi_device_upload.1516799061
Short name T284
Test name
Test status
Simulation time 172090759 ps
CPU time 3.09 seconds
Started Dec 27 01:32:10 PM PST 23
Finished Dec 27 01:32:14 PM PST 23
Peak memory 218408 kb
Host smart-a42af9a4-594b-4cc0-ae30-aa19bdc25686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516799061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1516799061
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_abort.555444836
Short name T94
Test name
Test status
Simulation time 32542159 ps
CPU time 0.75 seconds
Started Dec 27 01:31:30 PM PST 23
Finished Dec 27 01:31:32 PM PST 23
Peak memory 206648 kb
Host smart-a1cfa59f-0b2b-40d2-a26d-594edb0b5b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555444836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_abort.555444836
Directory /workspace/11.spi_device_abort/latest

Test location /workspace/coverage/default/11.spi_device_bit_transfer.1111568989
Short name T1559
Test name
Test status
Simulation time 1088920411 ps
CPU time 2.64 seconds
Started Dec 27 01:31:44 PM PST 23
Finished Dec 27 01:31:47 PM PST 23
Peak memory 216788 kb
Host smart-72f0220c-4f2a-4aef-927d-4cf5d4222cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111568989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_bit_transfer.1111568989
Directory /workspace/11.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/11.spi_device_byte_transfer.3234715063
Short name T737
Test name
Test status
Simulation time 81852815 ps
CPU time 2.42 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:29 PM PST 23
Peak memory 216756 kb
Host smart-b3477a5b-07ba-4e70-93c8-64baa5911c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234715063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_byte_transfer.3234715063
Directory /workspace/11.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.177940345
Short name T1367
Test name
Test status
Simulation time 16323153374 ps
CPU time 6.86 seconds
Started Dec 27 01:31:04 PM PST 23
Finished Dec 27 01:31:12 PM PST 23
Peak memory 240256 kb
Host smart-6edbf469-2b66-4abc-828d-dd1f70aa5d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177940345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.177940345
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3500350545
Short name T863
Test name
Test status
Simulation time 19569762 ps
CPU time 0.79 seconds
Started Dec 27 01:32:09 PM PST 23
Finished Dec 27 01:32:11 PM PST 23
Peak memory 206604 kb
Host smart-590cff0f-e574-484a-b599-19453ccd5836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500350545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3500350545
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_dummy_item_extra_dly.1689540818
Short name T570
Test name
Test status
Simulation time 904811954028 ps
CPU time 422.95 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:39:26 PM PST 23
Peak memory 318312 kb
Host smart-7f4532db-f0fe-4f77-9dfe-0f40ed8c93ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689540818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_dummy_item_extra_dly.1689540818
Directory /workspace/11.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/11.spi_device_extreme_fifo_size.2919675899
Short name T650
Test name
Test status
Simulation time 297237430328 ps
CPU time 835.98 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:46:24 PM PST 23
Peak memory 225104 kb
Host smart-285a1a6e-2d75-4e25-95cc-78dadd38341f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919675899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_extreme_fifo_size.2919675899
Directory /workspace/11.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/11.spi_device_fifo_full.60523802
Short name T46
Test name
Test status
Simulation time 244853602682 ps
CPU time 2029.12 seconds
Started Dec 27 01:32:33 PM PST 23
Finished Dec 27 02:06:27 PM PST 23
Peak memory 270176 kb
Host smart-4f5742e9-6b76-482e-a45a-ff9fadc5e0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60523802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_fifo_full.60523802
Directory /workspace/11.spi_device_fifo_full/latest

Test location /workspace/coverage/default/11.spi_device_fifo_underflow_overflow.1702324343
Short name T1698
Test name
Test status
Simulation time 50758839802 ps
CPU time 421.59 seconds
Started Dec 27 01:32:37 PM PST 23
Finished Dec 27 01:39:41 PM PST 23
Peak memory 415092 kb
Host smart-8a21edd4-dbd2-49af-b31d-d4bb517a57ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702324343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_fifo_underflow_overf
low.1702324343
Directory /workspace/11.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3987032523
Short name T320
Test name
Test status
Simulation time 121684227871 ps
CPU time 140.94 seconds
Started Dec 27 01:31:14 PM PST 23
Finished Dec 27 01:33:36 PM PST 23
Peak memory 240280 kb
Host smart-4d46dfb6-1ede-4f38-a7bd-fb0abd25874d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987032523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3987032523
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3198134245
Short name T921
Test name
Test status
Simulation time 13099871891 ps
CPU time 109.59 seconds
Started Dec 27 01:31:25 PM PST 23
Finished Dec 27 01:33:16 PM PST 23
Peak memory 266164 kb
Host smart-cf79dcce-3a60-4090-a6a9-70669edeca79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198134245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3198134245
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3980996282
Short name T1605
Test name
Test status
Simulation time 213792709 ps
CPU time 7.2 seconds
Started Dec 27 01:31:12 PM PST 23
Finished Dec 27 01:31:20 PM PST 23
Peak memory 234068 kb
Host smart-2db17ca3-8208-439d-9f80-ef480fb51ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980996282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3980996282
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3469203127
Short name T739
Test name
Test status
Simulation time 2583441451 ps
CPU time 6.86 seconds
Started Dec 27 01:31:57 PM PST 23
Finished Dec 27 01:32:04 PM PST 23
Peak memory 220124 kb
Host smart-3ce29bf4-ba5e-4d1a-8cf9-02121c148fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469203127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3469203127
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_intr.1404000709
Short name T1577
Test name
Test status
Simulation time 7928728120 ps
CPU time 48.63 seconds
Started Dec 27 01:32:14 PM PST 23
Finished Dec 27 01:33:11 PM PST 23
Peak memory 241140 kb
Host smart-cadee0c4-7091-48c4-b8b1-8345d997e37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404000709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intr.1404000709
Directory /workspace/11.spi_device_intr/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2739553700
Short name T1387
Test name
Test status
Simulation time 3954735132 ps
CPU time 6.25 seconds
Started Dec 27 01:31:37 PM PST 23
Finished Dec 27 01:31:43 PM PST 23
Peak memory 248312 kb
Host smart-2d3aa075-1df0-4609-8be9-851ab289b07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739553700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2739553700
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3382553262
Short name T708
Test name
Test status
Simulation time 43295699 ps
CPU time 1.01 seconds
Started Dec 27 01:32:00 PM PST 23
Finished Dec 27 01:32:02 PM PST 23
Peak memory 218852 kb
Host smart-a8f4a628-534b-459f-8d98-791ff0b1e170
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382553262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3382553262
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3448622939
Short name T318
Test name
Test status
Simulation time 3544776743 ps
CPU time 5.17 seconds
Started Dec 27 01:31:27 PM PST 23
Finished Dec 27 01:31:32 PM PST 23
Peak memory 241008 kb
Host smart-e36c9f0f-ba3b-4b09-9e73-8ff414c3f03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448622939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3448622939
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.918981274
Short name T1142
Test name
Test status
Simulation time 1245510141 ps
CPU time 4.24 seconds
Started Dec 27 01:31:44 PM PST 23
Finished Dec 27 01:31:48 PM PST 23
Peak memory 218632 kb
Host smart-68b70dac-6ac6-4d02-9297-ffbd53ce5fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918981274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.918981274
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_perf.3653512906
Short name T676
Test name
Test status
Simulation time 28989718726 ps
CPU time 1792.2 seconds
Started Dec 27 01:32:14 PM PST 23
Finished Dec 27 02:02:15 PM PST 23
Peak memory 249760 kb
Host smart-a865861b-621f-47f5-9b70-a5f6f9eaab6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653512906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_perf.3653512906
Directory /workspace/11.spi_device_perf/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.3918461439
Short name T521
Test name
Test status
Simulation time 45493096 ps
CPU time 0.71 seconds
Started Dec 27 01:31:31 PM PST 23
Finished Dec 27 01:31:33 PM PST 23
Peak memory 216696 kb
Host smart-74f16e91-6306-4582-94c4-5a34c0770017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918461439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3918461439
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3932588052
Short name T582
Test name
Test status
Simulation time 1104263310 ps
CPU time 4.61 seconds
Started Dec 27 01:31:11 PM PST 23
Finished Dec 27 01:31:17 PM PST 23
Peak memory 234484 kb
Host smart-03b53557-bb99-47cd-9e10-1609a9f1e622
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3932588052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3932588052
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_rx_async_fifo_reset.2690352496
Short name T1611
Test name
Test status
Simulation time 21302744 ps
CPU time 0.87 seconds
Started Dec 27 01:31:30 PM PST 23
Finished Dec 27 01:31:32 PM PST 23
Peak memory 208464 kb
Host smart-2800e2a6-3b7a-4ab6-a60d-1f7c941b54ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690352496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_rx_async_fifo_reset.2690352496
Directory /workspace/11.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/11.spi_device_rx_timeout.1180946743
Short name T835
Test name
Test status
Simulation time 3968232030 ps
CPU time 5.1 seconds
Started Dec 27 01:31:52 PM PST 23
Finished Dec 27 01:31:58 PM PST 23
Peak memory 216948 kb
Host smart-258846c7-0991-4dd5-a54c-f472f01b82e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180946743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_rx_timeout.1180946743
Directory /workspace/11.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/11.spi_device_smoke.580192971
Short name T1175
Test name
Test status
Simulation time 120719797 ps
CPU time 1.04 seconds
Started Dec 27 01:32:18 PM PST 23
Finished Dec 27 01:32:25 PM PST 23
Peak memory 208344 kb
Host smart-b1971216-1de1-4abe-91ce-1a46860e8034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580192971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_smoke.580192971
Directory /workspace/11.spi_device_smoke/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1365209992
Short name T330
Test name
Test status
Simulation time 446437263997 ps
CPU time 1277.14 seconds
Started Dec 27 01:31:28 PM PST 23
Finished Dec 27 01:52:46 PM PST 23
Peak memory 347832 kb
Host smart-7d3623d4-d092-4067-b07d-07c9dbd6046e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365209992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1365209992
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2492129618
Short name T902
Test name
Test status
Simulation time 3191509001 ps
CPU time 40.08 seconds
Started Dec 27 01:31:43 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 216872 kb
Host smart-42e0d890-7ae7-474e-bc2b-2c6c3f68d0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492129618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2492129618
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2114497029
Short name T695
Test name
Test status
Simulation time 48126614 ps
CPU time 1.17 seconds
Started Dec 27 01:31:50 PM PST 23
Finished Dec 27 01:31:52 PM PST 23
Peak memory 208280 kb
Host smart-29d49e46-c937-4772-bdb3-29424e608901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114497029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2114497029
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2928893693
Short name T115
Test name
Test status
Simulation time 42089214 ps
CPU time 0.8 seconds
Started Dec 27 01:31:36 PM PST 23
Finished Dec 27 01:31:37 PM PST 23
Peak memory 206848 kb
Host smart-40531855-aaa7-4f95-9957-3ec7d47aed4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928893693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2928893693
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_tx_async_fifo_reset.1646423247
Short name T1406
Test name
Test status
Simulation time 71057036 ps
CPU time 0.76 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 208480 kb
Host smart-68de4aa5-9aae-461f-96b7-1a6f539332a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646423247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tx_async_fifo_reset.1646423247
Directory /workspace/11.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/11.spi_device_upload.62716710
Short name T1602
Test name
Test status
Simulation time 941251492 ps
CPU time 9.01 seconds
Started Dec 27 01:32:18 PM PST 23
Finished Dec 27 01:32:32 PM PST 23
Peak memory 247692 kb
Host smart-f0a1c493-70f2-4666-b7d1-a4d63ba0546c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62716710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.62716710
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_abort.2727119647
Short name T1539
Test name
Test status
Simulation time 23621312 ps
CPU time 0.74 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:28 PM PST 23
Peak memory 206616 kb
Host smart-584f27b0-c8e9-4787-869e-84f70e906043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727119647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_abort.2727119647
Directory /workspace/12.spi_device_abort/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.758880128
Short name T105
Test name
Test status
Simulation time 34774384 ps
CPU time 0.71 seconds
Started Dec 27 01:32:40 PM PST 23
Finished Dec 27 01:32:43 PM PST 23
Peak memory 206472 kb
Host smart-c959b24b-be7c-4d97-8c5e-663786b5424f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758880128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.758880128
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_bit_transfer.940895069
Short name T1556
Test name
Test status
Simulation time 641296510 ps
CPU time 2.86 seconds
Started Dec 27 01:32:48 PM PST 23
Finished Dec 27 01:32:56 PM PST 23
Peak memory 216888 kb
Host smart-a0c33fc8-4568-4988-939a-db6c0f1cd705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940895069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_bit_transfer.940895069
Directory /workspace/12.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/12.spi_device_byte_transfer.1570261280
Short name T1607
Test name
Test status
Simulation time 143002883 ps
CPU time 2.75 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:32:26 PM PST 23
Peak memory 216872 kb
Host smart-c0c3b20a-2c39-499c-a12a-54b8f1b698a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570261280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_byte_transfer.1570261280
Directory /workspace/12.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2035334686
Short name T1014
Test name
Test status
Simulation time 3626382921 ps
CPU time 13.25 seconds
Started Dec 27 01:32:30 PM PST 23
Finished Dec 27 01:32:49 PM PST 23
Peak memory 240284 kb
Host smart-a2293366-53d6-4554-b0c1-56607c0cfcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035334686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2035334686
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.466704248
Short name T1368
Test name
Test status
Simulation time 18740320 ps
CPU time 0.81 seconds
Started Dec 27 01:32:27 PM PST 23
Finished Dec 27 01:32:37 PM PST 23
Peak memory 207548 kb
Host smart-420b4e4e-0f07-4d4c-9579-f07201fb6721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466704248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.466704248
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_dummy_item_extra_dly.2126118155
Short name T563
Test name
Test status
Simulation time 239532878199 ps
CPU time 855.92 seconds
Started Dec 27 01:32:25 PM PST 23
Finished Dec 27 01:46:49 PM PST 23
Peak memory 303556 kb
Host smart-0b10beda-b32e-4cef-9df7-fbfd6eac2ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126118155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_dummy_item_extra_dly.2126118155
Directory /workspace/12.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/12.spi_device_extreme_fifo_size.1849822779
Short name T720
Test name
Test status
Simulation time 38147692654 ps
CPU time 1833.67 seconds
Started Dec 27 01:32:01 PM PST 23
Finished Dec 27 02:02:36 PM PST 23
Peak memory 216872 kb
Host smart-293a724f-84bf-425e-b6ac-421a84769f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849822779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_extreme_fifo_size.1849822779
Directory /workspace/12.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/12.spi_device_fifo_full.133348611
Short name T1296
Test name
Test status
Simulation time 64693343413 ps
CPU time 959.56 seconds
Started Dec 27 01:32:14 PM PST 23
Finished Dec 27 01:48:22 PM PST 23
Peak memory 262592 kb
Host smart-bf1335f2-0d96-4ec8-9a9d-7dcdf38cf0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133348611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_fifo_full.133348611
Directory /workspace/12.spi_device_fifo_full/latest

Test location /workspace/coverage/default/12.spi_device_fifo_underflow_overflow.2255438660
Short name T67
Test name
Test status
Simulation time 13343428743 ps
CPU time 149.73 seconds
Started Dec 27 01:32:23 PM PST 23
Finished Dec 27 01:35:02 PM PST 23
Peak memory 319696 kb
Host smart-d503cb67-455e-47cd-ac48-c3338465c26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255438660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_fifo_underflow_overf
low.2255438660
Directory /workspace/12.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.4171129776
Short name T1747
Test name
Test status
Simulation time 20126207026 ps
CPU time 30.05 seconds
Started Dec 27 01:32:24 PM PST 23
Finished Dec 27 01:33:03 PM PST 23
Peak memory 239820 kb
Host smart-be64e799-bb20-4bfb-b1a1-f3de2d6b4739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171129776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.4171129776
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.174035556
Short name T1365
Test name
Test status
Simulation time 14818546345 ps
CPU time 57.42 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:33:25 PM PST 23
Peak memory 249868 kb
Host smart-8cfe5fcb-05e4-4c34-9f0f-d32ec8475b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174035556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.174035556
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2002691772
Short name T347
Test name
Test status
Simulation time 20719218358 ps
CPU time 24.48 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:52 PM PST 23
Peak memory 250428 kb
Host smart-dfc4029c-2c92-43b0-80ab-3a006b043ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002691772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2002691772
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1074418418
Short name T236
Test name
Test status
Simulation time 5272439042 ps
CPU time 6.89 seconds
Started Dec 27 01:32:28 PM PST 23
Finished Dec 27 01:32:41 PM PST 23
Peak memory 225140 kb
Host smart-62cf5fe8-95c2-462b-a4b9-b3525506f98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074418418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1074418418
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_intr.3833663907
Short name T508
Test name
Test status
Simulation time 6643058294 ps
CPU time 41.87 seconds
Started Dec 27 01:32:20 PM PST 23
Finished Dec 27 01:33:11 PM PST 23
Peak memory 231384 kb
Host smart-48823b20-5f89-4844-92a8-f03c5d36c76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833663907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intr.3833663907
Directory /workspace/12.spi_device_intr/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1040797409
Short name T33
Test name
Test status
Simulation time 3980664185 ps
CPU time 6.83 seconds
Started Dec 27 01:32:11 PM PST 23
Finished Dec 27 01:32:20 PM PST 23
Peak memory 233260 kb
Host smart-b3a504e2-349b-4a1b-93c7-242e577429c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040797409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1040797409
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.4101609903
Short name T58
Test name
Test status
Simulation time 47607634 ps
CPU time 0.98 seconds
Started Dec 27 01:32:15 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 218872 kb
Host smart-a8013835-ef48-4485-9230-7c20ef644d8d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101609903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.4101609903
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1059015984
Short name T1436
Test name
Test status
Simulation time 673088606 ps
CPU time 4.04 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:32 PM PST 23
Peak memory 218824 kb
Host smart-ef46bc82-b34a-4b23-9ea8-46ee8845490a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059015984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1059015984
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2126365291
Short name T25
Test name
Test status
Simulation time 2640420351 ps
CPU time 11.35 seconds
Started Dec 27 01:32:27 PM PST 23
Finished Dec 27 01:32:45 PM PST 23
Peak memory 238672 kb
Host smart-e4fd1043-6035-40d8-ab31-6eba4a5b540e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126365291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2126365291
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_perf.3665670630
Short name T1313
Test name
Test status
Simulation time 111648658816 ps
CPU time 1709.45 seconds
Started Dec 27 01:32:18 PM PST 23
Finished Dec 27 02:00:53 PM PST 23
Peak memory 262408 kb
Host smart-909428e0-2736-4d99-8684-4c37e545bcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665670630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_perf.3665670630
Directory /workspace/12.spi_device_perf/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4180425503
Short name T1647
Test name
Test status
Simulation time 2051577360 ps
CPU time 6.26 seconds
Started Dec 27 01:32:14 PM PST 23
Finished Dec 27 01:32:29 PM PST 23
Peak memory 236260 kb
Host smart-7af4e4c0-d69b-4418-8e3b-5961c5017933
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4180425503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4180425503
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_rx_async_fifo_reset.2196920842
Short name T1046
Test name
Test status
Simulation time 76449668 ps
CPU time 0.88 seconds
Started Dec 27 01:32:43 PM PST 23
Finished Dec 27 01:32:45 PM PST 23
Peak memory 208532 kb
Host smart-afc41eeb-3a24-46af-ba01-7c873a1ed81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196920842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_rx_async_fifo_reset.2196920842
Directory /workspace/12.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/12.spi_device_rx_timeout.2459570342
Short name T900
Test name
Test status
Simulation time 382895604 ps
CPU time 4.8 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:32 PM PST 23
Peak memory 216880 kb
Host smart-e111ae3d-2027-4cc8-abeb-3e853bd37e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459570342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_rx_timeout.2459570342
Directory /workspace/12.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/12.spi_device_smoke.1888019680
Short name T1609
Test name
Test status
Simulation time 618914216 ps
CPU time 1.18 seconds
Started Dec 27 01:31:41 PM PST 23
Finished Dec 27 01:31:43 PM PST 23
Peak memory 216804 kb
Host smart-f0418d07-8d35-4ea9-8f38-8f07479d4b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888019680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_smoke.1888019680
Directory /workspace/12.spi_device_smoke/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1671191524
Short name T271
Test name
Test status
Simulation time 212370706360 ps
CPU time 3024.75 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 02:22:53 PM PST 23
Peak memory 299012 kb
Host smart-24caaefa-266c-4114-8999-776cddbd3134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671191524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1671191524
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3001692769
Short name T1689
Test name
Test status
Simulation time 2425282885 ps
CPU time 8.29 seconds
Started Dec 27 01:32:27 PM PST 23
Finished Dec 27 01:32:42 PM PST 23
Peak memory 216852 kb
Host smart-a62682fe-5284-41ec-946b-285e8d527ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001692769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3001692769
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.363845653
Short name T123
Test name
Test status
Simulation time 72169189 ps
CPU time 1.55 seconds
Started Dec 27 01:32:37 PM PST 23
Finished Dec 27 01:32:40 PM PST 23
Peak memory 216808 kb
Host smart-6d171daf-12ef-435b-8825-b25c5b380d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363845653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.363845653
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2484353685
Short name T1297
Test name
Test status
Simulation time 159600188 ps
CPU time 1.07 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:29 PM PST 23
Peak memory 207992 kb
Host smart-0f0b0df6-be40-46a0-9b35-1f6839290ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484353685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2484353685
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_tx_async_fifo_reset.1771059916
Short name T1528
Test name
Test status
Simulation time 27767002 ps
CPU time 0.8 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 208332 kb
Host smart-656a5468-fd51-4261-9741-28ddc38645a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771059916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tx_async_fifo_reset.1771059916
Directory /workspace/12.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/12.spi_device_txrx.106260630
Short name T1211
Test name
Test status
Simulation time 16922047101 ps
CPU time 103.43 seconds
Started Dec 27 01:32:10 PM PST 23
Finished Dec 27 01:33:55 PM PST 23
Peak memory 264036 kb
Host smart-39955206-e143-4a9e-956d-db810ee5c7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106260630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_txrx.106260630
Directory /workspace/12.spi_device_txrx/latest

Test location /workspace/coverage/default/12.spi_device_upload.600825910
Short name T259
Test name
Test status
Simulation time 44690840306 ps
CPU time 25.49 seconds
Started Dec 27 01:32:18 PM PST 23
Finished Dec 27 01:32:49 PM PST 23
Peak memory 224948 kb
Host smart-934e958b-fec5-40b3-9fd7-efa2545920d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600825910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.600825910
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.259777110
Short name T873
Test name
Test status
Simulation time 38187200 ps
CPU time 0.74 seconds
Started Dec 27 01:32:40 PM PST 23
Finished Dec 27 01:32:42 PM PST 23
Peak memory 206464 kb
Host smart-00fa5433-fb35-4183-b811-746963c5ca11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259777110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.259777110
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_bit_transfer.2864666888
Short name T1192
Test name
Test status
Simulation time 304563945 ps
CPU time 2.25 seconds
Started Dec 27 01:32:02 PM PST 23
Finished Dec 27 01:32:05 PM PST 23
Peak memory 216892 kb
Host smart-681c67a3-bbce-46a5-9c44-773d59f81629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864666888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_bit_transfer.2864666888
Directory /workspace/13.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/13.spi_device_byte_transfer.2901904041
Short name T1500
Test name
Test status
Simulation time 770259062 ps
CPU time 2.46 seconds
Started Dec 27 01:32:18 PM PST 23
Finished Dec 27 01:32:26 PM PST 23
Peak memory 216656 kb
Host smart-e7a0c5bb-cc64-4569-8d32-f97f486b90d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901904041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_byte_transfer.2901904041
Directory /workspace/13.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2421871083
Short name T1262
Test name
Test status
Simulation time 739731395 ps
CPU time 4.12 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:32:28 PM PST 23
Peak memory 225084 kb
Host smart-41bda73c-b2b5-4217-9e1b-d6e76dc348a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421871083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2421871083
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3636042473
Short name T553
Test name
Test status
Simulation time 44001005 ps
CPU time 0.81 seconds
Started Dec 27 01:32:21 PM PST 23
Finished Dec 27 01:32:31 PM PST 23
Peak memory 207552 kb
Host smart-6536505e-d062-4f16-88bc-1c7e059f2bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636042473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3636042473
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_dummy_item_extra_dly.2788743862
Short name T814
Test name
Test status
Simulation time 77911936775 ps
CPU time 616.34 seconds
Started Dec 27 01:32:30 PM PST 23
Finished Dec 27 01:42:52 PM PST 23
Peak memory 273460 kb
Host smart-d6f797e9-4b9d-4b31-bea6-2a39d2b1f830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788743862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_dummy_item_extra_dly.2788743862
Directory /workspace/13.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/13.spi_device_extreme_fifo_size.3247454764
Short name T5
Test name
Test status
Simulation time 1653201187 ps
CPU time 30.78 seconds
Started Dec 27 01:32:28 PM PST 23
Finished Dec 27 01:33:05 PM PST 23
Peak memory 223896 kb
Host smart-6d7e4725-10bc-4357-9614-d01bf43d054c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247454764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_extreme_fifo_size.3247454764
Directory /workspace/13.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/13.spi_device_fifo_full.491346314
Short name T787
Test name
Test status
Simulation time 107951502572 ps
CPU time 170.86 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:35:14 PM PST 23
Peak memory 281576 kb
Host smart-9d78d059-3e35-402e-819d-f5480e1666cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491346314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_fifo_full.491346314
Directory /workspace/13.spi_device_fifo_full/latest

Test location /workspace/coverage/default/13.spi_device_fifo_underflow_overflow.4264979067
Short name T1168
Test name
Test status
Simulation time 88094303223 ps
CPU time 329.71 seconds
Started Dec 27 01:32:18 PM PST 23
Finished Dec 27 01:37:53 PM PST 23
Peak memory 477792 kb
Host smart-ea56c1d6-2acb-49c3-9cf0-9e75b7a806e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264979067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_fifo_underflow_overf
low.4264979067
Directory /workspace/13.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3084384173
Short name T630
Test name
Test status
Simulation time 29832551805 ps
CPU time 69.71 seconds
Started Dec 27 01:32:24 PM PST 23
Finished Dec 27 01:33:42 PM PST 23
Peak memory 253716 kb
Host smart-8961b30c-a499-4ea3-a7ef-d8683a72fe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084384173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3084384173
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3179113193
Short name T864
Test name
Test status
Simulation time 15322485179 ps
CPU time 119.28 seconds
Started Dec 27 01:32:24 PM PST 23
Finished Dec 27 01:34:32 PM PST 23
Peak memory 249760 kb
Host smart-800f3ca4-e0e4-419b-96b1-6b49e9eca482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179113193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3179113193
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1582854937
Short name T1642
Test name
Test status
Simulation time 7882699718 ps
CPU time 57.68 seconds
Started Dec 27 01:32:13 PM PST 23
Finished Dec 27 01:33:19 PM PST 23
Peak memory 249820 kb
Host smart-b630a862-2e2f-418a-9fb0-433634713cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582854937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1582854937
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3849087770
Short name T1256
Test name
Test status
Simulation time 20707381471 ps
CPU time 32.88 seconds
Started Dec 27 01:32:27 PM PST 23
Finished Dec 27 01:33:06 PM PST 23
Peak memory 238988 kb
Host smart-7cda8a1b-13b7-49cb-a956-c4200a088b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849087770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3849087770
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2564609560
Short name T887
Test name
Test status
Simulation time 3652110221 ps
CPU time 7.58 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:34 PM PST 23
Peak memory 221544 kb
Host smart-611c96f3-d851-467a-8b29-539bc549b24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564609560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2564609560
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_intr.3536665083
Short name T1227
Test name
Test status
Simulation time 6198811003 ps
CPU time 21.86 seconds
Started Dec 27 01:32:25 PM PST 23
Finished Dec 27 01:32:55 PM PST 23
Peak memory 218204 kb
Host smart-eca493ea-1799-4b3f-9492-ba2e926f0c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536665083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intr.3536665083
Directory /workspace/13.spi_device_intr/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.515783379
Short name T556
Test name
Test status
Simulation time 273172944 ps
CPU time 4.77 seconds
Started Dec 27 01:31:42 PM PST 23
Finished Dec 27 01:31:47 PM PST 23
Peak memory 220948 kb
Host smart-9c805acb-ec85-4d1a-bb60-d2cbd7239360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515783379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.515783379
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2116084506
Short name T1657
Test name
Test status
Simulation time 15012012 ps
CPU time 0.99 seconds
Started Dec 27 01:32:26 PM PST 23
Finished Dec 27 01:32:34 PM PST 23
Peak memory 218844 kb
Host smart-4084ae04-977a-4857-87ee-110a4417ae18
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116084506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2116084506
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2498665965
Short name T335
Test name
Test status
Simulation time 34204756348 ps
CPU time 12.19 seconds
Started Dec 27 01:31:38 PM PST 23
Finished Dec 27 01:31:51 PM PST 23
Peak memory 219500 kb
Host smart-5e0615f6-ad73-46f5-bb8c-e271e202a24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498665965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2498665965
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3042062401
Short name T32
Test name
Test status
Simulation time 4857686092 ps
CPU time 9.57 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:37 PM PST 23
Peak memory 231556 kb
Host smart-8020e602-d038-41e4-99ed-4d570ca33044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042062401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3042062401
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_perf.2889291044
Short name T914
Test name
Test status
Simulation time 172492827067 ps
CPU time 872.94 seconds
Started Dec 27 01:32:23 PM PST 23
Finished Dec 27 01:47:05 PM PST 23
Peak memory 289848 kb
Host smart-768f35d1-23a9-49ee-ad28-3be2c9ae2112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889291044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_perf.2889291044
Directory /workspace/13.spi_device_perf/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.1756656152
Short name T1429
Test name
Test status
Simulation time 22074628 ps
CPU time 0.72 seconds
Started Dec 27 01:32:28 PM PST 23
Finished Dec 27 01:32:35 PM PST 23
Peak memory 216656 kb
Host smart-41407040-b3a9-4088-b3fc-bb7f5c9a674b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756656152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.1756656152
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1336586687
Short name T1237
Test name
Test status
Simulation time 2921604026 ps
CPU time 3.99 seconds
Started Dec 27 01:32:12 PM PST 23
Finished Dec 27 01:32:18 PM PST 23
Peak memory 234228 kb
Host smart-c75f3f5b-87cd-4412-a3f5-602ccd2488b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1336586687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1336586687
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_rx_timeout.3423488832
Short name T548
Test name
Test status
Simulation time 5815425121 ps
CPU time 5.12 seconds
Started Dec 27 01:32:35 PM PST 23
Finished Dec 27 01:32:43 PM PST 23
Peak memory 216892 kb
Host smart-ef611169-7bb6-488f-88a6-a049b2c9b647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423488832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_rx_timeout.3423488832
Directory /workspace/13.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/13.spi_device_smoke.1386456551
Short name T1555
Test name
Test status
Simulation time 40469015 ps
CPU time 1.12 seconds
Started Dec 27 01:32:20 PM PST 23
Finished Dec 27 01:32:31 PM PST 23
Peak memory 216784 kb
Host smart-60803a59-588a-472e-a7b7-03c03859ca07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386456551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_smoke.1386456551
Directory /workspace/13.spi_device_smoke/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.488456307
Short name T1294
Test name
Test status
Simulation time 225940189600 ps
CPU time 505.34 seconds
Started Dec 27 01:32:46 PM PST 23
Finished Dec 27 01:41:13 PM PST 23
Peak memory 331840 kb
Host smart-4dea5be5-96c2-4008-941d-902e67390a59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488456307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.488456307
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.4192579269
Short name T664
Test name
Test status
Simulation time 9906891216 ps
CPU time 41.94 seconds
Started Dec 27 01:32:15 PM PST 23
Finished Dec 27 01:33:05 PM PST 23
Peak memory 220820 kb
Host smart-4f5603d7-57b3-4a86-a133-e1e62d06c247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192579269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.4192579269
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2633084838
Short name T1071
Test name
Test status
Simulation time 10683557844 ps
CPU time 20.75 seconds
Started Dec 27 01:32:51 PM PST 23
Finished Dec 27 01:33:14 PM PST 23
Peak memory 216876 kb
Host smart-e4c54b04-056a-49ce-afcc-2615354e21bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633084838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2633084838
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.242183701
Short name T1099
Test name
Test status
Simulation time 120358536 ps
CPU time 1.07 seconds
Started Dec 27 01:31:34 PM PST 23
Finished Dec 27 01:31:36 PM PST 23
Peak memory 207872 kb
Host smart-88ccf6b2-277b-488a-9212-a1e35cdf02fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242183701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.242183701
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.4009762918
Short name T679
Test name
Test status
Simulation time 115648005 ps
CPU time 0.95 seconds
Started Dec 27 01:32:29 PM PST 23
Finished Dec 27 01:32:36 PM PST 23
Peak memory 208068 kb
Host smart-450361a5-dcf9-4719-9725-855443b0d567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009762918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.4009762918
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_txrx.535365952
Short name T1636
Test name
Test status
Simulation time 20158425858 ps
CPU time 77.92 seconds
Started Dec 27 01:32:34 PM PST 23
Finished Dec 27 01:33:55 PM PST 23
Peak memory 231732 kb
Host smart-897b092f-20a7-4442-9373-311db9256470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535365952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_txrx.535365952
Directory /workspace/13.spi_device_txrx/latest

Test location /workspace/coverage/default/13.spi_device_upload.793904399
Short name T287
Test name
Test status
Simulation time 1488316991 ps
CPU time 11.7 seconds
Started Dec 27 01:31:49 PM PST 23
Finished Dec 27 01:32:02 PM PST 23
Peak memory 233232 kb
Host smart-7dffe82a-f0aa-41ba-b79b-5dc82d070fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793904399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.793904399
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_abort.2952485858
Short name T1064
Test name
Test status
Simulation time 17769891 ps
CPU time 0.74 seconds
Started Dec 27 01:32:07 PM PST 23
Finished Dec 27 01:32:08 PM PST 23
Peak memory 206584 kb
Host smart-8f91b0c6-ba8e-4adb-94a0-4f6ff38a2001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952485858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_abort.2952485858
Directory /workspace/14.spi_device_abort/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.4241556137
Short name T484
Test name
Test status
Simulation time 63240883 ps
CPU time 0.71 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:28 PM PST 23
Peak memory 206484 kb
Host smart-e4729ff0-5677-4e35-9ff9-07901f8c6bc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241556137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
4241556137
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_bit_transfer.2589109270
Short name T1514
Test name
Test status
Simulation time 736764624 ps
CPU time 2.58 seconds
Started Dec 27 01:31:34 PM PST 23
Finished Dec 27 01:31:37 PM PST 23
Peak memory 216748 kb
Host smart-e395dffd-1edc-44f0-802a-d2927c9805d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589109270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_bit_transfer.2589109270
Directory /workspace/14.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/14.spi_device_byte_transfer.2411032600
Short name T1335
Test name
Test status
Simulation time 1205402423 ps
CPU time 3.09 seconds
Started Dec 27 01:31:33 PM PST 23
Finished Dec 27 01:31:37 PM PST 23
Peak memory 216764 kb
Host smart-04226775-eefa-4bc3-8c96-a00b2d59b34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411032600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_byte_transfer.2411032600
Directory /workspace/14.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3656749554
Short name T1473
Test name
Test status
Simulation time 818260821 ps
CPU time 3.33 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:32:27 PM PST 23
Peak memory 219496 kb
Host smart-5d1cdd5f-ff0d-4f64-bbc0-7c2109ca3fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656749554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3656749554
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3719096781
Short name T1073
Test name
Test status
Simulation time 41306930 ps
CPU time 0.79 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 207536 kb
Host smart-df32f3ef-3345-4e50-92b3-a9944b760680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719096781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3719096781
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_dummy_item_extra_dly.354802952
Short name T282
Test name
Test status
Simulation time 51694425398 ps
CPU time 516.99 seconds
Started Dec 27 01:31:27 PM PST 23
Finished Dec 27 01:40:04 PM PST 23
Peak memory 233388 kb
Host smart-d471e3c3-0ed3-439a-9443-05abd029c082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354802952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_dummy_item_extra_dly.354802952
Directory /workspace/14.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/14.spi_device_extreme_fifo_size.4010193161
Short name T1726
Test name
Test status
Simulation time 3136634255 ps
CPU time 69.04 seconds
Started Dec 27 01:31:29 PM PST 23
Finished Dec 27 01:32:39 PM PST 23
Peak memory 220448 kb
Host smart-acccf829-894e-44c5-850f-0177f08a4bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010193161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_extreme_fifo_size.4010193161
Directory /workspace/14.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/14.spi_device_fifo_full.414880888
Short name T510
Test name
Test status
Simulation time 62050178396 ps
CPU time 302.01 seconds
Started Dec 27 01:32:27 PM PST 23
Finished Dec 27 01:37:35 PM PST 23
Peak memory 263632 kb
Host smart-61a469c8-46d7-40e1-88b2-8f7fb6824243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414880888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_fifo_full.414880888
Directory /workspace/14.spi_device_fifo_full/latest

Test location /workspace/coverage/default/14.spi_device_fifo_underflow_overflow.3738753168
Short name T815
Test name
Test status
Simulation time 81170327920 ps
CPU time 332.35 seconds
Started Dec 27 01:31:23 PM PST 23
Finished Dec 27 01:36:56 PM PST 23
Peak memory 333148 kb
Host smart-62bc7b54-3aeb-4492-b86e-ecc4f83b1f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738753168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_fifo_underflow_overf
low.3738753168
Directory /workspace/14.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3273341
Short name T719
Test name
Test status
Simulation time 21227166700 ps
CPU time 34.3 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:32:58 PM PST 23
Peak memory 239084 kb
Host smart-3d25906a-a285-4f74-b07e-24f01500d30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3273341
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3108803634
Short name T1244
Test name
Test status
Simulation time 2233861597 ps
CPU time 8.97 seconds
Started Dec 27 01:31:38 PM PST 23
Finished Dec 27 01:31:48 PM PST 23
Peak memory 220696 kb
Host smart-e306e39b-421b-4872-9ad5-4e1d7d81cd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108803634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3108803634
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_intr.1895256807
Short name T1724
Test name
Test status
Simulation time 6145164329 ps
CPU time 33.04 seconds
Started Dec 27 01:32:31 PM PST 23
Finished Dec 27 01:33:09 PM PST 23
Peak memory 223780 kb
Host smart-a21e5cfd-60c1-401d-bcbb-4343a624af8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895256807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intr.1895256807
Directory /workspace/14.spi_device_intr/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3021826841
Short name T1364
Test name
Test status
Simulation time 939707054 ps
CPU time 3.67 seconds
Started Dec 27 01:32:13 PM PST 23
Finished Dec 27 01:32:25 PM PST 23
Peak memory 234636 kb
Host smart-748425bc-d777-49c7-90dc-465e34c556fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021826841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3021826841
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.4064157247
Short name T1000
Test name
Test status
Simulation time 48287630 ps
CPU time 1.07 seconds
Started Dec 27 01:31:27 PM PST 23
Finished Dec 27 01:31:29 PM PST 23
Peak memory 218792 kb
Host smart-b2ab5725-0943-405a-afd6-2ebd38c649f5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064157247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.4064157247
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4000848306
Short name T1552
Test name
Test status
Simulation time 590735540 ps
CPU time 3.01 seconds
Started Dec 27 01:31:56 PM PST 23
Finished Dec 27 01:32:00 PM PST 23
Peak memory 218212 kb
Host smart-824a58fd-1f87-4769-8eb8-bef361354823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000848306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.4000848306
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2408878466
Short name T958
Test name
Test status
Simulation time 2222758867 ps
CPU time 4.83 seconds
Started Dec 27 01:31:37 PM PST 23
Finished Dec 27 01:31:42 PM PST 23
Peak memory 238412 kb
Host smart-4d8b1e5d-2652-45a3-9bd3-02bd829211d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408878466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2408878466
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_perf.840904357
Short name T880
Test name
Test status
Simulation time 14393682185 ps
CPU time 369.71 seconds
Started Dec 27 01:31:26 PM PST 23
Finished Dec 27 01:37:36 PM PST 23
Peak memory 269276 kb
Host smart-881ebabd-dce5-47bb-bb92-cad2e7b3fc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840904357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_perf.840904357
Directory /workspace/14.spi_device_perf/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.2308849146
Short name T923
Test name
Test status
Simulation time 17662852 ps
CPU time 0.73 seconds
Started Dec 27 01:32:06 PM PST 23
Finished Dec 27 01:32:08 PM PST 23
Peak memory 216672 kb
Host smart-668540ef-8c78-434e-924c-dc7c4114c580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308849146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.2308849146
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3715432311
Short name T551
Test name
Test status
Simulation time 842958941 ps
CPU time 3.7 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:32:27 PM PST 23
Peak memory 220280 kb
Host smart-9a9fc198-0b5d-475d-9c1f-d1d145639208
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3715432311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3715432311
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_rx_async_fifo_reset.2276285216
Short name T1236
Test name
Test status
Simulation time 118784706 ps
CPU time 0.92 seconds
Started Dec 27 01:31:43 PM PST 23
Finished Dec 27 01:31:45 PM PST 23
Peak memory 208464 kb
Host smart-891199ed-30ea-4654-9a68-936635a86075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276285216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_rx_async_fifo_reset.2276285216
Directory /workspace/14.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/14.spi_device_rx_timeout.1886700996
Short name T1467
Test name
Test status
Simulation time 610413784 ps
CPU time 5.86 seconds
Started Dec 27 01:31:49 PM PST 23
Finished Dec 27 01:31:56 PM PST 23
Peak memory 216852 kb
Host smart-51bbc950-bcc5-41d2-ada2-f1ecd99be8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886700996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_rx_timeout.1886700996
Directory /workspace/14.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/14.spi_device_smoke.2262724740
Short name T653
Test name
Test status
Simulation time 72023460 ps
CPU time 1.25 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:32:25 PM PST 23
Peak memory 216616 kb
Host smart-177f6d7d-62ee-4193-bc2f-6651949592e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262724740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_smoke.2262724740
Directory /workspace/14.spi_device_smoke/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1323580836
Short name T688
Test name
Test status
Simulation time 1314034497 ps
CPU time 23.14 seconds
Started Dec 27 01:31:29 PM PST 23
Finished Dec 27 01:31:53 PM PST 23
Peak memory 216784 kb
Host smart-74ed4514-8624-4670-8a71-694ce4637c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323580836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1323580836
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2266200634
Short name T794
Test name
Test status
Simulation time 292910337 ps
CPU time 1.38 seconds
Started Dec 27 01:32:07 PM PST 23
Finished Dec 27 01:32:08 PM PST 23
Peak memory 207896 kb
Host smart-eabbbad1-e92b-43c8-80cb-774925619a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266200634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2266200634
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1137947365
Short name T690
Test name
Test status
Simulation time 95649803 ps
CPU time 2 seconds
Started Dec 27 01:31:32 PM PST 23
Finished Dec 27 01:31:35 PM PST 23
Peak memory 216852 kb
Host smart-4ec2a5c6-b46a-4957-b488-1c6251e8c1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137947365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1137947365
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.242671656
Short name T1382
Test name
Test status
Simulation time 116623556 ps
CPU time 1.05 seconds
Started Dec 27 01:31:39 PM PST 23
Finished Dec 27 01:31:41 PM PST 23
Peak memory 208036 kb
Host smart-e46839f6-3133-4ae6-ba2f-66df3f691734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242671656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.242671656
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_tx_async_fifo_reset.3828506021
Short name T648
Test name
Test status
Simulation time 48248434 ps
CPU time 0.76 seconds
Started Dec 27 01:31:50 PM PST 23
Finished Dec 27 01:31:52 PM PST 23
Peak memory 208444 kb
Host smart-93e8beec-0f1e-492c-a8b3-bbf2e6ea4590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828506021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tx_async_fifo_reset.3828506021
Directory /workspace/14.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/14.spi_device_txrx.938291706
Short name T224
Test name
Test status
Simulation time 62420798823 ps
CPU time 525.93 seconds
Started Dec 27 01:32:40 PM PST 23
Finished Dec 27 01:41:28 PM PST 23
Peak memory 267164 kb
Host smart-1075dc72-f4e7-421c-89ec-e85a4674964d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938291706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_txrx.938291706
Directory /workspace/14.spi_device_txrx/latest

Test location /workspace/coverage/default/14.spi_device_upload.595155356
Short name T1189
Test name
Test status
Simulation time 2858331618 ps
CPU time 8.02 seconds
Started Dec 27 01:31:50 PM PST 23
Finished Dec 27 01:31:59 PM PST 23
Peak memory 220204 kb
Host smart-b66e1638-d99a-413e-ac6d-c6cbc2c94b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595155356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.595155356
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_abort.1515057949
Short name T1147
Test name
Test status
Simulation time 47929205 ps
CPU time 0.75 seconds
Started Dec 27 01:31:25 PM PST 23
Finished Dec 27 01:31:27 PM PST 23
Peak memory 206516 kb
Host smart-7112c691-48e3-4aca-9ba5-26f739a48fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515057949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_abort.1515057949
Directory /workspace/15.spi_device_abort/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.4170368634
Short name T706
Test name
Test status
Simulation time 42169703 ps
CPU time 0.73 seconds
Started Dec 27 01:31:42 PM PST 23
Finished Dec 27 01:31:43 PM PST 23
Peak memory 206492 kb
Host smart-8c8ac9f7-bc1b-469b-b39b-1e40bb264855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170368634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
4170368634
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_bit_transfer.3165361704
Short name T878
Test name
Test status
Simulation time 1979677703 ps
CPU time 2.35 seconds
Started Dec 27 01:31:53 PM PST 23
Finished Dec 27 01:31:56 PM PST 23
Peak memory 216816 kb
Host smart-d34e9b28-9ff5-4483-85bf-259dcf1da327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165361704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_bit_transfer.3165361704
Directory /workspace/15.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/15.spi_device_byte_transfer.812662813
Short name T1346
Test name
Test status
Simulation time 160025682 ps
CPU time 2.87 seconds
Started Dec 27 01:31:42 PM PST 23
Finished Dec 27 01:31:45 PM PST 23
Peak memory 216856 kb
Host smart-9db66b46-e410-4bb7-8b9c-263661e9d596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812662813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_byte_transfer.812662813
Directory /workspace/15.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2491386913
Short name T1643
Test name
Test status
Simulation time 15027474 ps
CPU time 0.8 seconds
Started Dec 27 01:31:20 PM PST 23
Finished Dec 27 01:31:21 PM PST 23
Peak memory 206492 kb
Host smart-99252a49-465b-46e8-a77a-788564494490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491386913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2491386913
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_dummy_item_extra_dly.2232301971
Short name T991
Test name
Test status
Simulation time 146935300400 ps
CPU time 697.41 seconds
Started Dec 27 01:31:26 PM PST 23
Finished Dec 27 01:43:04 PM PST 23
Peak memory 240788 kb
Host smart-bf591235-ce1b-462d-9e1b-e90b4edc00d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232301971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_dummy_item_extra_dly.2232301971
Directory /workspace/15.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/15.spi_device_fifo_underflow_overflow.2376441253
Short name T1541
Test name
Test status
Simulation time 51017227512 ps
CPU time 257.55 seconds
Started Dec 27 01:32:31 PM PST 23
Finished Dec 27 01:36:54 PM PST 23
Peak memory 310408 kb
Host smart-22e5d763-44c3-4c39-8686-12540b3da584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376441253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_fifo_underflow_overf
low.2376441253
Directory /workspace/15.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.4176162450
Short name T1707
Test name
Test status
Simulation time 29100592925 ps
CPU time 38.62 seconds
Started Dec 27 01:32:02 PM PST 23
Finished Dec 27 01:32:41 PM PST 23
Peak memory 240088 kb
Host smart-b2f713cd-058e-4941-96d2-00730a6e2419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176162450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.4176162450
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.962730959
Short name T263
Test name
Test status
Simulation time 5376058048 ps
CPU time 30.2 seconds
Started Dec 27 01:31:31 PM PST 23
Finished Dec 27 01:32:02 PM PST 23
Peak memory 237788 kb
Host smart-2abe6d96-9518-417a-9d26-6e516f8965fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962730959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.962730959
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3380154594
Short name T652
Test name
Test status
Simulation time 1766354980 ps
CPU time 33.79 seconds
Started Dec 27 01:31:49 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 254192 kb
Host smart-c18605e2-1f5c-4ef6-874f-32d74b8f877b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380154594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3380154594
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2589716378
Short name T1673
Test name
Test status
Simulation time 434550496 ps
CPU time 11.59 seconds
Started Dec 27 01:32:09 PM PST 23
Finished Dec 27 01:32:22 PM PST 23
Peak memory 222812 kb
Host smart-3ce3e30c-7db9-4e02-a32d-dc882bd23885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589716378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2589716378
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.4032733363
Short name T983
Test name
Test status
Simulation time 224289528 ps
CPU time 3.22 seconds
Started Dec 27 01:32:21 PM PST 23
Finished Dec 27 01:32:33 PM PST 23
Peak memory 220492 kb
Host smart-9de79424-6f6e-44f5-9c16-d548f236cca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032733363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.4032733363
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_intr.2907916748
Short name T1140
Test name
Test status
Simulation time 10793291621 ps
CPU time 58.02 seconds
Started Dec 27 01:31:38 PM PST 23
Finished Dec 27 01:32:37 PM PST 23
Peak memory 238744 kb
Host smart-71e0ee40-521c-48ae-ae3f-28ad973c2e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907916748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intr.2907916748
Directory /workspace/15.spi_device_intr/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1119803024
Short name T1569
Test name
Test status
Simulation time 3282983171 ps
CPU time 16.92 seconds
Started Dec 27 01:32:23 PM PST 23
Finished Dec 27 01:32:49 PM PST 23
Peak memory 223204 kb
Host smart-aa0f2ed9-2a2b-4a34-aa69-5d1cb5ac9ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119803024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1119803024
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1434653606
Short name T1310
Test name
Test status
Simulation time 25270993 ps
CPU time 1.09 seconds
Started Dec 27 01:31:30 PM PST 23
Finished Dec 27 01:31:31 PM PST 23
Peak memory 218824 kb
Host smart-15f2eb3e-8330-4cfb-bca1-69c0342a96e3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434653606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1434653606
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2018260640
Short name T346
Test name
Test status
Simulation time 1031746992 ps
CPU time 5.18 seconds
Started Dec 27 01:31:42 PM PST 23
Finished Dec 27 01:31:48 PM PST 23
Peak memory 241380 kb
Host smart-b20d1ce7-1f45-4065-8a11-8cd18832b6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018260640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2018260640
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3684555820
Short name T264
Test name
Test status
Simulation time 33856098619 ps
CPU time 34.06 seconds
Started Dec 27 01:31:34 PM PST 23
Finished Dec 27 01:32:09 PM PST 23
Peak memory 252768 kb
Host smart-8d372592-f974-4e2a-97ed-d1f9d430596e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684555820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3684555820
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_perf.2805883476
Short name T1307
Test name
Test status
Simulation time 37658563453 ps
CPU time 152.3 seconds
Started Dec 27 01:32:06 PM PST 23
Finished Dec 27 01:34:39 PM PST 23
Peak memory 282460 kb
Host smart-f245ce85-ada7-4bc9-8a24-d970f451c748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805883476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_perf.2805883476
Directory /workspace/15.spi_device_perf/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.439868111
Short name T108
Test name
Test status
Simulation time 18826039 ps
CPU time 0.73 seconds
Started Dec 27 01:31:53 PM PST 23
Finished Dec 27 01:31:54 PM PST 23
Peak memory 216648 kb
Host smart-0e0f4e04-ae80-4ff4-961f-36d676ecd039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439868111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.439868111
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3081190026
Short name T15
Test name
Test status
Simulation time 7451188066 ps
CPU time 5.66 seconds
Started Dec 27 01:31:59 PM PST 23
Finished Dec 27 01:32:05 PM PST 23
Peak memory 234764 kb
Host smart-850881bd-0bad-4ad7-a3b8-d6f355ca8440
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3081190026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3081190026
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_rx_async_fifo_reset.4044798769
Short name T65
Test name
Test status
Simulation time 198260068 ps
CPU time 0.95 seconds
Started Dec 27 01:31:43 PM PST 23
Finished Dec 27 01:31:45 PM PST 23
Peak memory 208460 kb
Host smart-ea073320-20b0-4d41-b6dd-d29298b10b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044798769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_rx_async_fifo_reset.4044798769
Directory /workspace/15.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/15.spi_device_rx_timeout.1002998614
Short name T641
Test name
Test status
Simulation time 380728185 ps
CPU time 4.59 seconds
Started Dec 27 01:32:02 PM PST 23
Finished Dec 27 01:32:07 PM PST 23
Peak memory 216892 kb
Host smart-d491c798-c940-404c-a810-f8f7746036af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002998614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_rx_timeout.1002998614
Directory /workspace/15.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/15.spi_device_smoke.3780710108
Short name T495
Test name
Test status
Simulation time 140630992 ps
CPU time 0.95 seconds
Started Dec 27 01:32:38 PM PST 23
Finished Dec 27 01:32:41 PM PST 23
Peak memory 207860 kb
Host smart-f3833a13-f17c-44a4-a69d-3817ef02d98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780710108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_smoke.3780710108
Directory /workspace/15.spi_device_smoke/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2117819555
Short name T1725
Test name
Test status
Simulation time 49354959224 ps
CPU time 31.01 seconds
Started Dec 27 01:31:30 PM PST 23
Finished Dec 27 01:32:02 PM PST 23
Peak memory 216864 kb
Host smart-8fbcca1c-bfe2-429c-a5ac-a15121384bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117819555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2117819555
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2211019261
Short name T885
Test name
Test status
Simulation time 11009784332 ps
CPU time 18.67 seconds
Started Dec 27 01:32:22 PM PST 23
Finished Dec 27 01:32:50 PM PST 23
Peak memory 217944 kb
Host smart-f27b4035-0079-47be-b5af-2d6a4f80eff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211019261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2211019261
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2339489117
Short name T1658
Test name
Test status
Simulation time 73920037 ps
CPU time 1.95 seconds
Started Dec 27 01:31:38 PM PST 23
Finished Dec 27 01:31:41 PM PST 23
Peak memory 216848 kb
Host smart-1589dea4-a867-41ec-9e2d-52d7d5e4a214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339489117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2339489117
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1342093578
Short name T601
Test name
Test status
Simulation time 26901001 ps
CPU time 0.79 seconds
Started Dec 27 01:32:10 PM PST 23
Finished Dec 27 01:32:11 PM PST 23
Peak memory 206848 kb
Host smart-33ea967d-fed3-4687-bb76-767777cdb6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342093578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1342093578
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_tx_async_fifo_reset.3863879289
Short name T159
Test name
Test status
Simulation time 28325490 ps
CPU time 0.78 seconds
Started Dec 27 01:31:28 PM PST 23
Finished Dec 27 01:31:29 PM PST 23
Peak memory 208452 kb
Host smart-f2fa3972-21f7-478d-9de6-2f4f99eba1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863879289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tx_async_fifo_reset.3863879289
Directory /workspace/15.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/15.spi_device_txrx.3584550631
Short name T21
Test name
Test status
Simulation time 307550876143 ps
CPU time 1950.32 seconds
Started Dec 27 01:33:31 PM PST 23
Finished Dec 27 02:06:03 PM PST 23
Peak memory 275104 kb
Host smart-5ed05e88-7523-482c-8129-2bfd82abb50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584550631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_txrx.3584550631
Directory /workspace/15.spi_device_txrx/latest

Test location /workspace/coverage/default/15.spi_device_upload.3908605569
Short name T312
Test name
Test status
Simulation time 812700428 ps
CPU time 12.98 seconds
Started Dec 27 01:32:21 PM PST 23
Finished Dec 27 01:32:44 PM PST 23
Peak memory 257180 kb
Host smart-72dfa7df-0174-487f-b3d9-20f3e82a7714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908605569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3908605569
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_abort.1819921560
Short name T777
Test name
Test status
Simulation time 46393992 ps
CPU time 0.75 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:27 PM PST 23
Peak memory 206612 kb
Host smart-fbcf29fa-758f-41d2-bc57-93ea798259a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819921560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_abort.1819921560
Directory /workspace/16.spi_device_abort/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3387858846
Short name T780
Test name
Test status
Simulation time 14014854 ps
CPU time 0.74 seconds
Started Dec 27 01:32:07 PM PST 23
Finished Dec 27 01:32:09 PM PST 23
Peak memory 206484 kb
Host smart-72a7296f-60c4-4534-8754-daf0bf579ec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387858846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3387858846
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_byte_transfer.516829375
Short name T850
Test name
Test status
Simulation time 177359057 ps
CPU time 3.02 seconds
Started Dec 27 01:32:20 PM PST 23
Finished Dec 27 01:32:31 PM PST 23
Peak memory 216888 kb
Host smart-b43a9e2b-336c-4f93-8ab7-1aeaf999f44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516829375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_byte_transfer.516829375
Directory /workspace/16.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2342032994
Short name T1508
Test name
Test status
Simulation time 96462997 ps
CPU time 2.51 seconds
Started Dec 27 01:32:26 PM PST 23
Finished Dec 27 01:32:36 PM PST 23
Peak memory 218600 kb
Host smart-96b7360d-abf5-4a5b-a2fb-627e03d8f2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342032994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2342032994
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2602221779
Short name T1691
Test name
Test status
Simulation time 27505022 ps
CPU time 0.77 seconds
Started Dec 27 01:32:11 PM PST 23
Finished Dec 27 01:32:13 PM PST 23
Peak memory 207624 kb
Host smart-c60c90cd-5d8e-438a-a9c5-f5c0cf86811d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602221779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2602221779
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_dummy_item_extra_dly.1614437929
Short name T1532
Test name
Test status
Simulation time 28416064237 ps
CPU time 170.56 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:35:14 PM PST 23
Peak memory 264664 kb
Host smart-e8e536b5-4a0f-4096-a65c-00525a5e00e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614437929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_dummy_item_extra_dly.1614437929
Directory /workspace/16.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/16.spi_device_extreme_fifo_size.454883659
Short name T66
Test name
Test status
Simulation time 123851036592 ps
CPU time 842.76 seconds
Started Dec 27 01:31:30 PM PST 23
Finished Dec 27 01:45:34 PM PST 23
Peak memory 220068 kb
Host smart-8318797e-ded7-4c4d-b491-9e1f8790b4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454883659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_extreme_fifo_size.454883659
Directory /workspace/16.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/16.spi_device_fifo_full.2804519434
Short name T822
Test name
Test status
Simulation time 61878608416 ps
CPU time 352.51 seconds
Started Dec 27 01:32:21 PM PST 23
Finished Dec 27 01:38:24 PM PST 23
Peak memory 301428 kb
Host smart-beb3b28a-0aa8-474f-a190-c0c9bfe23360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804519434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_fifo_full.2804519434
Directory /workspace/16.spi_device_fifo_full/latest

Test location /workspace/coverage/default/16.spi_device_fifo_underflow_overflow.3403534931
Short name T1043
Test name
Test status
Simulation time 67560671315 ps
CPU time 359.25 seconds
Started Dec 27 01:31:43 PM PST 23
Finished Dec 27 01:37:43 PM PST 23
Peak memory 379100 kb
Host smart-57967142-a51b-4299-97de-220d8a8e6a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403534931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_fifo_underflow_overf
low.3403534931
Directory /workspace/16.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3250107407
Short name T1355
Test name
Test status
Simulation time 124123281657 ps
CPU time 51.45 seconds
Started Dec 27 01:32:20 PM PST 23
Finished Dec 27 01:33:21 PM PST 23
Peak memory 251368 kb
Host smart-0b5fef12-9ea1-48b8-9005-edafa75c26fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250107407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3250107407
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.292115845
Short name T190
Test name
Test status
Simulation time 1392468006 ps
CPU time 13.77 seconds
Started Dec 27 01:32:51 PM PST 23
Finished Dec 27 01:33:07 PM PST 23
Peak memory 257600 kb
Host smart-8ae68e4b-932f-4edc-a426-a5e88353f2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292115845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.292115845
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2481875087
Short name T1449
Test name
Test status
Simulation time 174982876 ps
CPU time 2.97 seconds
Started Dec 27 01:32:29 PM PST 23
Finished Dec 27 01:32:38 PM PST 23
Peak memory 237532 kb
Host smart-468e3c25-bb95-4675-9c7e-e522c0b9af99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481875087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2481875087
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_intr.1878000668
Short name T208
Test name
Test status
Simulation time 31544189674 ps
CPU time 63.48 seconds
Started Dec 27 01:31:42 PM PST 23
Finished Dec 27 01:32:46 PM PST 23
Peak memory 240248 kb
Host smart-aba865c3-2ecb-43a9-a07e-746fe21d6bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878000668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intr.1878000668
Directory /workspace/16.spi_device_intr/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2291523721
Short name T291
Test name
Test status
Simulation time 2992170937 ps
CPU time 12.98 seconds
Started Dec 27 01:32:31 PM PST 23
Finished Dec 27 01:32:49 PM PST 23
Peak memory 233272 kb
Host smart-c62b30eb-a9a1-4a85-ab6d-dcaffa7ea063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291523721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2291523721
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1685594909
Short name T925
Test name
Test status
Simulation time 214775625 ps
CPU time 1.04 seconds
Started Dec 27 01:32:18 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 218852 kb
Host smart-ff350eb8-f5ee-4d22-8fdb-ac91db092a9f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685594909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1685594909
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.305855996
Short name T1410
Test name
Test status
Simulation time 1407119679 ps
CPU time 9.45 seconds
Started Dec 27 01:32:18 PM PST 23
Finished Dec 27 01:32:33 PM PST 23
Peak memory 247744 kb
Host smart-c54a5502-3d3a-4980-9a29-7e1575b19707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305855996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.305855996
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1759178669
Short name T1458
Test name
Test status
Simulation time 23846839004 ps
CPU time 13.75 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:32:37 PM PST 23
Peak memory 229400 kb
Host smart-1c637d50-d656-4985-a0cd-f40b9827e8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759178669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1759178669
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_perf.1902765046
Short name T1393
Test name
Test status
Simulation time 31736536888 ps
CPU time 1100.21 seconds
Started Dec 27 01:32:12 PM PST 23
Finished Dec 27 01:50:34 PM PST 23
Peak memory 282704 kb
Host smart-64a898bb-633a-47de-ac3f-eb4ce4c2362d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902765046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_perf.1902765046
Directory /workspace/16.spi_device_perf/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.2444773706
Short name T547
Test name
Test status
Simulation time 15978111 ps
CPU time 0.73 seconds
Started Dec 27 01:32:23 PM PST 23
Finished Dec 27 01:32:33 PM PST 23
Peak memory 216732 kb
Host smart-c59ab702-148a-4ca9-be3a-74a3c7817fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444773706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.2444773706
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.476916247
Short name T1568
Test name
Test status
Simulation time 827135385 ps
CPU time 4.23 seconds
Started Dec 27 01:32:51 PM PST 23
Finished Dec 27 01:32:58 PM PST 23
Peak memory 218540 kb
Host smart-695c0e21-6000-450e-a16c-fa84aa1315c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=476916247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.476916247
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_rx_async_fifo_reset.3695800904
Short name T717
Test name
Test status
Simulation time 24976137 ps
CPU time 0.91 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 208392 kb
Host smart-8077a06e-d76e-4ee7-9ff9-521aba9fa871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695800904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_rx_async_fifo_reset.3695800904
Directory /workspace/16.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/16.spi_device_rx_timeout.4199986994
Short name T572
Test name
Test status
Simulation time 1483980484 ps
CPU time 4.33 seconds
Started Dec 27 01:31:47 PM PST 23
Finished Dec 27 01:31:52 PM PST 23
Peak memory 216892 kb
Host smart-69b050a5-7f6d-4d03-814a-acc1b251ec05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199986994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_rx_timeout.4199986994
Directory /workspace/16.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/16.spi_device_smoke.3762753464
Short name T486
Test name
Test status
Simulation time 376792725 ps
CPU time 1.09 seconds
Started Dec 27 01:32:03 PM PST 23
Finished Dec 27 01:32:05 PM PST 23
Peak memory 208436 kb
Host smart-afd870cb-a9a3-43c6-8d12-e739eb7ebb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762753464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_smoke.3762753464
Directory /workspace/16.spi_device_smoke/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1907493036
Short name T1121
Test name
Test status
Simulation time 6010556586 ps
CPU time 72.7 seconds
Started Dec 27 01:32:46 PM PST 23
Finished Dec 27 01:34:00 PM PST 23
Peak memory 216828 kb
Host smart-54f088ec-a693-46ba-835f-a140104540d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907493036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1907493036
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.471842854
Short name T1185
Test name
Test status
Simulation time 1211623741 ps
CPU time 8.73 seconds
Started Dec 27 01:32:13 PM PST 23
Finished Dec 27 01:32:30 PM PST 23
Peak memory 216896 kb
Host smart-62793923-25e2-4621-a026-dd62d12ef10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471842854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.471842854
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2741923006
Short name T617
Test name
Test status
Simulation time 79102556 ps
CPU time 1.58 seconds
Started Dec 27 01:32:24 PM PST 23
Finished Dec 27 01:32:35 PM PST 23
Peak memory 216844 kb
Host smart-2372f30d-7d87-4f7a-80f3-f9d4d6af6da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741923006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2741923006
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1373328247
Short name T1159
Test name
Test status
Simulation time 141070586 ps
CPU time 0.86 seconds
Started Dec 27 01:32:40 PM PST 23
Finished Dec 27 01:32:43 PM PST 23
Peak memory 206940 kb
Host smart-0be31a40-f3da-434b-a175-eeb4c48cbe74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373328247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1373328247
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_tx_async_fifo_reset.353962503
Short name T1431
Test name
Test status
Simulation time 54695119 ps
CPU time 0.76 seconds
Started Dec 27 01:32:24 PM PST 23
Finished Dec 27 01:32:33 PM PST 23
Peak memory 208460 kb
Host smart-3939fbb8-ebec-4040-b81f-adf33d19bb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353962503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tx_async_fifo_reset.353962503
Directory /workspace/16.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/16.spi_device_txrx.3086357405
Short name T1522
Test name
Test status
Simulation time 47898575168 ps
CPU time 112.42 seconds
Started Dec 27 01:31:42 PM PST 23
Finished Dec 27 01:33:35 PM PST 23
Peak memory 240596 kb
Host smart-be060622-020c-42a4-bbd6-d2f65ce7d4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086357405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_txrx.3086357405
Directory /workspace/16.spi_device_txrx/latest

Test location /workspace/coverage/default/16.spi_device_upload.1543761917
Short name T1634
Test name
Test status
Simulation time 169957476 ps
CPU time 2.45 seconds
Started Dec 27 01:32:08 PM PST 23
Finished Dec 27 01:32:12 PM PST 23
Peak memory 218480 kb
Host smart-146c4f3b-00a0-4bb9-811e-4b454f2b5c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543761917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1543761917
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_abort.1889556483
Short name T1412
Test name
Test status
Simulation time 26605222 ps
CPU time 0.74 seconds
Started Dec 27 01:32:26 PM PST 23
Finished Dec 27 01:32:34 PM PST 23
Peak memory 206668 kb
Host smart-c97f3335-a6e1-4090-98f8-c1e4c25b55b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889556483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_abort.1889556483
Directory /workspace/17.spi_device_abort/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2801977128
Short name T1619
Test name
Test status
Simulation time 19814555 ps
CPU time 0.7 seconds
Started Dec 27 01:32:23 PM PST 23
Finished Dec 27 01:32:33 PM PST 23
Peak memory 206412 kb
Host smart-2f966596-7143-489d-93df-3f2a17f6d025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801977128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2801977128
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_bit_transfer.2616349576
Short name T1427
Test name
Test status
Simulation time 259006843 ps
CPU time 2.54 seconds
Started Dec 27 01:32:24 PM PST 23
Finished Dec 27 01:32:36 PM PST 23
Peak memory 216820 kb
Host smart-e1bf4a11-a089-4ffe-93aa-78323105bb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616349576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_bit_transfer.2616349576
Directory /workspace/17.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/17.spi_device_byte_transfer.1046976260
Short name T740
Test name
Test status
Simulation time 246603199 ps
CPU time 3.39 seconds
Started Dec 27 01:31:46 PM PST 23
Finished Dec 27 01:31:50 PM PST 23
Peak memory 216732 kb
Host smart-3ad5eb0b-530a-4ae3-886c-a2e74591ab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046976260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_byte_transfer.1046976260
Directory /workspace/17.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.608850636
Short name T911
Test name
Test status
Simulation time 350577603 ps
CPU time 3.27 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:32:26 PM PST 23
Peak memory 225020 kb
Host smart-53df2732-76ef-480d-b7c2-2e5974ee1286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608850636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.608850636
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.728382503
Short name T761
Test name
Test status
Simulation time 129554745 ps
CPU time 0.76 seconds
Started Dec 27 01:31:48 PM PST 23
Finished Dec 27 01:31:50 PM PST 23
Peak memory 207596 kb
Host smart-ae055615-a839-42dc-b27c-e2dbb8db4c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728382503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.728382503
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_dummy_item_extra_dly.3811044472
Short name T578
Test name
Test status
Simulation time 29625928788 ps
CPU time 136.83 seconds
Started Dec 27 01:31:46 PM PST 23
Finished Dec 27 01:34:09 PM PST 23
Peak memory 255596 kb
Host smart-24d38d6b-df45-4df7-bd34-166440007ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811044472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_dummy_item_extra_dly.3811044472
Directory /workspace/17.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/17.spi_device_extreme_fifo_size.84985883
Short name T114
Test name
Test status
Simulation time 42354743950 ps
CPU time 582.23 seconds
Started Dec 27 01:31:30 PM PST 23
Finished Dec 27 01:41:13 PM PST 23
Peak memory 216980 kb
Host smart-09953da1-eca6-4740-8439-6e36cd57302e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84985883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_extreme_fifo_size.84985883
Directory /workspace/17.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/17.spi_device_fifo_full.1255290289
Short name T574
Test name
Test status
Simulation time 108101607490 ps
CPU time 1837.94 seconds
Started Dec 27 01:31:29 PM PST 23
Finished Dec 27 02:02:07 PM PST 23
Peak memory 256028 kb
Host smart-c579c919-8dbc-4a5c-a887-4bde0e054c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255290289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_fifo_full.1255290289
Directory /workspace/17.spi_device_fifo_full/latest

Test location /workspace/coverage/default/17.spi_device_fifo_underflow_overflow.3887573458
Short name T1588
Test name
Test status
Simulation time 202805695343 ps
CPU time 830.5 seconds
Started Dec 27 01:31:25 PM PST 23
Finished Dec 27 01:45:17 PM PST 23
Peak memory 418548 kb
Host smart-cd61a47e-a803-49b4-912a-dcd52e1a7c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887573458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_fifo_underflow_overf
low.3887573458
Directory /workspace/17.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2841683738
Short name T1223
Test name
Test status
Simulation time 204518067627 ps
CPU time 180.26 seconds
Started Dec 27 01:32:39 PM PST 23
Finished Dec 27 01:35:42 PM PST 23
Peak memory 253460 kb
Host smart-37ef29aa-da24-4ac6-bf23-5a9f0e8405ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841683738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2841683738
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1347154238
Short name T267
Test name
Test status
Simulation time 104211046469 ps
CPU time 205.17 seconds
Started Dec 27 01:32:29 PM PST 23
Finished Dec 27 01:36:00 PM PST 23
Peak memory 257388 kb
Host smart-26e34659-6a7f-4b05-92d6-e4220b1e7c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347154238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1347154238
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2218402165
Short name T1420
Test name
Test status
Simulation time 3750664142 ps
CPU time 9.06 seconds
Started Dec 27 01:32:20 PM PST 23
Finished Dec 27 01:32:38 PM PST 23
Peak memory 233356 kb
Host smart-37fd6237-5a9b-40ee-a372-8471fcd57675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218402165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2218402165
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.4035569945
Short name T1430
Test name
Test status
Simulation time 118147785 ps
CPU time 3.29 seconds
Started Dec 27 01:32:13 PM PST 23
Finished Dec 27 01:32:25 PM PST 23
Peak memory 226244 kb
Host smart-88e279a7-3267-4280-87b0-6e83ffdf7247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035569945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.4035569945
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_intr.4002795825
Short name T1044
Test name
Test status
Simulation time 12817236282 ps
CPU time 56.66 seconds
Started Dec 27 01:32:21 PM PST 23
Finished Dec 27 01:33:27 PM PST 23
Peak memory 239564 kb
Host smart-ba0ee0db-dfaa-42b0-b4b3-cee41716a2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002795825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intr.4002795825
Directory /workspace/17.spi_device_intr/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2027657287
Short name T1746
Test name
Test status
Simulation time 3439520665 ps
CPU time 9.62 seconds
Started Dec 27 01:32:11 PM PST 23
Finished Dec 27 01:32:22 PM PST 23
Peak memory 223896 kb
Host smart-2b4a7933-b6bb-4bc1-9849-c3151b1d1ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027657287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2027657287
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.230894145
Short name T1021
Test name
Test status
Simulation time 51631979 ps
CPU time 1.08 seconds
Started Dec 27 01:31:38 PM PST 23
Finished Dec 27 01:31:40 PM PST 23
Peak memory 218844 kb
Host smart-36ef29fe-fd16-4664-b723-f5d642f7c372
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230894145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.230894145
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3681403068
Short name T1226
Test name
Test status
Simulation time 5828616109 ps
CPU time 20.41 seconds
Started Dec 27 01:32:29 PM PST 23
Finished Dec 27 01:32:55 PM PST 23
Peak memory 235344 kb
Host smart-7c8aa409-7edf-47b1-a89a-b372eea15568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681403068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3681403068
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2946624167
Short name T1662
Test name
Test status
Simulation time 2286325019 ps
CPU time 6.38 seconds
Started Dec 27 01:32:18 PM PST 23
Finished Dec 27 01:32:30 PM PST 23
Peak memory 238892 kb
Host smart-665317ac-2017-4fa0-ad8f-358807dcc218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946624167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2946624167
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_perf.2482356415
Short name T1331
Test name
Test status
Simulation time 18753769011 ps
CPU time 394.75 seconds
Started Dec 27 01:31:48 PM PST 23
Finished Dec 27 01:38:23 PM PST 23
Peak memory 272200 kb
Host smart-3aad882a-a7d0-43dd-a83c-f534fbcdfbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482356415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_perf.2482356415
Directory /workspace/17.spi_device_perf/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.3217938962
Short name T1001
Test name
Test status
Simulation time 17132833 ps
CPU time 0.71 seconds
Started Dec 27 01:32:14 PM PST 23
Finished Dec 27 01:32:22 PM PST 23
Peak memory 216700 kb
Host smart-10865a6e-4f68-4dd0-a986-f6e66ffb1e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217938962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.3217938962
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2022366534
Short name T1566
Test name
Test status
Simulation time 77948492 ps
CPU time 4.03 seconds
Started Dec 27 01:32:21 PM PST 23
Finished Dec 27 01:32:35 PM PST 23
Peak memory 234592 kb
Host smart-7f97913e-d5de-4149-b826-94311059d316
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2022366534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2022366534
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_rx_async_fifo_reset.542223959
Short name T1660
Test name
Test status
Simulation time 81679860 ps
CPU time 0.89 seconds
Started Dec 27 01:32:15 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 208424 kb
Host smart-06537225-d591-488c-94ab-c0e290800c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542223959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_rx_async_fifo_reset.542223959
Directory /workspace/17.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/17.spi_device_rx_timeout.3072487286
Short name T128
Test name
Test status
Simulation time 4872449136 ps
CPU time 6.35 seconds
Started Dec 27 01:31:46 PM PST 23
Finished Dec 27 01:31:53 PM PST 23
Peak memory 216816 kb
Host smart-24b1d273-6b06-4a13-985e-bcf877d35dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072487286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_rx_timeout.3072487286
Directory /workspace/17.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/17.spi_device_smoke.990224968
Short name T55
Test name
Test status
Simulation time 36700179 ps
CPU time 0.99 seconds
Started Dec 27 01:32:06 PM PST 23
Finished Dec 27 01:32:08 PM PST 23
Peak memory 208356 kb
Host smart-64cadf4b-ba54-4b1b-905d-b1082701fe85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990224968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_smoke.990224968
Directory /workspace/17.spi_device_smoke/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3504223060
Short name T1215
Test name
Test status
Simulation time 2073926343 ps
CPU time 33.75 seconds
Started Dec 27 01:32:00 PM PST 23
Finished Dec 27 01:32:34 PM PST 23
Peak memory 216976 kb
Host smart-dd3f18f8-618e-4a83-903c-72a7effbc568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504223060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3504223060
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.699139996
Short name T133
Test name
Test status
Simulation time 15378174947 ps
CPU time 11.15 seconds
Started Dec 27 01:32:32 PM PST 23
Finished Dec 27 01:32:48 PM PST 23
Peak memory 218932 kb
Host smart-5f0b6916-2469-42b5-9369-b0a6b34baaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699139996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.699139996
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.120885190
Short name T1045
Test name
Test status
Simulation time 34225644 ps
CPU time 1 seconds
Started Dec 27 01:32:22 PM PST 23
Finished Dec 27 01:32:33 PM PST 23
Peak memory 207960 kb
Host smart-8e8c0d5b-24a9-4e3d-b44e-870fcff3e1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120885190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.120885190
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3220370235
Short name T1564
Test name
Test status
Simulation time 37795194 ps
CPU time 0.8 seconds
Started Dec 27 01:32:18 PM PST 23
Finished Dec 27 01:32:26 PM PST 23
Peak memory 206932 kb
Host smart-efd1c012-a9e2-4c1d-9c58-b71004056f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220370235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3220370235
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_tx_async_fifo_reset.2635006737
Short name T1491
Test name
Test status
Simulation time 37124755 ps
CPU time 0.78 seconds
Started Dec 27 01:32:42 PM PST 23
Finished Dec 27 01:32:44 PM PST 23
Peak memory 208492 kb
Host smart-10fc5f5c-d78d-44ce-9a25-ee550fb0d076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635006737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tx_async_fifo_reset.2635006737
Directory /workspace/17.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/17.spi_device_txrx.2690814042
Short name T830
Test name
Test status
Simulation time 13013034347 ps
CPU time 130.91 seconds
Started Dec 27 01:32:05 PM PST 23
Finished Dec 27 01:34:17 PM PST 23
Peak memory 257632 kb
Host smart-113faeeb-773d-4917-b82c-2a8d9a4172aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690814042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_txrx.2690814042
Directory /workspace/17.spi_device_txrx/latest

Test location /workspace/coverage/default/17.spi_device_upload.889840627
Short name T1241
Test name
Test status
Simulation time 9093585730 ps
CPU time 16.49 seconds
Started Dec 27 01:32:18 PM PST 23
Finished Dec 27 01:32:40 PM PST 23
Peak memory 223784 kb
Host smart-36bc573e-54e5-47fd-b4bf-2c4fb797ddf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889840627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.889840627
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_abort.3385107287
Short name T981
Test name
Test status
Simulation time 30977610 ps
CPU time 0.72 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:28 PM PST 23
Peak memory 206540 kb
Host smart-2ad9f419-f5db-4442-bdd7-f7b58ddecade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385107287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_abort.3385107287
Directory /workspace/18.spi_device_abort/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1510949964
Short name T1275
Test name
Test status
Simulation time 27218719 ps
CPU time 0.75 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 206528 kb
Host smart-2f8eb28a-0689-467e-9f03-ff095825bf30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510949964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1510949964
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_bit_transfer.1023836914
Short name T971
Test name
Test status
Simulation time 3545043980 ps
CPU time 2.94 seconds
Started Dec 27 01:31:37 PM PST 23
Finished Dec 27 01:31:40 PM PST 23
Peak memory 216856 kb
Host smart-54666869-ccd9-4df7-b614-ff542d804155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023836914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_bit_transfer.1023836914
Directory /workspace/18.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/18.spi_device_byte_transfer.180066548
Short name T1576
Test name
Test status
Simulation time 472480741 ps
CPU time 2.24 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:29 PM PST 23
Peak memory 216796 kb
Host smart-652cdddf-cdab-4c2c-9f57-aa1fbe962f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180066548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_byte_transfer.180066548
Directory /workspace/18.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2483031387
Short name T624
Test name
Test status
Simulation time 447684394 ps
CPU time 3.58 seconds
Started Dec 27 01:32:34 PM PST 23
Finished Dec 27 01:32:41 PM PST 23
Peak memory 220280 kb
Host smart-df81b6d1-2014-4dad-87ca-75b2e605ad03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483031387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2483031387
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1456388612
Short name T1624
Test name
Test status
Simulation time 32145437 ps
CPU time 0.79 seconds
Started Dec 27 01:32:18 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 207600 kb
Host smart-2373cb95-ff4d-405c-873c-a01060f01c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456388612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1456388612
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_dummy_item_extra_dly.1878102327
Short name T1195
Test name
Test status
Simulation time 135111803998 ps
CPU time 1674.59 seconds
Started Dec 27 01:31:32 PM PST 23
Finished Dec 27 01:59:27 PM PST 23
Peak memory 259952 kb
Host smart-dd8dda38-aeee-411f-a913-a3e73c9ff5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878102327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_dummy_item_extra_dly.1878102327
Directory /workspace/18.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/18.spi_device_extreme_fifo_size.1415021743
Short name T71
Test name
Test status
Simulation time 54912147770 ps
CPU time 934.17 seconds
Started Dec 27 01:32:03 PM PST 23
Finished Dec 27 01:47:38 PM PST 23
Peak memory 219084 kb
Host smart-9f4992ea-6dfd-4b12-87f0-f390e4e9a271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415021743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_extreme_fifo_size.1415021743
Directory /workspace/18.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/18.spi_device_fifo_full.1331454346
Short name T567
Test name
Test status
Simulation time 278526221839 ps
CPU time 844.62 seconds
Started Dec 27 01:31:33 PM PST 23
Finished Dec 27 01:45:38 PM PST 23
Peak memory 249696 kb
Host smart-4d6f2185-6034-43fa-8188-794c128e12f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331454346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_fifo_full.1331454346
Directory /workspace/18.spi_device_fifo_full/latest

Test location /workspace/coverage/default/18.spi_device_fifo_underflow_overflow.1798818302
Short name T1468
Test name
Test status
Simulation time 184887243989 ps
CPU time 563.05 seconds
Started Dec 27 01:32:07 PM PST 23
Finished Dec 27 01:41:32 PM PST 23
Peak memory 359888 kb
Host smart-8f55bdf2-aeae-49ff-a330-227c82282a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798818302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_fifo_underflow_overf
low.1798818302
Directory /workspace/18.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.585200659
Short name T216
Test name
Test status
Simulation time 18267343598 ps
CPU time 15.71 seconds
Started Dec 27 01:32:07 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 252336 kb
Host smart-73526539-9888-4050-9ba2-7fe1ef09235b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585200659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.585200659
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3069023010
Short name T1454
Test name
Test status
Simulation time 50780909114 ps
CPU time 127.12 seconds
Started Dec 27 01:32:29 PM PST 23
Finished Dec 27 01:34:42 PM PST 23
Peak memory 250400 kb
Host smart-1fbd5101-d89e-438a-94b5-4ea01525da4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069023010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3069023010
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3615237475
Short name T1318
Test name
Test status
Simulation time 8144625758 ps
CPU time 99.96 seconds
Started Dec 27 01:32:25 PM PST 23
Finished Dec 27 01:34:13 PM PST 23
Peak memory 267604 kb
Host smart-8d2cfcea-71a8-4d86-aac5-6a7bb95391bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615237475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3615237475
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3454785433
Short name T249
Test name
Test status
Simulation time 849323667 ps
CPU time 6.1 seconds
Started Dec 27 01:32:28 PM PST 23
Finished Dec 27 01:32:40 PM PST 23
Peak memory 236836 kb
Host smart-2eba239b-40c2-4322-ba35-aa138de6ce41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454785433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3454785433
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_intr.463492139
Short name T707
Test name
Test status
Simulation time 7042932902 ps
CPU time 48.39 seconds
Started Dec 27 01:32:30 PM PST 23
Finished Dec 27 01:33:24 PM PST 23
Peak memory 234432 kb
Host smart-ee9d703a-ca07-4ba4-9e3b-bd29d6e7448a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463492139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intr.463492139
Directory /workspace/18.spi_device_intr/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1499306341
Short name T1053
Test name
Test status
Simulation time 382079117 ps
CPU time 4.1 seconds
Started Dec 27 01:32:29 PM PST 23
Finished Dec 27 01:32:39 PM PST 23
Peak memory 240876 kb
Host smart-19cf2dca-adc3-44dd-8c2c-003ef8d99567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499306341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1499306341
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1429453832
Short name T1260
Test name
Test status
Simulation time 146256868 ps
CPU time 1.06 seconds
Started Dec 27 01:32:47 PM PST 23
Finished Dec 27 01:32:53 PM PST 23
Peak memory 218912 kb
Host smart-0d25b8dc-401b-4d5a-9d3f-a8c17c314da0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429453832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1429453832
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1237364538
Short name T1183
Test name
Test status
Simulation time 17174942860 ps
CPU time 16.67 seconds
Started Dec 27 01:32:25 PM PST 23
Finished Dec 27 01:32:50 PM PST 23
Peak memory 227976 kb
Host smart-65c437d1-77a7-41cc-abcb-81369da85188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237364538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1237364538
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2777553866
Short name T1717
Test name
Test status
Simulation time 10512603539 ps
CPU time 18.02 seconds
Started Dec 27 01:32:24 PM PST 23
Finished Dec 27 01:32:51 PM PST 23
Peak memory 227924 kb
Host smart-ba6017e9-7101-4df2-90c9-6ae52856afc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777553866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2777553866
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_perf.4254723009
Short name T554
Test name
Test status
Simulation time 28563786892 ps
CPU time 178.46 seconds
Started Dec 27 01:32:15 PM PST 23
Finished Dec 27 01:35:21 PM PST 23
Peak memory 292768 kb
Host smart-0640ca0d-a181-45e4-9fb8-bdf1ee01ab20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254723009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_perf.4254723009
Directory /workspace/18.spi_device_perf/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.246501889
Short name T1326
Test name
Test status
Simulation time 30047080 ps
CPU time 0.72 seconds
Started Dec 27 01:32:24 PM PST 23
Finished Dec 27 01:32:34 PM PST 23
Peak memory 216736 kb
Host smart-65b390a4-b389-4c30-a48a-92e4517b53e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246501889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.246501889
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_rx_async_fifo_reset.510021971
Short name T1041
Test name
Test status
Simulation time 168360279 ps
CPU time 0.93 seconds
Started Dec 27 01:32:12 PM PST 23
Finished Dec 27 01:32:18 PM PST 23
Peak memory 208440 kb
Host smart-616a6deb-218a-47b5-9b0d-0870921c4620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510021971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_rx_async_fifo_reset.510021971
Directory /workspace/18.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/18.spi_device_rx_timeout.2354098618
Short name T1123
Test name
Test status
Simulation time 1104793543 ps
CPU time 5.02 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:33 PM PST 23
Peak memory 216816 kb
Host smart-7a40d5fb-a2f2-478b-8c3e-8bec8acd076d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354098618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_rx_timeout.2354098618
Directory /workspace/18.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/18.spi_device_smoke.3121431490
Short name T130
Test name
Test status
Simulation time 118315627 ps
CPU time 1.15 seconds
Started Dec 27 01:32:15 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 216816 kb
Host smart-72d7b1f1-0bab-4cee-ad54-d333cd4d4078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121431490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_smoke.3121431490
Directory /workspace/18.spi_device_smoke/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.769221777
Short name T786
Test name
Test status
Simulation time 8287627338 ps
CPU time 32.95 seconds
Started Dec 27 01:31:33 PM PST 23
Finished Dec 27 01:32:06 PM PST 23
Peak memory 216992 kb
Host smart-ff289461-18bd-474a-a6c4-15d67e22a008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769221777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.769221777
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3283360886
Short name T1743
Test name
Test status
Simulation time 2444859767 ps
CPU time 13.45 seconds
Started Dec 27 01:32:03 PM PST 23
Finished Dec 27 01:32:17 PM PST 23
Peak memory 216796 kb
Host smart-ba50c736-cab5-4edb-8019-f5a470696f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283360886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3283360886
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3180440725
Short name T1613
Test name
Test status
Simulation time 589846003 ps
CPU time 1.63 seconds
Started Dec 27 01:32:23 PM PST 23
Finished Dec 27 01:32:34 PM PST 23
Peak memory 216872 kb
Host smart-c8a2a44b-ba67-47b4-bb73-efa94d3f987e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180440725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3180440725
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3598895465
Short name T505
Test name
Test status
Simulation time 1306070717 ps
CPU time 1.14 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:29 PM PST 23
Peak memory 208008 kb
Host smart-e1ee8e47-c269-4960-a1af-19c8e4f3d2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598895465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3598895465
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_tx_async_fifo_reset.2006177068
Short name T1163
Test name
Test status
Simulation time 43417252 ps
CPU time 0.79 seconds
Started Dec 27 01:32:12 PM PST 23
Finished Dec 27 01:32:19 PM PST 23
Peak memory 208436 kb
Host smart-0022f386-f2ca-4e35-998d-5c3ed0d9756c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006177068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tx_async_fifo_reset.2006177068
Directory /workspace/18.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/18.spi_device_txrx.1152237303
Short name T584
Test name
Test status
Simulation time 118679003139 ps
CPU time 874.65 seconds
Started Dec 27 01:31:48 PM PST 23
Finished Dec 27 01:46:23 PM PST 23
Peak memory 311848 kb
Host smart-5afa01a0-1fd8-4b82-93ed-10be080d25b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152237303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_txrx.1152237303
Directory /workspace/18.spi_device_txrx/latest

Test location /workspace/coverage/default/18.spi_device_upload.2982730939
Short name T1347
Test name
Test status
Simulation time 212401082 ps
CPU time 5.37 seconds
Started Dec 27 01:32:34 PM PST 23
Finished Dec 27 01:32:43 PM PST 23
Peak memory 229964 kb
Host smart-80aff342-6678-4a7c-9b77-5e0580e27b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982730939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2982730939
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_abort.1525762257
Short name T1505
Test name
Test status
Simulation time 30699463 ps
CPU time 0.75 seconds
Started Dec 27 01:32:25 PM PST 23
Finished Dec 27 01:32:34 PM PST 23
Peak memory 206672 kb
Host smart-d31562dc-b256-41d2-b8dc-7e1cee834119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525762257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_abort.1525762257
Directory /workspace/19.spi_device_abort/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1307634654
Short name T1535
Test name
Test status
Simulation time 21513254 ps
CPU time 0.75 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:32:33 PM PST 23
Peak memory 206388 kb
Host smart-ac1ff8c0-bbe3-4d5c-9016-5f0eb6b4313b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307634654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1307634654
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_byte_transfer.3090843384
Short name T832
Test name
Test status
Simulation time 1249385095 ps
CPU time 2.72 seconds
Started Dec 27 01:32:54 PM PST 23
Finished Dec 27 01:32:59 PM PST 23
Peak memory 216872 kb
Host smart-06bc759d-d2ea-43f8-8e0f-d1ec4d4c6857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090843384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_byte_transfer.3090843384
Directory /workspace/19.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.287367582
Short name T1286
Test name
Test status
Simulation time 583607443 ps
CPU time 4.88 seconds
Started Dec 27 01:32:43 PM PST 23
Finished Dec 27 01:32:49 PM PST 23
Peak memory 239944 kb
Host smart-2c9d27e8-5017-4b81-9ee7-7b902087dbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287367582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.287367582
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2075836058
Short name T516
Test name
Test status
Simulation time 19941455 ps
CPU time 0.78 seconds
Started Dec 27 01:32:54 PM PST 23
Finished Dec 27 01:32:57 PM PST 23
Peak memory 207612 kb
Host smart-66c03043-9d40-4b2e-acb3-0b5a70f46261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075836058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2075836058
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_dummy_item_extra_dly.3977575370
Short name T1096
Test name
Test status
Simulation time 81596180738 ps
CPU time 2318.45 seconds
Started Dec 27 01:32:26 PM PST 23
Finished Dec 27 02:11:12 PM PST 23
Peak memory 249748 kb
Host smart-65553884-b256-458c-896d-a5a115674d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977575370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_dummy_item_extra_dly.3977575370
Directory /workspace/19.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/19.spi_device_extreme_fifo_size.2296293215
Short name T746
Test name
Test status
Simulation time 77400141988 ps
CPU time 1252.57 seconds
Started Dec 27 01:32:18 PM PST 23
Finished Dec 27 01:53:16 PM PST 23
Peak memory 217940 kb
Host smart-03119a57-cad8-4ec5-b4a7-50a2cc58a847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296293215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_extreme_fifo_size.2296293215
Directory /workspace/19.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/19.spi_device_fifo_full.376094770
Short name T16
Test name
Test status
Simulation time 22249172466 ps
CPU time 399.47 seconds
Started Dec 27 01:32:39 PM PST 23
Finished Dec 27 01:39:20 PM PST 23
Peak memory 271764 kb
Host smart-e59d6c37-2a4c-4157-bd70-43ae4f2b754d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376094770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_fifo_full.376094770
Directory /workspace/19.spi_device_fifo_full/latest

Test location /workspace/coverage/default/19.spi_device_fifo_underflow_overflow.2292500011
Short name T209
Test name
Test status
Simulation time 197714812942 ps
CPU time 814.82 seconds
Started Dec 27 01:32:32 PM PST 23
Finished Dec 27 01:46:12 PM PST 23
Peak memory 617948 kb
Host smart-f1d9c07e-8aa3-4d5c-b6df-103e9a122d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292500011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_fifo_underflow_overf
low.2292500011
Directory /workspace/19.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3384110233
Short name T50
Test name
Test status
Simulation time 1564153251 ps
CPU time 18.61 seconds
Started Dec 27 01:32:13 PM PST 23
Finished Dec 27 01:32:40 PM PST 23
Peak memory 251792 kb
Host smart-5aab3610-02cc-4bac-8eba-9a7436740d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384110233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3384110233
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.4003704871
Short name T355
Test name
Test status
Simulation time 7135743682 ps
CPU time 65.44 seconds
Started Dec 27 01:32:25 PM PST 23
Finished Dec 27 01:33:38 PM PST 23
Peak memory 225296 kb
Host smart-cace86d3-c61f-46ab-8f5e-4cd536f70421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003704871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.4003704871
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3511336381
Short name T63
Test name
Test status
Simulation time 188819925651 ps
CPU time 372.8 seconds
Started Dec 27 01:32:29 PM PST 23
Finished Dec 27 01:38:48 PM PST 23
Peak memory 255304 kb
Host smart-21211aff-a2c5-4728-828a-6d05713b42e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511336381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3511336381
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.838938925
Short name T1354
Test name
Test status
Simulation time 9921417505 ps
CPU time 31.25 seconds
Started Dec 27 01:32:38 PM PST 23
Finished Dec 27 01:33:11 PM PST 23
Peak memory 254796 kb
Host smart-19e5e521-3220-45d4-9a8c-13195cea0cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838938925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.838938925
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.4140739169
Short name T1272
Test name
Test status
Simulation time 974177101 ps
CPU time 5.02 seconds
Started Dec 27 01:32:41 PM PST 23
Finished Dec 27 01:32:47 PM PST 23
Peak memory 238736 kb
Host smart-a19a4257-f4d0-4bba-8e2a-f1745800ace3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140739169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4140739169
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_intr.404491464
Short name T597
Test name
Test status
Simulation time 12484607277 ps
CPU time 6.54 seconds
Started Dec 27 01:32:42 PM PST 23
Finished Dec 27 01:32:50 PM PST 23
Peak memory 218072 kb
Host smart-a9eff77c-6a10-4c59-bc30-5ee1c68e58fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404491464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intr.404491464
Directory /workspace/19.spi_device_intr/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1308049821
Short name T45
Test name
Test status
Simulation time 2369224700 ps
CPU time 3.28 seconds
Started Dec 27 01:32:37 PM PST 23
Finished Dec 27 01:32:42 PM PST 23
Peak memory 218836 kb
Host smart-8187c2d2-faf4-4cd0-b622-8b9d9ec6bb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308049821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1308049821
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2509151482
Short name T667
Test name
Test status
Simulation time 26751922 ps
CPU time 1.05 seconds
Started Dec 27 01:32:39 PM PST 23
Finished Dec 27 01:32:42 PM PST 23
Peak memory 218740 kb
Host smart-a56769f2-ad19-481c-b836-d11159e4036e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509151482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2509151482
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2168237923
Short name T35
Test name
Test status
Simulation time 6819161048 ps
CPU time 21.32 seconds
Started Dec 27 01:33:12 PM PST 23
Finished Dec 27 01:33:34 PM PST 23
Peak memory 234260 kb
Host smart-0e9231eb-f081-45ba-a82a-f9f8061869f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168237923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2168237923
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.617352661
Short name T747
Test name
Test status
Simulation time 2178376236 ps
CPU time 8.49 seconds
Started Dec 27 01:32:37 PM PST 23
Finished Dec 27 01:32:47 PM PST 23
Peak memory 220424 kb
Host smart-79860a76-ef78-4d19-9b8c-e6be3a1e45b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617352661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.617352661
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_perf.1456202283
Short name T848
Test name
Test status
Simulation time 40414647514 ps
CPU time 716.95 seconds
Started Dec 27 01:32:53 PM PST 23
Finished Dec 27 01:44:54 PM PST 23
Peak memory 286784 kb
Host smart-6345575d-77e4-4d65-9700-88c8f45ce213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456202283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_perf.1456202283
Directory /workspace/19.spi_device_perf/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.3964140633
Short name T1486
Test name
Test status
Simulation time 31449591 ps
CPU time 0.71 seconds
Started Dec 27 01:32:22 PM PST 23
Finished Dec 27 01:32:32 PM PST 23
Peak memory 216696 kb
Host smart-2b5a1896-525a-4c02-bb30-3cc8037756bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964140633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.3964140633
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2114241160
Short name T588
Test name
Test status
Simulation time 706972923 ps
CPU time 4.45 seconds
Started Dec 27 01:32:40 PM PST 23
Finished Dec 27 01:32:46 PM PST 23
Peak memory 237752 kb
Host smart-56ba696c-4120-407e-972a-4bc1503634e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2114241160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2114241160
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_rx_async_fifo_reset.722511906
Short name T98
Test name
Test status
Simulation time 114281427 ps
CPU time 0.92 seconds
Started Dec 27 01:32:20 PM PST 23
Finished Dec 27 01:32:30 PM PST 23
Peak memory 208400 kb
Host smart-65347d76-fd75-4976-9832-430c0dd02ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722511906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_rx_async_fifo_reset.722511906
Directory /workspace/19.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/19.spi_device_smoke.2721009517
Short name T640
Test name
Test status
Simulation time 37909574 ps
CPU time 1.13 seconds
Started Dec 27 01:32:00 PM PST 23
Finished Dec 27 01:32:02 PM PST 23
Peak memory 216760 kb
Host smart-967bb53c-4d70-41bc-a460-c31466aad5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721009517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_smoke.2721009517
Directory /workspace/19.spi_device_smoke/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.952561164
Short name T248
Test name
Test status
Simulation time 302744837000 ps
CPU time 1228.16 seconds
Started Dec 27 01:32:09 PM PST 23
Finished Dec 27 01:52:38 PM PST 23
Peak memory 316556 kb
Host smart-9d784e26-eaf4-4d89-921b-7ed3e7d1f167
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952561164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.952561164
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3947362850
Short name T1495
Test name
Test status
Simulation time 3736904346 ps
CPU time 35.84 seconds
Started Dec 27 01:32:20 PM PST 23
Finished Dec 27 01:33:05 PM PST 23
Peak memory 216872 kb
Host smart-76d7693a-98ce-4a99-b151-1fc7a68d13df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947362850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3947362850
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.251201126
Short name T634
Test name
Test status
Simulation time 9546234433 ps
CPU time 28.42 seconds
Started Dec 27 01:32:22 PM PST 23
Finished Dec 27 01:33:00 PM PST 23
Peak memory 216920 kb
Host smart-ac59a277-b7fb-4c4f-bb4d-8c9592d9d13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251201126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.251201126
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.856168683
Short name T101
Test name
Test status
Simulation time 208302115 ps
CPU time 5.71 seconds
Started Dec 27 01:32:04 PM PST 23
Finished Dec 27 01:32:10 PM PST 23
Peak memory 216740 kb
Host smart-6223ec61-4fcf-4be2-9b5e-680040eeb28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856168683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.856168683
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2013683244
Short name T898
Test name
Test status
Simulation time 333360970 ps
CPU time 0.83 seconds
Started Dec 27 01:32:56 PM PST 23
Finished Dec 27 01:32:58 PM PST 23
Peak memory 206844 kb
Host smart-92f3cd71-b7b1-46a7-a823-af59647f3200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013683244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2013683244
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_tx_async_fifo_reset.3590024671
Short name T97
Test name
Test status
Simulation time 223026288 ps
CPU time 0.76 seconds
Started Dec 27 01:32:32 PM PST 23
Finished Dec 27 01:32:37 PM PST 23
Peak memory 208352 kb
Host smart-b9d1604b-dbea-4a88-9eac-ad0664c62c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590024671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tx_async_fifo_reset.3590024671
Directory /workspace/19.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/19.spi_device_txrx.2399055356
Short name T757
Test name
Test status
Simulation time 36337230531 ps
CPU time 346.58 seconds
Started Dec 27 01:32:13 PM PST 23
Finished Dec 27 01:38:06 PM PST 23
Peak memory 290248 kb
Host smart-2980eeb0-ccfe-4a87-8dc4-63ace33c470e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399055356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_txrx.2399055356
Directory /workspace/19.spi_device_txrx/latest

Test location /workspace/coverage/default/19.spi_device_upload.3327135044
Short name T1424
Test name
Test status
Simulation time 8327656807 ps
CPU time 11.9 seconds
Started Dec 27 01:32:32 PM PST 23
Finished Dec 27 01:32:49 PM PST 23
Peak memory 241400 kb
Host smart-39a670ba-8165-4bd8-b9eb-8606428b5265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327135044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3327135044
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_abort.1490353564
Short name T627
Test name
Test status
Simulation time 19656397 ps
CPU time 0.73 seconds
Started Dec 27 01:30:20 PM PST 23
Finished Dec 27 01:30:23 PM PST 23
Peak memory 206640 kb
Host smart-8a93c7da-8061-462e-804d-369fbf99cf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490353564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_abort.1490353564
Directory /workspace/2.spi_device_abort/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3927204056
Short name T1268
Test name
Test status
Simulation time 16557488 ps
CPU time 0.82 seconds
Started Dec 27 01:30:25 PM PST 23
Finished Dec 27 01:30:28 PM PST 23
Peak memory 206528 kb
Host smart-98498d13-40b2-4e8c-b999-001008e884a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927204056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
927204056
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_bit_transfer.965227457
Short name T800
Test name
Test status
Simulation time 945045539 ps
CPU time 2.65 seconds
Started Dec 27 01:30:27 PM PST 23
Finished Dec 27 01:30:31 PM PST 23
Peak memory 216836 kb
Host smart-0b29350a-7ab5-445e-94f8-ef5287e0f407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965227457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_bit_transfer.965227457
Directory /workspace/2.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/2.spi_device_byte_transfer.3324394137
Short name T560
Test name
Test status
Simulation time 291370067 ps
CPU time 2.8 seconds
Started Dec 27 01:30:13 PM PST 23
Finished Dec 27 01:30:20 PM PST 23
Peak memory 216736 kb
Host smart-a172edf3-bffa-489e-8e18-fe3452d8962f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324394137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_byte_transfer.3324394137
Directory /workspace/2.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2455571550
Short name T1303
Test name
Test status
Simulation time 914581468 ps
CPU time 3.34 seconds
Started Dec 27 01:30:36 PM PST 23
Finished Dec 27 01:30:41 PM PST 23
Peak memory 219024 kb
Host smart-fd4d1e41-fec1-4705-bc67-dd9048a166e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455571550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2455571550
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2857375684
Short name T910
Test name
Test status
Simulation time 36161232 ps
CPU time 0.79 seconds
Started Dec 27 01:30:16 PM PST 23
Finished Dec 27 01:30:20 PM PST 23
Peak memory 207592 kb
Host smart-1b8ca6de-56ce-42b9-bf43-2405dc046c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857375684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2857375684
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_dummy_item_extra_dly.2472881611
Short name T1478
Test name
Test status
Simulation time 136667884343 ps
CPU time 296.18 seconds
Started Dec 27 01:30:19 PM PST 23
Finished Dec 27 01:35:18 PM PST 23
Peak memory 333576 kb
Host smart-4a3c39cc-53f9-48b0-8b5b-8ffc37218451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472881611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_dummy_item_extra_dly.2472881611
Directory /workspace/2.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/2.spi_device_extreme_fifo_size.2654282980
Short name T1515
Test name
Test status
Simulation time 176198380287 ps
CPU time 3562.73 seconds
Started Dec 27 01:30:45 PM PST 23
Finished Dec 27 02:30:08 PM PST 23
Peak memory 225064 kb
Host smart-ac64cb21-a9e3-4d17-977b-66d836776963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654282980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_extreme_fifo_size.2654282980
Directory /workspace/2.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/2.spi_device_fifo_full.2311216394
Short name T542
Test name
Test status
Simulation time 43468082593 ps
CPU time 481.37 seconds
Started Dec 27 01:30:08 PM PST 23
Finished Dec 27 01:38:14 PM PST 23
Peak memory 260116 kb
Host smart-b50b1afe-8c89-4206-be79-6bb7a2764b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311216394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_fifo_full.2311216394
Directory /workspace/2.spi_device_fifo_full/latest

Test location /workspace/coverage/default/2.spi_device_fifo_underflow_overflow.461469140
Short name T1739
Test name
Test status
Simulation time 75593472630 ps
CPU time 394.94 seconds
Started Dec 27 01:30:11 PM PST 23
Finished Dec 27 01:36:51 PM PST 23
Peak memory 345860 kb
Host smart-662b8d7c-cc76-49bf-94a8-d03e706eb28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461469140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_fifo_underflow_overflo
w.461469140
Directory /workspace/2.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3038869395
Short name T1358
Test name
Test status
Simulation time 15156834097 ps
CPU time 70.94 seconds
Started Dec 27 01:30:44 PM PST 23
Finished Dec 27 01:31:56 PM PST 23
Peak memory 267136 kb
Host smart-bfcd8bbb-37e1-401a-abf2-6cde6b8ca9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038869395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3038869395
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.946219106
Short name T1587
Test name
Test status
Simulation time 26704648728 ps
CPU time 99.63 seconds
Started Dec 27 01:30:34 PM PST 23
Finished Dec 27 01:32:15 PM PST 23
Peak memory 257524 kb
Host smart-a72313cb-c4c4-42c0-ae56-713b01d0c222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946219106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.946219106
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.4006680900
Short name T1090
Test name
Test status
Simulation time 1736529746 ps
CPU time 10.86 seconds
Started Dec 27 01:30:14 PM PST 23
Finished Dec 27 01:30:29 PM PST 23
Peak memory 238380 kb
Host smart-e0da4aed-462e-470c-9e0d-47c369c5f809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006680900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4006680900
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1810480471
Short name T1126
Test name
Test status
Simulation time 10407134903 ps
CPU time 11.43 seconds
Started Dec 27 01:30:39 PM PST 23
Finished Dec 27 01:30:51 PM PST 23
Peak memory 225056 kb
Host smart-7d0baa04-0b6a-43b4-9143-ff6decd111ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810480471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1810480471
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_intr.1415426606
Short name T1187
Test name
Test status
Simulation time 30801814443 ps
CPU time 39.09 seconds
Started Dec 27 01:30:44 PM PST 23
Finished Dec 27 01:31:24 PM PST 23
Peak memory 232828 kb
Host smart-dfe40de1-8889-4e27-932d-5f6f3efe4559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415426606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intr.1415426606
Directory /workspace/2.spi_device_intr/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3211186422
Short name T274
Test name
Test status
Simulation time 9489810709 ps
CPU time 26.39 seconds
Started Dec 27 01:30:15 PM PST 23
Finished Dec 27 01:30:45 PM PST 23
Peak memory 235088 kb
Host smart-eeb6b2b3-22c0-4fc2-8c98-e7187fec2fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211186422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3211186422
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1717669550
Short name T1663
Test name
Test status
Simulation time 18437959 ps
CPU time 1.03 seconds
Started Dec 27 01:30:31 PM PST 23
Finished Dec 27 01:30:33 PM PST 23
Peak memory 218936 kb
Host smart-39bb7006-9c11-4268-b3b5-10614a6d2feb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717669550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1717669550
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.4008393723
Short name T1446
Test name
Test status
Simulation time 2173936095 ps
CPU time 5.04 seconds
Started Dec 27 01:30:26 PM PST 23
Finished Dec 27 01:30:32 PM PST 23
Peak memory 219268 kb
Host smart-f787e90b-3fe2-4568-93d8-ac148c8063ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008393723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.4008393723
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3291790304
Short name T229
Test name
Test status
Simulation time 12298310558 ps
CPU time 10.52 seconds
Started Dec 27 01:30:21 PM PST 23
Finished Dec 27 01:30:33 PM PST 23
Peak memory 238284 kb
Host smart-2441bc3d-c525-4662-a1ca-b71fe9a32d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291790304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3291790304
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_perf.1774636656
Short name T692
Test name
Test status
Simulation time 35287600962 ps
CPU time 499.05 seconds
Started Dec 27 01:30:14 PM PST 23
Finished Dec 27 01:38:37 PM PST 23
Peak memory 285888 kb
Host smart-19426cee-7c93-4729-baf5-54c68adda14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774636656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_perf.1774636656
Directory /workspace/2.spi_device_perf/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.1368137809
Short name T899
Test name
Test status
Simulation time 20950029 ps
CPU time 0.72 seconds
Started Dec 27 01:30:30 PM PST 23
Finished Dec 27 01:30:32 PM PST 23
Peak memory 216728 kb
Host smart-b69bd9d0-92d6-40ab-ab93-9acf80f61e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368137809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.1368137809
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1651263209
Short name T506
Test name
Test status
Simulation time 613048370 ps
CPU time 3.37 seconds
Started Dec 27 01:30:39 PM PST 23
Finished Dec 27 01:30:43 PM PST 23
Peak memory 218848 kb
Host smart-b396f225-d38c-4f15-989e-6d28e5c28222
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1651263209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1651263209
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_rx_timeout.2706190512
Short name T596
Test name
Test status
Simulation time 5626655685 ps
CPU time 5.26 seconds
Started Dec 27 01:30:17 PM PST 23
Finished Dec 27 01:30:25 PM PST 23
Peak memory 216804 kb
Host smart-c5efb856-151c-44e3-a45d-f3403762bdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706190512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_rx_timeout.2706190512
Directory /workspace/2.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.421587928
Short name T113
Test name
Test status
Simulation time 38206404 ps
CPU time 1 seconds
Started Dec 27 01:30:09 PM PST 23
Finished Dec 27 01:30:14 PM PST 23
Peak memory 235752 kb
Host smart-eabfef38-f3be-4d83-94ab-326e75bd6005
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421587928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.421587928
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_smoke.2285249459
Short name T1220
Test name
Test status
Simulation time 52688240 ps
CPU time 0.84 seconds
Started Dec 27 01:30:09 PM PST 23
Finished Dec 27 01:30:13 PM PST 23
Peak memory 207872 kb
Host smart-9d5f7510-8442-44d4-bb5f-ef649dbba7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285249459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_smoke.2285249459
Directory /workspace/2.spi_device_smoke/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2321543238
Short name T1510
Test name
Test status
Simulation time 258343890399 ps
CPU time 1671.63 seconds
Started Dec 27 01:30:27 PM PST 23
Finished Dec 27 01:58:21 PM PST 23
Peak memory 266228 kb
Host smart-73f8fe75-5ad4-4181-8f13-0fbd738ca956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321543238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2321543238
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1664311637
Short name T765
Test name
Test status
Simulation time 5849849318 ps
CPU time 8.26 seconds
Started Dec 27 01:30:41 PM PST 23
Finished Dec 27 01:30:50 PM PST 23
Peak memory 216956 kb
Host smart-b1b58107-6c4d-4466-a231-b8bfd679907e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664311637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1664311637
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.228935842
Short name T119
Test name
Test status
Simulation time 15650290417 ps
CPU time 16.41 seconds
Started Dec 27 01:30:08 PM PST 23
Finished Dec 27 01:30:29 PM PST 23
Peak memory 216828 kb
Host smart-952e3287-0b6c-4677-9f93-669a584fff77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228935842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.228935842
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1309414303
Short name T1048
Test name
Test status
Simulation time 22219670 ps
CPU time 1.24 seconds
Started Dec 27 01:29:59 PM PST 23
Finished Dec 27 01:30:03 PM PST 23
Peak memory 208684 kb
Host smart-241c5329-ab66-4bb7-8bc8-1da500185568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309414303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1309414303
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1075775800
Short name T566
Test name
Test status
Simulation time 15541932 ps
CPU time 0.72 seconds
Started Dec 27 01:30:18 PM PST 23
Finished Dec 27 01:30:21 PM PST 23
Peak memory 206956 kb
Host smart-0cf377c8-d305-4537-8a32-dbb4a675830c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075775800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1075775800
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_tx_async_fifo_reset.497568922
Short name T805
Test name
Test status
Simulation time 14739561 ps
CPU time 0.78 seconds
Started Dec 27 01:30:10 PM PST 23
Finished Dec 27 01:30:14 PM PST 23
Peak memory 208404 kb
Host smart-ee86681a-3c13-432f-9564-f5c2e39da14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497568922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tx_async_fifo_reset.497568922
Directory /workspace/2.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/2.spi_device_txrx.1438111094
Short name T1617
Test name
Test status
Simulation time 758267422456 ps
CPU time 611.46 seconds
Started Dec 27 01:30:16 PM PST 23
Finished Dec 27 01:40:30 PM PST 23
Peak memory 280792 kb
Host smart-9226dad1-bc50-4efe-b4e1-b160311f73e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438111094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_txrx.1438111094
Directory /workspace/2.spi_device_txrx/latest

Test location /workspace/coverage/default/2.spi_device_upload.3194223911
Short name T948
Test name
Test status
Simulation time 12398129425 ps
CPU time 11.54 seconds
Started Dec 27 01:30:11 PM PST 23
Finished Dec 27 01:30:25 PM PST 23
Peak memory 222476 kb
Host smart-69dc3f62-cdd3-4610-92e4-34d4d5d82937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194223911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3194223911
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_abort.3543402427
Short name T1422
Test name
Test status
Simulation time 16097825 ps
CPU time 0.76 seconds
Started Dec 27 01:32:12 PM PST 23
Finished Dec 27 01:32:19 PM PST 23
Peak memory 206644 kb
Host smart-ec22b33d-7a91-44a5-a036-57279ecf4779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543402427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_abort.3543402427
Directory /workspace/20.spi_device_abort/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2127507176
Short name T836
Test name
Test status
Simulation time 11718249 ps
CPU time 0.71 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 206464 kb
Host smart-fa90c700-99af-4c1e-be8e-b328f129b7a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127507176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2127507176
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_bit_transfer.3784824187
Short name T1574
Test name
Test status
Simulation time 422141172 ps
CPU time 3.05 seconds
Started Dec 27 01:32:18 PM PST 23
Finished Dec 27 01:32:29 PM PST 23
Peak memory 216692 kb
Host smart-dd4c46f1-047c-4ac6-a182-be24865c35cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784824187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_bit_transfer.3784824187
Directory /workspace/20.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/20.spi_device_byte_transfer.2009007543
Short name T602
Test name
Test status
Simulation time 318183170 ps
CPU time 2.61 seconds
Started Dec 27 01:32:28 PM PST 23
Finished Dec 27 01:32:37 PM PST 23
Peak memory 216816 kb
Host smart-4edfaae2-8916-4881-97e4-9139c45f552d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009007543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_byte_transfer.2009007543
Directory /workspace/20.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.845036446
Short name T1321
Test name
Test status
Simulation time 8989357102 ps
CPU time 11.26 seconds
Started Dec 27 01:32:18 PM PST 23
Finished Dec 27 01:32:37 PM PST 23
Peak memory 239888 kb
Host smart-14ddeed2-9385-4e32-baa1-a6e9c4b8a983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845036446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.845036446
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3521985840
Short name T1056
Test name
Test status
Simulation time 13734755 ps
CPU time 0.76 seconds
Started Dec 27 01:32:14 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 206492 kb
Host smart-ccf7b9c9-e0e7-46fb-af2f-5a40f1ec7e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521985840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3521985840
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_dummy_item_extra_dly.726303101
Short name T1701
Test name
Test status
Simulation time 97027882698 ps
CPU time 231.53 seconds
Started Dec 27 01:32:28 PM PST 23
Finished Dec 27 01:36:26 PM PST 23
Peak memory 233412 kb
Host smart-e1cb73f6-00d4-4d15-bff6-384051f2588f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726303101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_dummy_item_extra_dly.726303101
Directory /workspace/20.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/20.spi_device_extreme_fifo_size.2688973298
Short name T813
Test name
Test status
Simulation time 6696984983 ps
CPU time 54.61 seconds
Started Dec 27 01:32:26 PM PST 23
Finished Dec 27 01:33:28 PM PST 23
Peak memory 225092 kb
Host smart-15fbecc6-118a-4d59-bf36-d18024d4cf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688973298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_extreme_fifo_size.2688973298
Directory /workspace/20.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/20.spi_device_fifo_full.1412914229
Short name T1675
Test name
Test status
Simulation time 188898855521 ps
CPU time 2747.93 seconds
Started Dec 27 01:32:10 PM PST 23
Finished Dec 27 02:17:59 PM PST 23
Peak memory 290228 kb
Host smart-fed5f5d3-47ff-4abf-9921-0f9e8fc8d91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412914229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_fifo_full.1412914229
Directory /workspace/20.spi_device_fifo_full/latest

Test location /workspace/coverage/default/20.spi_device_fifo_underflow_overflow.2731357510
Short name T72
Test name
Test status
Simulation time 84913357204 ps
CPU time 1853.25 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 02:03:16 PM PST 23
Peak memory 677336 kb
Host smart-4b8359c4-02b9-4cef-b2bb-14f43bce7528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731357510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_fifo_underflow_overf
low.2731357510
Directory /workspace/20.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1928173366
Short name T60
Test name
Test status
Simulation time 14638244653 ps
CPU time 67.69 seconds
Started Dec 27 01:32:42 PM PST 23
Finished Dec 27 01:33:51 PM PST 23
Peak memory 240228 kb
Host smart-50c264ec-2c08-4a1a-bfb5-3da9f62bf56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928173366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1928173366
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.444999952
Short name T1622
Test name
Test status
Simulation time 55372945698 ps
CPU time 112.14 seconds
Started Dec 27 01:32:29 PM PST 23
Finished Dec 27 01:34:27 PM PST 23
Peak memory 239932 kb
Host smart-f20d6abd-b55f-4308-bad7-c3b691564c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444999952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.444999952
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2950513945
Short name T1638
Test name
Test status
Simulation time 224309596 ps
CPU time 4.36 seconds
Started Dec 27 01:32:28 PM PST 23
Finished Dec 27 01:32:38 PM PST 23
Peak memory 219236 kb
Host smart-d8455470-3dc6-4cb3-a46e-bc78b20bacc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950513945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2950513945
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_intr.1464595116
Short name T511
Test name
Test status
Simulation time 5317814336 ps
CPU time 24.3 seconds
Started Dec 27 01:31:58 PM PST 23
Finished Dec 27 01:32:23 PM PST 23
Peak memory 224912 kb
Host smart-9a315d66-4f3e-44d8-916b-c510a069593d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464595116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intr.1464595116
Directory /workspace/20.spi_device_intr/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1344830609
Short name T14
Test name
Test status
Simulation time 4605986462 ps
CPU time 6.02 seconds
Started Dec 27 01:32:35 PM PST 23
Finished Dec 27 01:32:44 PM PST 23
Peak memory 225212 kb
Host smart-6ce7edb7-a145-463d-9e24-363be14f000a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344830609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1344830609
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1195805067
Short name T1285
Test name
Test status
Simulation time 15404692678 ps
CPU time 34.97 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:32:58 PM PST 23
Peak memory 225172 kb
Host smart-5281b521-dbe4-43d2-a999-928f9bcecad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195805067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1195805067
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1091408632
Short name T976
Test name
Test status
Simulation time 1922885522 ps
CPU time 8.56 seconds
Started Dec 27 01:32:50 PM PST 23
Finished Dec 27 01:33:02 PM PST 23
Peak memory 219152 kb
Host smart-4c865e26-efeb-4d56-9cfb-631ff96dd72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091408632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1091408632
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_perf.1286482776
Short name T18
Test name
Test status
Simulation time 70277433232 ps
CPU time 764.46 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:45:07 PM PST 23
Peak memory 282188 kb
Host smart-629d780f-2cd3-4b9f-8ba5-ea24f510ceaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286482776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_perf.1286482776
Directory /workspace/20.spi_device_perf/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2215817966
Short name T753
Test name
Test status
Simulation time 291668199 ps
CPU time 4.01 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:32 PM PST 23
Peak memory 234112 kb
Host smart-9c1dfcf4-a59b-4d51-b780-cd3489a145d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2215817966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2215817966
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_rx_async_fifo_reset.4036862179
Short name T1242
Test name
Test status
Simulation time 33347086 ps
CPU time 0.86 seconds
Started Dec 27 01:32:20 PM PST 23
Finished Dec 27 01:32:31 PM PST 23
Peak memory 208460 kb
Host smart-9d4766ac-0143-4ffb-a2d0-e7996c47873a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036862179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_rx_async_fifo_reset.4036862179
Directory /workspace/20.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/20.spi_device_rx_timeout.360054422
Short name T475
Test name
Test status
Simulation time 898065398 ps
CPU time 6.93 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:32:30 PM PST 23
Peak memory 216860 kb
Host smart-978dde04-44ea-44a0-b17e-88f1f10f3426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360054422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_rx_timeout.360054422
Directory /workspace/20.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/20.spi_device_smoke.4043685758
Short name T539
Test name
Test status
Simulation time 114791256 ps
CPU time 1.14 seconds
Started Dec 27 01:32:24 PM PST 23
Finished Dec 27 01:32:34 PM PST 23
Peak memory 216608 kb
Host smart-2d27eb81-9e6a-4ea8-8a67-5dc32c30d6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043685758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_smoke.4043685758
Directory /workspace/20.spi_device_smoke/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.300445680
Short name T1604
Test name
Test status
Simulation time 2148083792 ps
CPU time 38.54 seconds
Started Dec 27 01:32:39 PM PST 23
Finished Dec 27 01:33:19 PM PST 23
Peak memory 216952 kb
Host smart-4c5ba4bf-2681-4c16-bf55-b79422de9899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300445680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.300445680
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3101929079
Short name T655
Test name
Test status
Simulation time 1103096379 ps
CPU time 3.95 seconds
Started Dec 27 01:32:31 PM PST 23
Finished Dec 27 01:32:40 PM PST 23
Peak memory 216780 kb
Host smart-1aa4d930-a4ab-4064-9b07-ef488478ed77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101929079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3101929079
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.376318054
Short name T935
Test name
Test status
Simulation time 413884994 ps
CPU time 7.81 seconds
Started Dec 27 01:32:45 PM PST 23
Finished Dec 27 01:32:55 PM PST 23
Peak memory 216804 kb
Host smart-a23b0e20-dc92-4741-829d-159e32d5d923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376318054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.376318054
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3193401395
Short name T840
Test name
Test status
Simulation time 55754586 ps
CPU time 0.76 seconds
Started Dec 27 01:32:18 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 206908 kb
Host smart-102e8dab-f3a2-4764-99c9-b7c73800a416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193401395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3193401395
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_tx_async_fifo_reset.1613205693
Short name T96
Test name
Test status
Simulation time 17071125 ps
CPU time 0.79 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 208508 kb
Host smart-af608c6e-72f5-4d9d-bdf3-2366a8ec219d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613205693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tx_async_fifo_reset.1613205693
Directory /workspace/20.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/20.spi_device_txrx.4228777185
Short name T1341
Test name
Test status
Simulation time 27015123924 ps
CPU time 179.49 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:35:23 PM PST 23
Peak memory 257500 kb
Host smart-9f426252-364b-4fb6-ac1a-a9160ea8a712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228777185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_txrx.4228777185
Directory /workspace/20.spi_device_txrx/latest

Test location /workspace/coverage/default/20.spi_device_upload.1149977989
Short name T1035
Test name
Test status
Simulation time 3017779718 ps
CPU time 8.15 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:36 PM PST 23
Peak memory 220440 kb
Host smart-3fd38e85-1523-424a-8ed9-fbd31dc0ac45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149977989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1149977989
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_abort.2244878737
Short name T1507
Test name
Test status
Simulation time 46802334 ps
CPU time 0.72 seconds
Started Dec 27 01:32:31 PM PST 23
Finished Dec 27 01:32:37 PM PST 23
Peak memory 206664 kb
Host smart-6f877d16-62b9-4b22-8cf1-3e015d8950e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244878737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_abort.2244878737
Directory /workspace/21.spi_device_abort/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.978516039
Short name T618
Test name
Test status
Simulation time 32276787 ps
CPU time 0.7 seconds
Started Dec 27 01:32:21 PM PST 23
Finished Dec 27 01:32:32 PM PST 23
Peak memory 206524 kb
Host smart-68f978c5-4f45-41e6-9ae2-97d86af65c68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978516039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.978516039
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_bit_transfer.3024709176
Short name T1736
Test name
Test status
Simulation time 150159873 ps
CPU time 2.65 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:31 PM PST 23
Peak memory 216884 kb
Host smart-678c3ea7-e9d6-4003-b742-64a3debdb78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024709176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_bit_transfer.3024709176
Directory /workspace/21.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/21.spi_device_byte_transfer.4142557988
Short name T1030
Test name
Test status
Simulation time 374383698 ps
CPU time 2.66 seconds
Started Dec 27 01:32:44 PM PST 23
Finished Dec 27 01:32:48 PM PST 23
Peak memory 216868 kb
Host smart-c1e12320-c723-4fe2-989f-e244742257f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142557988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_byte_transfer.4142557988
Directory /workspace/21.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3171166744
Short name T1529
Test name
Test status
Simulation time 1335317932 ps
CPU time 4.96 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:33 PM PST 23
Peak memory 239276 kb
Host smart-ea7ab6a7-ffc8-4973-879c-bfb77604ba90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171166744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3171166744
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2438053586
Short name T488
Test name
Test status
Simulation time 101394775 ps
CPU time 0.8 seconds
Started Dec 27 01:32:48 PM PST 23
Finished Dec 27 01:32:54 PM PST 23
Peak memory 206600 kb
Host smart-15675b32-8879-4346-a890-cdd0ca04053c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438053586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2438053586
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_dummy_item_extra_dly.806739903
Short name T778
Test name
Test status
Simulation time 23637387356 ps
CPU time 167.81 seconds
Started Dec 27 01:32:21 PM PST 23
Finished Dec 27 01:35:18 PM PST 23
Peak memory 268904 kb
Host smart-70e51a46-8fe1-48e8-92ce-4e7ee0ccc5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806739903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_dummy_item_extra_dly.806739903
Directory /workspace/21.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/21.spi_device_extreme_fifo_size.1422714107
Short name T277
Test name
Test status
Simulation time 65523966463 ps
CPU time 2304.58 seconds
Started Dec 27 01:32:29 PM PST 23
Finished Dec 27 02:11:00 PM PST 23
Peak memory 219408 kb
Host smart-b18b4f97-ca1e-4b0e-a257-8cb398873a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422714107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_extreme_fifo_size.1422714107
Directory /workspace/21.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/21.spi_device_fifo_full.2447862269
Short name T1097
Test name
Test status
Simulation time 204393268032 ps
CPU time 1078.25 seconds
Started Dec 27 01:32:22 PM PST 23
Finished Dec 27 01:50:30 PM PST 23
Peak memory 282788 kb
Host smart-acde983e-d3fa-4dba-86cf-35706ee09b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447862269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_fifo_full.2447862269
Directory /workspace/21.spi_device_fifo_full/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1225009697
Short name T308
Test name
Test status
Simulation time 23087268268 ps
CPU time 108.07 seconds
Started Dec 27 01:32:15 PM PST 23
Finished Dec 27 01:34:11 PM PST 23
Peak memory 255516 kb
Host smart-f2a10d54-0f5d-4ddf-9b44-36e7949746ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225009697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1225009697
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2364845050
Short name T305
Test name
Test status
Simulation time 62302716832 ps
CPU time 185.8 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:35:29 PM PST 23
Peak memory 241564 kb
Host smart-77717eca-8397-4b04-9e4f-742fe497d007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364845050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2364845050
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2416794264
Short name T268
Test name
Test status
Simulation time 70459889340 ps
CPU time 154.8 seconds
Started Dec 27 01:32:37 PM PST 23
Finished Dec 27 01:35:18 PM PST 23
Peak memory 249792 kb
Host smart-515c7147-7de4-40cc-885d-69dd038f3b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416794264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2416794264
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3786647911
Short name T1542
Test name
Test status
Simulation time 24109879274 ps
CPU time 29.97 seconds
Started Dec 27 01:32:25 PM PST 23
Finished Dec 27 01:33:03 PM PST 23
Peak memory 233804 kb
Host smart-2a6b46f0-25e1-46b3-8cb6-6728272a8d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786647911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3786647911
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1610356785
Short name T1536
Test name
Test status
Simulation time 1637659077 ps
CPU time 5.05 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:32 PM PST 23
Peak memory 241496 kb
Host smart-0a8c3845-9f33-44d5-b083-6f809c7d26f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610356785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1610356785
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_intr.3150052591
Short name T543
Test name
Test status
Simulation time 2701163021 ps
CPU time 10.33 seconds
Started Dec 27 01:32:50 PM PST 23
Finished Dec 27 01:33:03 PM PST 23
Peak memory 218304 kb
Host smart-ee357046-ce0e-461a-b00d-3ed3b9a25fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150052591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intr.3150052591
Directory /workspace/21.spi_device_intr/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.883847448
Short name T478
Test name
Test status
Simulation time 6933351163 ps
CPU time 8.65 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:32:32 PM PST 23
Peak memory 227100 kb
Host smart-3b161c1c-6f21-485a-bb23-12c54ae2dcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883847448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.883847448
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.768095028
Short name T1503
Test name
Test status
Simulation time 580863356 ps
CPU time 5.51 seconds
Started Dec 27 01:32:05 PM PST 23
Finished Dec 27 01:32:12 PM PST 23
Peak memory 241396 kb
Host smart-446e0046-b2a3-4792-85a0-b5f77f85a3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768095028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.768095028
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.393504115
Short name T929
Test name
Test status
Simulation time 3217507012 ps
CPU time 7.09 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:32:30 PM PST 23
Peak memory 219260 kb
Host smart-b00db2a2-dfac-48b9-a33c-65305ff274ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393504115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.393504115
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_perf.3604941882
Short name T496
Test name
Test status
Simulation time 20542077885 ps
CPU time 1204.28 seconds
Started Dec 27 01:32:29 PM PST 23
Finished Dec 27 01:52:39 PM PST 23
Peak memory 273456 kb
Host smart-da5a54ed-28b3-4a04-8546-9fe608ddc87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604941882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_perf.3604941882
Directory /workspace/21.spi_device_perf/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2732891699
Short name T504
Test name
Test status
Simulation time 363213798 ps
CPU time 3.72 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:32:27 PM PST 23
Peak memory 219564 kb
Host smart-51f0eab4-ceaa-4280-8ef3-438f4545e723
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2732891699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2732891699
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_rx_async_fifo_reset.2062643888
Short name T884
Test name
Test status
Simulation time 18548806 ps
CPU time 0.87 seconds
Started Dec 27 01:32:29 PM PST 23
Finished Dec 27 01:32:36 PM PST 23
Peak memory 208492 kb
Host smart-7f1c5816-7d01-43d0-9eec-c44251ccdaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062643888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_rx_async_fifo_reset.2062643888
Directory /workspace/21.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/21.spi_device_rx_timeout.3931617187
Short name T703
Test name
Test status
Simulation time 608950212 ps
CPU time 5.82 seconds
Started Dec 27 01:32:37 PM PST 23
Finished Dec 27 01:32:44 PM PST 23
Peak memory 216808 kb
Host smart-3864f1f7-26df-41cf-8485-d491078ed635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931617187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_rx_timeout.3931617187
Directory /workspace/21.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/21.spi_device_smoke.1911234102
Short name T762
Test name
Test status
Simulation time 256815269 ps
CPU time 1.11 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:32:28 PM PST 23
Peak memory 216528 kb
Host smart-000d88fb-f003-4c85-8d4e-6a87d44cea30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911234102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_smoke.1911234102
Directory /workspace/21.spi_device_smoke/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.112273155
Short name T358
Test name
Test status
Simulation time 1558688338 ps
CPU time 6.65 seconds
Started Dec 27 01:32:02 PM PST 23
Finished Dec 27 01:32:09 PM PST 23
Peak memory 216784 kb
Host smart-0253e422-5dc8-4694-b235-1ac42f6e6229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112273155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.112273155
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2411789403
Short name T134
Test name
Test status
Simulation time 8052782784 ps
CPU time 13.29 seconds
Started Dec 27 01:32:35 PM PST 23
Finished Dec 27 01:32:51 PM PST 23
Peak memory 217940 kb
Host smart-577fa85c-282d-4a3c-b040-115c602bb126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411789403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2411789403
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3556436586
Short name T1745
Test name
Test status
Simulation time 269228715 ps
CPU time 2.82 seconds
Started Dec 27 01:32:08 PM PST 23
Finished Dec 27 01:32:12 PM PST 23
Peak memory 216740 kb
Host smart-28d407bd-af5a-428f-9e67-5aece1986248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556436586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3556436586
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.4233537360
Short name T903
Test name
Test status
Simulation time 135535316 ps
CPU time 1.12 seconds
Started Dec 27 01:32:11 PM PST 23
Finished Dec 27 01:32:13 PM PST 23
Peak memory 207896 kb
Host smart-71492981-e987-4c30-82a2-35af5d52f215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233537360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.4233537360
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_tx_async_fifo_reset.3448602691
Short name T1217
Test name
Test status
Simulation time 17002472 ps
CPU time 0.78 seconds
Started Dec 27 01:32:12 PM PST 23
Finished Dec 27 01:32:14 PM PST 23
Peak memory 208336 kb
Host smart-454bc94a-db30-47ea-bc6d-847cb3c222ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448602691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tx_async_fifo_reset.3448602691
Directory /workspace/21.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/21.spi_device_txrx.4038558909
Short name T862
Test name
Test status
Simulation time 26015283516 ps
CPU time 201.91 seconds
Started Dec 27 01:32:42 PM PST 23
Finished Dec 27 01:36:05 PM PST 23
Peak memory 257012 kb
Host smart-38a6b77c-16b5-4b7e-b5e2-f654910243ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038558909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_txrx.4038558909
Directory /workspace/21.spi_device_txrx/latest

Test location /workspace/coverage/default/21.spi_device_upload.3255865613
Short name T1460
Test name
Test status
Simulation time 11761503901 ps
CPU time 5.38 seconds
Started Dec 27 01:32:37 PM PST 23
Finished Dec 27 01:32:44 PM PST 23
Peak memory 219832 kb
Host smart-15d13b9b-c358-4d6e-a263-4ad93ae66436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255865613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3255865613
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_abort.310438267
Short name T1154
Test name
Test status
Simulation time 15748365 ps
CPU time 0.75 seconds
Started Dec 27 01:32:45 PM PST 23
Finished Dec 27 01:32:47 PM PST 23
Peak memory 206664 kb
Host smart-5fb452a6-6726-4611-84d1-1572dfab6ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310438267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_abort.310438267
Directory /workspace/22.spi_device_abort/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.145791409
Short name T1322
Test name
Test status
Simulation time 24221397 ps
CPU time 0.72 seconds
Started Dec 27 01:32:51 PM PST 23
Finished Dec 27 01:32:54 PM PST 23
Peak memory 206524 kb
Host smart-8b1a3a15-db87-46ba-bf93-9049d7122403
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145791409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.145791409
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_bit_transfer.688004648
Short name T1621
Test name
Test status
Simulation time 172382556 ps
CPU time 2.76 seconds
Started Dec 27 01:32:20 PM PST 23
Finished Dec 27 01:32:32 PM PST 23
Peak memory 216692 kb
Host smart-c24517d5-cbb9-4929-9313-58cc368a31c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688004648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_bit_transfer.688004648
Directory /workspace/22.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/22.spi_device_byte_transfer.3790915587
Short name T1360
Test name
Test status
Simulation time 156849920 ps
CPU time 2.92 seconds
Started Dec 27 01:32:39 PM PST 23
Finished Dec 27 01:32:44 PM PST 23
Peak memory 216716 kb
Host smart-d34b351a-5add-4d5a-a7d5-dee7486eb149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790915587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_byte_transfer.3790915587
Directory /workspace/22.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2024501831
Short name T1213
Test name
Test status
Simulation time 122782079 ps
CPU time 3.66 seconds
Started Dec 27 01:32:37 PM PST 23
Finished Dec 27 01:32:42 PM PST 23
Peak memory 241068 kb
Host smart-0f228536-6ad4-4da4-9331-89f349944275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024501831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2024501831
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.129399029
Short name T526
Test name
Test status
Simulation time 64454118 ps
CPU time 0.82 seconds
Started Dec 27 01:32:28 PM PST 23
Finished Dec 27 01:32:35 PM PST 23
Peak memory 207588 kb
Host smart-7de4bffb-4598-4b36-93d1-b249a09247ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129399029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.129399029
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_dummy_item_extra_dly.3765816787
Short name T1263
Test name
Test status
Simulation time 404529865176 ps
CPU time 226.66 seconds
Started Dec 27 01:32:22 PM PST 23
Finished Dec 27 01:36:19 PM PST 23
Peak memory 265896 kb
Host smart-6bc4d5f4-0019-4fcd-88f6-e8a038aeac4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765816787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_dummy_item_extra_dly.3765816787
Directory /workspace/22.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/22.spi_device_extreme_fifo_size.3565340462
Short name T1557
Test name
Test status
Simulation time 43136795045 ps
CPU time 1442.77 seconds
Started Dec 27 01:32:23 PM PST 23
Finished Dec 27 01:56:35 PM PST 23
Peak memory 225072 kb
Host smart-0a6ca3cc-21fe-4686-8e04-13a206a6af39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565340462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_extreme_fifo_size.3565340462
Directory /workspace/22.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/22.spi_device_fifo_full.2334732634
Short name T632
Test name
Test status
Simulation time 142974624941 ps
CPU time 558.89 seconds
Started Dec 27 01:32:47 PM PST 23
Finished Dec 27 01:42:11 PM PST 23
Peak memory 285132 kb
Host smart-6e1db88a-b2b6-4ee8-8936-ba89b3967c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334732634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_fifo_full.2334732634
Directory /workspace/22.spi_device_fifo_full/latest

Test location /workspace/coverage/default/22.spi_device_fifo_underflow_overflow.1562863463
Short name T1209
Test name
Test status
Simulation time 40774265896 ps
CPU time 332.47 seconds
Started Dec 27 01:32:19 PM PST 23
Finished Dec 27 01:38:01 PM PST 23
Peak memory 453736 kb
Host smart-f4771696-9ef9-4522-b782-0adb8ed7ca77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562863463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_fifo_underflow_overf
low.1562863463
Directory /workspace/22.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.660415808
Short name T244
Test name
Test status
Simulation time 7705858321 ps
CPU time 19.23 seconds
Started Dec 27 01:32:52 PM PST 23
Finished Dec 27 01:33:16 PM PST 23
Peak memory 233264 kb
Host smart-d756ab1d-9945-47fb-bac1-650693f5c9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660415808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.660415808
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1406717140
Short name T1560
Test name
Test status
Simulation time 116714566355 ps
CPU time 422.19 seconds
Started Dec 27 01:32:24 PM PST 23
Finished Dec 27 01:39:35 PM PST 23
Peak memory 266132 kb
Host smart-cda58153-a844-46b4-987f-afae0b8c836e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406717140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1406717140
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3875351954
Short name T1248
Test name
Test status
Simulation time 5278250984 ps
CPU time 28.27 seconds
Started Dec 27 01:32:35 PM PST 23
Finished Dec 27 01:33:06 PM PST 23
Peak memory 247908 kb
Host smart-13a7a23d-94a8-49bb-9f66-eb7af15a396e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875351954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3875351954
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2637113624
Short name T1141
Test name
Test status
Simulation time 2082981750 ps
CPU time 5.06 seconds
Started Dec 27 01:32:27 PM PST 23
Finished Dec 27 01:32:39 PM PST 23
Peak memory 238508 kb
Host smart-f95c1b91-f7f6-4d3e-847d-dc289b6d290b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637113624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2637113624
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_intr.979790796
Short name T64
Test name
Test status
Simulation time 9782663021 ps
CPU time 9.88 seconds
Started Dec 27 01:32:33 PM PST 23
Finished Dec 27 01:32:47 PM PST 23
Peak memory 216960 kb
Host smart-a2b03d08-ce35-4a90-a7ef-6f0413f4a073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979790796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intr.979790796
Directory /workspace/22.spi_device_intr/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.690946780
Short name T1300
Test name
Test status
Simulation time 5566115352 ps
CPU time 8.06 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:32:31 PM PST 23
Peak memory 227008 kb
Host smart-cd9be351-4eac-4c90-8cbb-5ac296566381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690946780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.690946780
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1430655571
Short name T1583
Test name
Test status
Simulation time 30643639606 ps
CPU time 26.22 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:32:49 PM PST 23
Peak memory 250660 kb
Host smart-21faa780-1ae3-4919-9e2d-9582f7022312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430655571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1430655571
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3196814252
Short name T930
Test name
Test status
Simulation time 4824344982 ps
CPU time 16.43 seconds
Started Dec 27 01:32:12 PM PST 23
Finished Dec 27 01:32:30 PM PST 23
Peak memory 225028 kb
Host smart-a0f906b8-12af-4156-a8c7-204a989778f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196814252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3196814252
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_perf.2269448671
Short name T482
Test name
Test status
Simulation time 173592228479 ps
CPU time 968.38 seconds
Started Dec 27 01:32:24 PM PST 23
Finished Dec 27 01:48:41 PM PST 23
Peak memory 307216 kb
Host smart-afa61936-b3d6-42e5-8ead-3a081f9a53f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269448671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_perf.2269448671
Directory /workspace/22.spi_device_perf/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.4062068846
Short name T743
Test name
Test status
Simulation time 694210880 ps
CPU time 4.16 seconds
Started Dec 27 01:32:36 PM PST 23
Finished Dec 27 01:32:42 PM PST 23
Peak memory 221944 kb
Host smart-c6f1f4ed-4ba3-4c3b-8ba8-74e3a5409d00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4062068846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.4062068846
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_rx_async_fifo_reset.2075843530
Short name T881
Test name
Test status
Simulation time 19046360 ps
CPU time 0.85 seconds
Started Dec 27 01:32:17 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 208448 kb
Host smart-40cbe206-37a6-4e86-ad78-6c24bdb784aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075843530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_rx_async_fifo_reset.2075843530
Directory /workspace/22.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/22.spi_device_rx_timeout.2230001412
Short name T1625
Test name
Test status
Simulation time 1158180873 ps
CPU time 5.33 seconds
Started Dec 27 01:32:38 PM PST 23
Finished Dec 27 01:32:44 PM PST 23
Peak memory 216668 kb
Host smart-adbb5b3d-b15d-42c1-8816-b19110716928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230001412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_rx_timeout.2230001412
Directory /workspace/22.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/22.spi_device_smoke.3560547238
Short name T579
Test name
Test status
Simulation time 34014659 ps
CPU time 1.02 seconds
Started Dec 27 01:32:20 PM PST 23
Finished Dec 27 01:32:30 PM PST 23
Peak memory 208332 kb
Host smart-ec69ca76-ddc9-4ca8-b889-db5651f6d9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560547238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_smoke.3560547238
Directory /workspace/22.spi_device_smoke/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.596030744
Short name T1504
Test name
Test status
Simulation time 266436696178 ps
CPU time 958.63 seconds
Started Dec 27 01:32:22 PM PST 23
Finished Dec 27 01:48:30 PM PST 23
Peak memory 308036 kb
Host smart-52c76f3a-32a6-44c6-8747-51695354588b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596030744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.596030744
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1054857108
Short name T1381
Test name
Test status
Simulation time 422913459 ps
CPU time 2.81 seconds
Started Dec 27 01:32:21 PM PST 23
Finished Dec 27 01:32:33 PM PST 23
Peak memory 219016 kb
Host smart-8e8b3472-cd32-415f-9381-e534db22c947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054857108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1054857108
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2057584491
Short name T121
Test name
Test status
Simulation time 597610166 ps
CPU time 4 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:32:27 PM PST 23
Peak memory 216748 kb
Host smart-433cd498-e870-41c2-a6e9-b5119697ce16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057584491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2057584491
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1687605703
Short name T1697
Test name
Test status
Simulation time 52883521 ps
CPU time 1 seconds
Started Dec 27 01:32:31 PM PST 23
Finished Dec 27 01:32:37 PM PST 23
Peak memory 207908 kb
Host smart-217ac078-bce8-4c27-9540-4fcba429a129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687605703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1687605703
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.19778230
Short name T493
Test name
Test status
Simulation time 23016138 ps
CPU time 0.77 seconds
Started Dec 27 01:32:37 PM PST 23
Finished Dec 27 01:32:39 PM PST 23
Peak memory 206944 kb
Host smart-30999197-d16d-47e0-90df-45b7c1d5b496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19778230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.19778230
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_tx_async_fifo_reset.1532067524
Short name T1438
Test name
Test status
Simulation time 17375656 ps
CPU time 0.75 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:32:24 PM PST 23
Peak memory 208436 kb
Host smart-9e00cb45-1e35-4a0f-9cc8-820a4d184139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532067524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tx_async_fifo_reset.1532067524
Directory /workspace/22.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/22.spi_device_txrx.3660190900
Short name T1480
Test name
Test status
Simulation time 120849874109 ps
CPU time 102.2 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:34:05 PM PST 23
Peak memory 259608 kb
Host smart-b47afe16-6a0f-43cf-b969-2af312438480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660190900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_txrx.3660190900
Directory /workspace/22.spi_device_txrx/latest

Test location /workspace/coverage/default/22.spi_device_upload.1361001164
Short name T1245
Test name
Test status
Simulation time 7117435837 ps
CPU time 14.06 seconds
Started Dec 27 01:32:57 PM PST 23
Finished Dec 27 01:33:12 PM PST 23
Peak memory 225184 kb
Host smart-6f231bfa-b043-4dac-b109-3b539a73c4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361001164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1361001164
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_abort.2753952885
Short name T628
Test name
Test status
Simulation time 52065567 ps
CPU time 0.73 seconds
Started Dec 27 01:32:51 PM PST 23
Finished Dec 27 01:32:54 PM PST 23
Peak memory 206668 kb
Host smart-5da743f1-d426-4e6f-8c9b-2071d067defb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753952885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_abort.2753952885
Directory /workspace/23.spi_device_abort/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.39086310
Short name T907
Test name
Test status
Simulation time 19615457 ps
CPU time 0.77 seconds
Started Dec 27 01:32:57 PM PST 23
Finished Dec 27 01:32:58 PM PST 23
Peak memory 206512 kb
Host smart-c20307da-79f7-4613-8e37-0347f135702c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39086310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.39086310
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_bit_transfer.1146968017
Short name T838
Test name
Test status
Simulation time 137051673 ps
CPU time 2.59 seconds
Started Dec 27 01:32:43 PM PST 23
Finished Dec 27 01:32:47 PM PST 23
Peak memory 216792 kb
Host smart-0bea8139-9f84-4f2e-9d42-cb7f19e0ba02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146968017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_bit_transfer.1146968017
Directory /workspace/23.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/23.spi_device_byte_transfer.4247161011
Short name T519
Test name
Test status
Simulation time 163313170 ps
CPU time 3.12 seconds
Started Dec 27 01:32:34 PM PST 23
Finished Dec 27 01:32:41 PM PST 23
Peak memory 216868 kb
Host smart-59b5c5e8-6514-410a-a822-daaff7d33d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247161011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_byte_transfer.4247161011
Directory /workspace/23.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3439811167
Short name T292
Test name
Test status
Simulation time 2015942338 ps
CPU time 5.27 seconds
Started Dec 27 01:33:00 PM PST 23
Finished Dec 27 01:33:06 PM PST 23
Peak memory 220656 kb
Host smart-13b1af24-e817-4835-950f-de090f97d305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439811167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3439811167
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2531269089
Short name T1483
Test name
Test status
Simulation time 53237521 ps
CPU time 0.76 seconds
Started Dec 27 01:32:34 PM PST 23
Finished Dec 27 01:32:38 PM PST 23
Peak memory 206592 kb
Host smart-08782cf2-3897-4ccd-b27d-6ad0049f2f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531269089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2531269089
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_dummy_item_extra_dly.3514109033
Short name T1512
Test name
Test status
Simulation time 205476022735 ps
CPU time 1167.26 seconds
Started Dec 27 01:32:22 PM PST 23
Finished Dec 27 01:51:59 PM PST 23
Peak memory 249680 kb
Host smart-a02936ad-ebfe-444c-93ec-9e26f0fd9eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514109033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_dummy_item_extra_dly.3514109033
Directory /workspace/23.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/23.spi_device_extreme_fifo_size.451230502
Short name T1628
Test name
Test status
Simulation time 202023323796 ps
CPU time 1663.01 seconds
Started Dec 27 01:32:21 PM PST 23
Finished Dec 27 02:00:14 PM PST 23
Peak memory 218124 kb
Host smart-f59c34a7-2de9-4203-85ae-2d4d8b168c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451230502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_extreme_fifo_size.451230502
Directory /workspace/23.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/23.spi_device_fifo_full.1096311645
Short name T782
Test name
Test status
Simulation time 45208005585 ps
CPU time 714.26 seconds
Started Dec 27 01:32:47 PM PST 23
Finished Dec 27 01:44:46 PM PST 23
Peak memory 273360 kb
Host smart-4c8422e8-f3d1-47e4-9fd6-3894f944260d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096311645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_fifo_full.1096311645
Directory /workspace/23.spi_device_fifo_full/latest

Test location /workspace/coverage/default/23.spi_device_fifo_underflow_overflow.2763736052
Short name T1270
Test name
Test status
Simulation time 181893077045 ps
CPU time 901.97 seconds
Started Dec 27 01:32:16 PM PST 23
Finished Dec 27 01:47:25 PM PST 23
Peak memory 546460 kb
Host smart-18bbad90-658f-492f-8a36-c97673ff684b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763736052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_fifo_underflow_overf
low.2763736052
Directory /workspace/23.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.887543993
Short name T247
Test name
Test status
Simulation time 25679331934 ps
CPU time 93.28 seconds
Started Dec 27 01:32:47 PM PST 23
Finished Dec 27 01:34:25 PM PST 23
Peak memory 266136 kb
Host smart-9052cb72-343a-47a5-a31f-e5a278c64613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887543993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.887543993
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1375282059
Short name T251
Test name
Test status
Simulation time 3324779754 ps
CPU time 13.69 seconds
Started Dec 27 01:33:43 PM PST 23
Finished Dec 27 01:33:58 PM PST 23
Peak memory 236892 kb
Host smart-6d98214f-8055-4508-808a-49fb081e0f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375282059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1375282059
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2137149001
Short name T647
Test name
Test status
Simulation time 168425814695 ps
CPU time 54.25 seconds
Started Dec 27 01:32:55 PM PST 23
Finished Dec 27 01:33:51 PM PST 23
Peak memory 250024 kb
Host smart-d548070c-c68e-47cf-91eb-b5c234cfcf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137149001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2137149001
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1175698210
Short name T262
Test name
Test status
Simulation time 3838607645 ps
CPU time 26.61 seconds
Started Dec 27 01:32:40 PM PST 23
Finished Dec 27 01:33:08 PM PST 23
Peak memory 235360 kb
Host smart-7ff4c265-bb9d-4411-84f9-807ca3096a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175698210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1175698210
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1691410107
Short name T678
Test name
Test status
Simulation time 39821356 ps
CPU time 2.91 seconds
Started Dec 27 01:32:54 PM PST 23
Finished Dec 27 01:33:00 PM PST 23
Peak memory 234292 kb
Host smart-5d85751c-3e73-4acb-b515-4b4d816fbb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691410107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1691410107
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_intr.3214975842
Short name T520
Test name
Test status
Simulation time 89173170399 ps
CPU time 37.96 seconds
Started Dec 27 01:32:50 PM PST 23
Finished Dec 27 01:33:31 PM PST 23
Peak memory 223120 kb
Host smart-65e7766f-f963-42ed-8ef8-b52000bd0eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214975842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intr.3214975842
Directory /workspace/23.spi_device_intr/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3090182494
Short name T1356
Test name
Test status
Simulation time 86397425015 ps
CPU time 34.27 seconds
Started Dec 27 01:32:33 PM PST 23
Finished Dec 27 01:33:11 PM PST 23
Peak memory 224368 kb
Host smart-be677372-34da-4f9e-9a73-e2c154517fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090182494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3090182494
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.748851451
Short name T1317
Test name
Test status
Simulation time 365364516 ps
CPU time 5.04 seconds
Started Dec 27 01:32:51 PM PST 23
Finished Dec 27 01:32:58 PM PST 23
Peak memory 226720 kb
Host smart-1c52dc17-9b0a-4c64-a8b6-e8262826a1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748851451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.748851451
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3170959200
Short name T1397
Test name
Test status
Simulation time 2433105405 ps
CPU time 7.76 seconds
Started Dec 27 01:33:19 PM PST 23
Finished Dec 27 01:33:28 PM PST 23
Peak memory 241412 kb
Host smart-0c6f5926-24d5-4fd1-b643-557ec15fbeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170959200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3170959200
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_perf.2870693708
Short name T827
Test name
Test status
Simulation time 22321236716 ps
CPU time 1495.88 seconds
Started Dec 27 01:33:08 PM PST 23
Finished Dec 27 01:58:06 PM PST 23
Peak memory 298196 kb
Host smart-51c9b006-cf67-4dd6-9e57-45f1fa534f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870693708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_perf.2870693708
Directory /workspace/23.spi_device_perf/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.330948724
Short name T642
Test name
Test status
Simulation time 2932432586 ps
CPU time 5.09 seconds
Started Dec 27 01:32:29 PM PST 23
Finished Dec 27 01:32:40 PM PST 23
Peak memory 221200 kb
Host smart-6fb8d734-95cd-440c-b12b-13b9b8380304
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=330948724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.330948724
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_rx_async_fifo_reset.4096146438
Short name T974
Test name
Test status
Simulation time 131991331 ps
CPU time 0.9 seconds
Started Dec 27 01:32:39 PM PST 23
Finished Dec 27 01:32:42 PM PST 23
Peak memory 208396 kb
Host smart-37e6b499-3430-4342-a67e-d86a7686c4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096146438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_rx_async_fifo_reset.4096146438
Directory /workspace/23.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/23.spi_device_rx_timeout.621846787
Short name T1418
Test name
Test status
Simulation time 4044737756 ps
CPU time 4.97 seconds
Started Dec 27 01:32:48 PM PST 23
Finished Dec 27 01:32:58 PM PST 23
Peak memory 216860 kb
Host smart-a178b761-5bc4-4d12-8444-33ffe4feb87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621846787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_rx_timeout.621846787
Directory /workspace/23.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/23.spi_device_smoke.1682386583
Short name T1620
Test name
Test status
Simulation time 164096108 ps
CPU time 1.27 seconds
Started Dec 27 01:32:27 PM PST 23
Finished Dec 27 01:32:35 PM PST 23
Peak memory 216680 kb
Host smart-37aa61bd-e52d-4718-b8dd-02f5a82ff922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682386583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_smoke.1682386583
Directory /workspace/23.spi_device_smoke/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1051946297
Short name T90
Test name
Test status
Simulation time 77265831077 ps
CPU time 1275.46 seconds
Started Dec 27 01:33:36 PM PST 23
Finished Dec 27 01:54:52 PM PST 23
Peak memory 336044 kb
Host smart-40d808cb-c503-4905-b7ae-13e71e6fc248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051946297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1051946297
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.764411879
Short name T569
Test name
Test status
Simulation time 1607567578 ps
CPU time 11.1 seconds
Started Dec 27 01:32:37 PM PST 23
Finished Dec 27 01:32:50 PM PST 23
Peak memory 216876 kb
Host smart-4ad8fa25-45ef-47d2-a03c-49e741aaa9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764411879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.764411879
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.256580701
Short name T691
Test name
Test status
Simulation time 451478539 ps
CPU time 1.85 seconds
Started Dec 27 01:32:44 PM PST 23
Finished Dec 27 01:32:47 PM PST 23
Peak memory 216736 kb
Host smart-96aba728-2b03-48d6-b29e-88f108e30ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256580701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.256580701
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.4280564942
Short name T1130
Test name
Test status
Simulation time 301766561 ps
CPU time 0.74 seconds
Started Dec 27 01:32:39 PM PST 23
Finished Dec 27 01:32:42 PM PST 23
Peak memory 206884 kb
Host smart-d872b25a-aa97-4d07-8d11-c4b22e068102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280564942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.4280564942
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_tx_async_fifo_reset.2350705909
Short name T1067
Test name
Test status
Simulation time 48403317 ps
CPU time 0.78 seconds
Started Dec 27 01:32:38 PM PST 23
Finished Dec 27 01:32:40 PM PST 23
Peak memory 208388 kb
Host smart-2f805317-85fe-4fd0-a2eb-a06f42ffd84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350705909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tx_async_fifo_reset.2350705909
Directory /workspace/23.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/23.spi_device_txrx.2806695020
Short name T1482
Test name
Test status
Simulation time 89549039246 ps
CPU time 354.3 seconds
Started Dec 27 01:32:32 PM PST 23
Finished Dec 27 01:38:31 PM PST 23
Peak memory 273864 kb
Host smart-32ca18a9-90eb-4eaf-9e1a-293e54c4a7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806695020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_txrx.2806695020
Directory /workspace/23.spi_device_txrx/latest

Test location /workspace/coverage/default/23.spi_device_upload.2493746230
Short name T1592
Test name
Test status
Simulation time 2661592666 ps
CPU time 10.54 seconds
Started Dec 27 01:32:52 PM PST 23
Finished Dec 27 01:33:06 PM PST 23
Peak memory 237812 kb
Host smart-62231733-b281-49bd-8ed5-d0915bc36878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493746230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2493746230
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_abort.4234225933
Short name T1238
Test name
Test status
Simulation time 205932907 ps
CPU time 0.73 seconds
Started Dec 27 01:33:31 PM PST 23
Finished Dec 27 01:33:37 PM PST 23
Peak memory 206600 kb
Host smart-6126b90d-fd98-4cbf-b623-7e7546874c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234225933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_abort.4234225933
Directory /workspace/24.spi_device_abort/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1679113173
Short name T909
Test name
Test status
Simulation time 12666193 ps
CPU time 0.75 seconds
Started Dec 27 01:33:48 PM PST 23
Finished Dec 27 01:33:50 PM PST 23
Peak memory 206408 kb
Host smart-8c70c706-b57e-435e-a039-21d9fa16a31b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679113173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1679113173
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_bit_transfer.2713029067
Short name T1348
Test name
Test status
Simulation time 148883949 ps
CPU time 2.72 seconds
Started Dec 27 01:33:34 PM PST 23
Finished Dec 27 01:33:38 PM PST 23
Peak memory 216820 kb
Host smart-f0375b89-18cb-419e-b922-d022cb6ceeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713029067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_bit_transfer.2713029067
Directory /workspace/24.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/24.spi_device_byte_transfer.3264183779
Short name T528
Test name
Test status
Simulation time 519788607 ps
CPU time 3.56 seconds
Started Dec 27 01:33:17 PM PST 23
Finished Dec 27 01:33:22 PM PST 23
Peak memory 216720 kb
Host smart-2f9f1f22-7e31-4783-aa79-2524e55537cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264183779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_byte_transfer.3264183779
Directory /workspace/24.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.4014343170
Short name T1047
Test name
Test status
Simulation time 130301125 ps
CPU time 3.63 seconds
Started Dec 27 01:33:17 PM PST 23
Finished Dec 27 01:33:22 PM PST 23
Peak memory 219528 kb
Host smart-232df9c6-523f-484c-a985-4383fb2ba4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014343170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.4014343170
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3467170600
Short name T498
Test name
Test status
Simulation time 24215267 ps
CPU time 0.82 seconds
Started Dec 27 01:33:20 PM PST 23
Finished Dec 27 01:33:22 PM PST 23
Peak memory 207512 kb
Host smart-93df031c-2d00-4145-93f2-a2ddd04f8482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467170600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3467170600
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_dummy_item_extra_dly.1987899796
Short name T1626
Test name
Test status
Simulation time 52843097232 ps
CPU time 200.9 seconds
Started Dec 27 01:33:18 PM PST 23
Finished Dec 27 01:36:40 PM PST 23
Peak memory 288000 kb
Host smart-6835e1ad-8710-4de2-92fb-1811fd7ab5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987899796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_dummy_item_extra_dly.1987899796
Directory /workspace/24.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/24.spi_device_extreme_fifo_size.1786372492
Short name T685
Test name
Test status
Simulation time 102659393593 ps
CPU time 1500.57 seconds
Started Dec 27 01:33:24 PM PST 23
Finished Dec 27 01:58:26 PM PST 23
Peak memory 219188 kb
Host smart-0ac44d64-34a4-49d9-a09b-d2901c363fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786372492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_extreme_fifo_size.1786372492
Directory /workspace/24.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/24.spi_device_fifo_full.1751637444
Short name T1107
Test name
Test status
Simulation time 294422629331 ps
CPU time 261.61 seconds
Started Dec 27 01:33:22 PM PST 23
Finished Dec 27 01:37:46 PM PST 23
Peak memory 265772 kb
Host smart-545089bc-576d-4e23-88be-df5f1e0b6e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751637444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_fifo_full.1751637444
Directory /workspace/24.spi_device_fifo_full/latest

Test location /workspace/coverage/default/24.spi_device_fifo_underflow_overflow.3812332787
Short name T1050
Test name
Test status
Simulation time 51796887305 ps
CPU time 435.64 seconds
Started Dec 27 01:33:23 PM PST 23
Finished Dec 27 01:40:40 PM PST 23
Peak memory 389100 kb
Host smart-9aef109c-c7f6-4213-a216-8c77d160b53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812332787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_fifo_underflow_overf
low.3812332787
Directory /workspace/24.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1407704206
Short name T39
Test name
Test status
Simulation time 156801918973 ps
CPU time 364.92 seconds
Started Dec 27 01:33:24 PM PST 23
Finished Dec 27 01:39:29 PM PST 23
Peak memory 257796 kb
Host smart-118aeea1-c9e0-4bad-bbb9-f7a3c7e1ca0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407704206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1407704206
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1675411477
Short name T732
Test name
Test status
Simulation time 16131633878 ps
CPU time 55.44 seconds
Started Dec 27 01:33:37 PM PST 23
Finished Dec 27 01:34:34 PM PST 23
Peak memory 250808 kb
Host smart-a0eb6f98-c091-4271-b3cd-74256d85180e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675411477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1675411477
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3071179987
Short name T609
Test name
Test status
Simulation time 236967911678 ps
CPU time 424.01 seconds
Started Dec 27 01:33:44 PM PST 23
Finished Dec 27 01:40:49 PM PST 23
Peak memory 255828 kb
Host smart-361c0b30-af1e-4d95-97a6-747905abcbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071179987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3071179987
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.4248225144
Short name T1498
Test name
Test status
Simulation time 14851558248 ps
CPU time 34.25 seconds
Started Dec 27 01:33:21 PM PST 23
Finished Dec 27 01:33:57 PM PST 23
Peak memory 256692 kb
Host smart-47129091-6716-405c-a566-36d3b9b761a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248225144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.4248225144
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.875611975
Short name T240
Test name
Test status
Simulation time 15374762204 ps
CPU time 13.11 seconds
Started Dec 27 01:33:17 PM PST 23
Finished Dec 27 01:33:32 PM PST 23
Peak memory 225112 kb
Host smart-124a735c-3637-47fd-a624-350e08f09a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875611975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.875611975
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_intr.380256978
Short name T487
Test name
Test status
Simulation time 8437679347 ps
CPU time 9.76 seconds
Started Dec 27 01:32:58 PM PST 23
Finished Dec 27 01:33:08 PM PST 23
Peak memory 217900 kb
Host smart-d02d7cfa-eadb-41b0-854b-7596a21231bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380256978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intr.380256978
Directory /workspace/24.spi_device_intr/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2059156406
Short name T1688
Test name
Test status
Simulation time 21366410657 ps
CPU time 24.3 seconds
Started Dec 27 01:33:59 PM PST 23
Finished Dec 27 01:34:24 PM PST 23
Peak memory 253432 kb
Host smart-cd8a7767-0151-4d77-8e2c-fb1388d72522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059156406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2059156406
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3932470919
Short name T1639
Test name
Test status
Simulation time 15713097004 ps
CPU time 42.3 seconds
Started Dec 27 01:33:16 PM PST 23
Finished Dec 27 01:34:01 PM PST 23
Peak memory 257084 kb
Host smart-15db58a1-f88f-4933-9bf0-17803dd0998c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932470919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3932470919
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2121209991
Short name T623
Test name
Test status
Simulation time 217090008 ps
CPU time 2.73 seconds
Started Dec 27 01:33:32 PM PST 23
Finished Dec 27 01:33:36 PM PST 23
Peak memory 224980 kb
Host smart-43397a33-d52a-4d2f-b836-76ec1541d41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121209991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2121209991
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_perf.493141970
Short name T1172
Test name
Test status
Simulation time 6769146989 ps
CPU time 177.6 seconds
Started Dec 27 01:32:58 PM PST 23
Finished Dec 27 01:35:56 PM PST 23
Peak memory 282528 kb
Host smart-6fdc1db2-782c-438f-b45f-2c91628e19ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493141970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_perf.493141970
Directory /workspace/24.spi_device_perf/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2824032954
Short name T727
Test name
Test status
Simulation time 176284256 ps
CPU time 3.64 seconds
Started Dec 27 01:34:07 PM PST 23
Finished Dec 27 01:34:12 PM PST 23
Peak memory 220852 kb
Host smart-28d3b5bd-80be-4681-82de-d12f0da44001
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2824032954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2824032954
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_rx_async_fifo_reset.3281007986
Short name T593
Test name
Test status
Simulation time 34445503 ps
CPU time 0.91 seconds
Started Dec 27 01:33:54 PM PST 23
Finished Dec 27 01:33:56 PM PST 23
Peak memory 208512 kb
Host smart-9657280b-b9bb-45b7-9203-59a308c5cc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281007986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_rx_async_fifo_reset.3281007986
Directory /workspace/24.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/24.spi_device_smoke.4045335015
Short name T1038
Test name
Test status
Simulation time 134289516 ps
CPU time 1.07 seconds
Started Dec 27 01:33:00 PM PST 23
Finished Dec 27 01:33:02 PM PST 23
Peak memory 208316 kb
Host smart-1f3719e7-bd62-40a6-8c80-7939369c3ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045335015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_smoke.4045335015
Directory /workspace/24.spi_device_smoke/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1797498312
Short name T1325
Test name
Test status
Simulation time 90931477118 ps
CPU time 540.26 seconds
Started Dec 27 01:33:34 PM PST 23
Finished Dec 27 01:42:35 PM PST 23
Peak memory 282620 kb
Host smart-2a255a60-1302-4a92-8626-3b2ccc64a690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797498312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1797498312
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3165190660
Short name T349
Test name
Test status
Simulation time 2545878437 ps
CPU time 30.19 seconds
Started Dec 27 01:33:55 PM PST 23
Finished Dec 27 01:34:26 PM PST 23
Peak memory 217408 kb
Host smart-bbd252c0-3a98-4157-acf5-97701f5d8faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165190660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3165190660
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1434864114
Short name T1517
Test name
Test status
Simulation time 982781915 ps
CPU time 2.35 seconds
Started Dec 27 01:33:15 PM PST 23
Finished Dec 27 01:33:18 PM PST 23
Peak memory 216548 kb
Host smart-9143b4c3-c8b1-41c0-8673-fa6e005c0f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434864114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1434864114
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3748102686
Short name T831
Test name
Test status
Simulation time 1183828615 ps
CPU time 10.6 seconds
Started Dec 27 01:33:22 PM PST 23
Finished Dec 27 01:33:34 PM PST 23
Peak memory 216816 kb
Host smart-7f802da5-45cd-42ae-99ca-05880632e5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748102686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3748102686
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.144013337
Short name T773
Test name
Test status
Simulation time 73034497 ps
CPU time 0.82 seconds
Started Dec 27 01:34:07 PM PST 23
Finished Dec 27 01:34:09 PM PST 23
Peak memory 206844 kb
Host smart-80d4210c-71f5-4725-9813-7f2b64ffccac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144013337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.144013337
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_tx_async_fifo_reset.188127292
Short name T157
Test name
Test status
Simulation time 43367893 ps
CPU time 0.75 seconds
Started Dec 27 01:33:52 PM PST 23
Finished Dec 27 01:33:53 PM PST 23
Peak memory 208432 kb
Host smart-0deb1beb-00ca-462f-b92f-448383df5548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188127292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tx_async_fifo_reset.188127292
Directory /workspace/24.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/24.spi_device_txrx.4119790054
Short name T481
Test name
Test status
Simulation time 29804042527 ps
CPU time 196.59 seconds
Started Dec 27 01:33:29 PM PST 23
Finished Dec 27 01:36:47 PM PST 23
Peak memory 277072 kb
Host smart-4000cfa4-d19b-4755-adb1-6c16f3454c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119790054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_txrx.4119790054
Directory /workspace/24.spi_device_txrx/latest

Test location /workspace/coverage/default/24.spi_device_upload.3703015969
Short name T917
Test name
Test status
Simulation time 439291811 ps
CPU time 3.63 seconds
Started Dec 27 01:33:48 PM PST 23
Finished Dec 27 01:33:53 PM PST 23
Peak memory 218204 kb
Host smart-7c83dd8b-e495-4615-b20e-84ef2472c4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703015969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3703015969
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_abort.968100235
Short name T92
Test name
Test status
Simulation time 38405765 ps
CPU time 0.77 seconds
Started Dec 27 01:32:54 PM PST 23
Finished Dec 27 01:32:58 PM PST 23
Peak memory 206672 kb
Host smart-e6978730-49e9-429b-b22f-681b88789f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968100235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_abort.968100235
Directory /workspace/25.spi_device_abort/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3330168313
Short name T979
Test name
Test status
Simulation time 18488594 ps
CPU time 0.71 seconds
Started Dec 27 01:32:51 PM PST 23
Finished Dec 27 01:32:54 PM PST 23
Peak memory 206476 kb
Host smart-42160751-5e83-451d-b84c-5a8e8d79a35d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330168313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3330168313
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_bit_transfer.798881700
Short name T779
Test name
Test status
Simulation time 901218274 ps
CPU time 2.45 seconds
Started Dec 27 01:32:52 PM PST 23
Finished Dec 27 01:33:01 PM PST 23
Peak memory 216908 kb
Host smart-8d68a062-6bb1-48d2-b85f-262b30fa815c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798881700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_bit_transfer.798881700
Directory /workspace/25.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/25.spi_device_byte_transfer.1124537045
Short name T41
Test name
Test status
Simulation time 181137249 ps
CPU time 2.4 seconds
Started Dec 27 01:32:47 PM PST 23
Finished Dec 27 01:32:54 PM PST 23
Peak memory 216744 kb
Host smart-c0adece0-7f7d-4f57-81fc-4959453a8b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124537045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_byte_transfer.1124537045
Directory /workspace/25.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1785087850
Short name T699
Test name
Test status
Simulation time 111530163 ps
CPU time 3.32 seconds
Started Dec 27 01:32:53 PM PST 23
Finished Dec 27 01:33:00 PM PST 23
Peak memory 234576 kb
Host smart-bf2a4c63-a7dc-4bc8-94a2-1dc36adf32e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785087850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1785087850
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2354464206
Short name T575
Test name
Test status
Simulation time 15472453 ps
CPU time 0.81 seconds
Started Dec 27 01:34:02 PM PST 23
Finished Dec 27 01:34:04 PM PST 23
Peak memory 207636 kb
Host smart-805ca8b2-ae7d-4320-8415-36aa823e5586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354464206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2354464206
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_dummy_item_extra_dly.1119182514
Short name T1054
Test name
Test status
Simulation time 7533778893 ps
CPU time 93.08 seconds
Started Dec 27 01:34:03 PM PST 23
Finished Dec 27 01:35:37 PM PST 23
Peak memory 241152 kb
Host smart-6edbf1ce-c488-47ee-9674-3c2fb3d1fb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119182514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_dummy_item_extra_dly.1119182514
Directory /workspace/25.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/25.spi_device_extreme_fifo_size.330741108
Short name T1709
Test name
Test status
Simulation time 171825936904 ps
CPU time 477.24 seconds
Started Dec 27 01:33:38 PM PST 23
Finished Dec 27 01:41:37 PM PST 23
Peak memory 216956 kb
Host smart-219b26e6-c248-4245-82ff-99a3b1314dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330741108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_extreme_fifo_size.330741108
Directory /workspace/25.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/25.spi_device_fifo_full.2766572259
Short name T608
Test name
Test status
Simulation time 285867141739 ps
CPU time 1013.11 seconds
Started Dec 27 01:33:44 PM PST 23
Finished Dec 27 01:50:38 PM PST 23
Peak memory 315372 kb
Host smart-25cd6300-cd72-4cc5-9d36-09c681c434cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766572259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_fifo_full.2766572259
Directory /workspace/25.spi_device_fifo_full/latest

Test location /workspace/coverage/default/25.spi_device_fifo_underflow_overflow.504110798
Short name T1065
Test name
Test status
Simulation time 17756401450 ps
CPU time 201.31 seconds
Started Dec 27 01:33:39 PM PST 23
Finished Dec 27 01:37:02 PM PST 23
Peak memory 341104 kb
Host smart-15b664e3-f198-431d-9839-e0db671bf986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504110798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_fifo_underflow_overfl
ow.504110798
Directory /workspace/25.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3462501289
Short name T1036
Test name
Test status
Simulation time 22805620254 ps
CPU time 138.88 seconds
Started Dec 27 01:33:20 PM PST 23
Finished Dec 27 01:35:40 PM PST 23
Peak memory 254156 kb
Host smart-8dc061dc-176a-4e9a-adad-a8ec218e6ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462501289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3462501289
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.402334683
Short name T1173
Test name
Test status
Simulation time 924767427 ps
CPU time 13.45 seconds
Started Dec 27 01:32:51 PM PST 23
Finished Dec 27 01:33:07 PM PST 23
Peak memory 249512 kb
Host smart-176f7eeb-a237-42c7-99fe-18aa7ab80666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402334683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.402334683
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2131966975
Short name T226
Test name
Test status
Simulation time 979514084 ps
CPU time 4.76 seconds
Started Dec 27 01:33:13 PM PST 23
Finished Dec 27 01:33:18 PM PST 23
Peak memory 220292 kb
Host smart-dc394d88-2f4e-49f9-bd94-7d100d297202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131966975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2131966975
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_intr.2645535874
Short name T710
Test name
Test status
Simulation time 6597813839 ps
CPU time 37.09 seconds
Started Dec 27 01:33:51 PM PST 23
Finished Dec 27 01:34:29 PM PST 23
Peak memory 240760 kb
Host smart-dbad2927-8e13-4772-abdc-095f006e3aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645535874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intr.2645535874
Directory /workspace/25.spi_device_intr/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2046037648
Short name T250
Test name
Test status
Simulation time 11883790751 ps
CPU time 18.43 seconds
Started Dec 27 01:32:59 PM PST 23
Finished Dec 27 01:33:17 PM PST 23
Peak memory 218988 kb
Host smart-db03b580-005d-4698-868c-98ee3500a34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046037648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2046037648
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.940892437
Short name T1654
Test name
Test status
Simulation time 158639328 ps
CPU time 3.71 seconds
Started Dec 27 01:32:58 PM PST 23
Finished Dec 27 01:33:02 PM PST 23
Peak memory 241256 kb
Host smart-c5cae1bd-f63c-423b-8477-43affbc9bc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940892437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.940892437
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3472088953
Short name T1305
Test name
Test status
Simulation time 1210532135 ps
CPU time 5.26 seconds
Started Dec 27 01:32:57 PM PST 23
Finished Dec 27 01:33:04 PM PST 23
Peak memory 218228 kb
Host smart-9fcc3fd1-c53e-4e3b-9e17-c509102f76db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472088953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3472088953
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_perf.166625895
Short name T1153
Test name
Test status
Simulation time 39935198159 ps
CPU time 1216.01 seconds
Started Dec 27 01:33:49 PM PST 23
Finished Dec 27 01:54:06 PM PST 23
Peak memory 269816 kb
Host smart-d7cbecad-460c-4b71-ac78-1e2eda7efa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166625895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_perf.166625895
Directory /workspace/25.spi_device_perf/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3750565396
Short name T1470
Test name
Test status
Simulation time 34652214838 ps
CPU time 7.7 seconds
Started Dec 27 01:32:53 PM PST 23
Finished Dec 27 01:33:04 PM PST 23
Peak memory 220824 kb
Host smart-fb456c3f-764e-4d8d-9e76-00735f3d5116
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3750565396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3750565396
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_rx_async_fifo_reset.2904855551
Short name T882
Test name
Test status
Simulation time 386586579 ps
CPU time 0.92 seconds
Started Dec 27 01:32:52 PM PST 23
Finished Dec 27 01:32:54 PM PST 23
Peak memory 208448 kb
Host smart-25f4a01d-eba6-4a0f-97c0-d44de6e25d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904855551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_rx_async_fifo_reset.2904855551
Directory /workspace/25.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/25.spi_device_rx_timeout.3281354999
Short name T20
Test name
Test status
Simulation time 2305949026 ps
CPU time 5.78 seconds
Started Dec 27 01:33:50 PM PST 23
Finished Dec 27 01:33:57 PM PST 23
Peak memory 216864 kb
Host smart-eeb4fea9-9aaa-4ebf-b3df-370c1f5ad4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281354999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_rx_timeout.3281354999
Directory /workspace/25.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/25.spi_device_smoke.2385789927
Short name T1344
Test name
Test status
Simulation time 158034817 ps
CPU time 1.09 seconds
Started Dec 27 01:33:21 PM PST 23
Finished Dec 27 01:33:23 PM PST 23
Peak memory 216528 kb
Host smart-2358c665-eab8-41cb-8279-0c1e4c547587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385789927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_smoke.2385789927
Directory /workspace/25.spi_device_smoke/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.4117303857
Short name T668
Test name
Test status
Simulation time 2892520597 ps
CPU time 6.06 seconds
Started Dec 27 01:32:51 PM PST 23
Finished Dec 27 01:32:59 PM PST 23
Peak memory 218432 kb
Host smart-92eedae3-9328-4c37-af88-6c8ed7fc5860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117303857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.4117303857
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2636842429
Short name T592
Test name
Test status
Simulation time 1623271891 ps
CPU time 3.41 seconds
Started Dec 27 01:32:55 PM PST 23
Finished Dec 27 01:33:00 PM PST 23
Peak memory 216792 kb
Host smart-e6c30479-26a3-4766-a827-9260d46c5d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636842429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2636842429
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.432882073
Short name T360
Test name
Test status
Simulation time 435133896 ps
CPU time 3.62 seconds
Started Dec 27 01:32:52 PM PST 23
Finished Dec 27 01:32:58 PM PST 23
Peak memory 216660 kb
Host smart-f3d86535-4705-45f4-bde5-e35bdc407294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432882073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.432882073
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1448135935
Short name T122
Test name
Test status
Simulation time 32937510 ps
CPU time 0.83 seconds
Started Dec 27 01:32:53 PM PST 23
Finished Dec 27 01:32:57 PM PST 23
Peak memory 206924 kb
Host smart-051487b4-2604-41b9-870c-7e794ce96203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448135935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1448135935
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_tx_async_fifo_reset.2625511669
Short name T1531
Test name
Test status
Simulation time 116067728 ps
CPU time 0.78 seconds
Started Dec 27 01:32:50 PM PST 23
Finished Dec 27 01:32:54 PM PST 23
Peak memory 208456 kb
Host smart-19a142aa-44e4-4507-9b7c-062e712e3204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625511669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tx_async_fifo_reset.2625511669
Directory /workspace/25.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/25.spi_device_txrx.3466602092
Short name T536
Test name
Test status
Simulation time 211524439641 ps
CPU time 199.78 seconds
Started Dec 27 01:33:44 PM PST 23
Finished Dec 27 01:37:05 PM PST 23
Peak memory 265116 kb
Host smart-97f9327a-439b-41ab-a225-bab30011768f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466602092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_txrx.3466602092
Directory /workspace/25.spi_device_txrx/latest

Test location /workspace/coverage/default/25.spi_device_upload.1715934553
Short name T306
Test name
Test status
Simulation time 1955624097 ps
CPU time 7.04 seconds
Started Dec 27 01:33:04 PM PST 23
Finished Dec 27 01:33:15 PM PST 23
Peak memory 236392 kb
Host smart-fce4206a-2d9c-4e64-989d-d50b55bb53d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715934553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1715934553
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_abort.2764892715
Short name T986
Test name
Test status
Simulation time 15909901 ps
CPU time 0.76 seconds
Started Dec 27 01:33:20 PM PST 23
Finished Dec 27 01:33:22 PM PST 23
Peak memory 206608 kb
Host smart-8b007bf6-e445-4a36-8ad8-b8a6a86e4d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764892715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_abort.2764892715
Directory /workspace/26.spi_device_abort/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1495288718
Short name T767
Test name
Test status
Simulation time 43873724 ps
CPU time 0.7 seconds
Started Dec 27 01:33:54 PM PST 23
Finished Dec 27 01:33:56 PM PST 23
Peak memory 206484 kb
Host smart-3cdb2307-94c9-4c5b-9881-e570e90cb18d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495288718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1495288718
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_bit_transfer.2507351850
Short name T503
Test name
Test status
Simulation time 266779503 ps
CPU time 3.01 seconds
Started Dec 27 01:32:51 PM PST 23
Finished Dec 27 01:32:56 PM PST 23
Peak memory 216844 kb
Host smart-eef2d1cb-ea8a-4426-9bdc-f2b0d9f8603a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507351850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_bit_transfer.2507351850
Directory /workspace/26.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/26.spi_device_byte_transfer.2703334189
Short name T704
Test name
Test status
Simulation time 1936869104 ps
CPU time 2.96 seconds
Started Dec 27 01:32:47 PM PST 23
Finished Dec 27 01:32:55 PM PST 23
Peak memory 216800 kb
Host smart-a56f1e9e-bca8-4fd1-9fce-77801cfb9350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703334189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_byte_transfer.2703334189
Directory /workspace/26.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3709174973
Short name T1388
Test name
Test status
Simulation time 788669378 ps
CPU time 6.34 seconds
Started Dec 27 01:32:57 PM PST 23
Finished Dec 27 01:33:04 PM PST 23
Peak memory 239104 kb
Host smart-d8ea9f83-fc1b-4d21-9c07-1022742a03ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709174973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3709174973
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3427305884
Short name T499
Test name
Test status
Simulation time 15808005 ps
CPU time 0.74 seconds
Started Dec 27 01:32:54 PM PST 23
Finished Dec 27 01:32:58 PM PST 23
Peak memory 206492 kb
Host smart-dd5731b8-f61a-4dcf-9e20-a6ed36c3c003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427305884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3427305884
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_dummy_item_extra_dly.2380125747
Short name T1233
Test name
Test status
Simulation time 31275731516 ps
CPU time 262.15 seconds
Started Dec 27 01:33:16 PM PST 23
Finished Dec 27 01:37:38 PM PST 23
Peak memory 257244 kb
Host smart-2dc4e4be-c023-4a3c-b719-138ff67e7abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380125747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_dummy_item_extra_dly.2380125747
Directory /workspace/26.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/26.spi_device_extreme_fifo_size.3088483073
Short name T922
Test name
Test status
Simulation time 217679574865 ps
CPU time 877.07 seconds
Started Dec 27 01:32:57 PM PST 23
Finished Dec 27 01:47:35 PM PST 23
Peak memory 225156 kb
Host smart-ae82ddf3-2c1f-45ab-a6f3-8bb5b8ab1635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088483073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_extreme_fifo_size.3088483073
Directory /workspace/26.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/26.spi_device_fifo_full.1174380592
Short name T577
Test name
Test status
Simulation time 13301628889 ps
CPU time 767.76 seconds
Started Dec 27 01:33:22 PM PST 23
Finished Dec 27 01:46:12 PM PST 23
Peak memory 309120 kb
Host smart-25eeb4b7-e5eb-4894-9492-2fa86f77d908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174380592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_fifo_full.1174380592
Directory /workspace/26.spi_device_fifo_full/latest

Test location /workspace/coverage/default/26.spi_device_fifo_underflow_overflow.3538331682
Short name T53
Test name
Test status
Simulation time 34804854351 ps
CPU time 132.71 seconds
Started Dec 27 01:33:19 PM PST 23
Finished Dec 27 01:35:33 PM PST 23
Peak memory 274092 kb
Host smart-72ee488a-776a-4a21-ae89-a24de2deea09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538331682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_fifo_underflow_overf
low.3538331682
Directory /workspace/26.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1788809456
Short name T774
Test name
Test status
Simulation time 44143373696 ps
CPU time 86.21 seconds
Started Dec 27 01:33:29 PM PST 23
Finished Dec 27 01:34:56 PM PST 23
Peak memory 250012 kb
Host smart-b83bc928-bbc5-4447-97ee-a02257af1ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788809456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1788809456
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3370980999
Short name T1351
Test name
Test status
Simulation time 7842983215 ps
CPU time 98.62 seconds
Started Dec 27 01:33:16 PM PST 23
Finished Dec 27 01:34:57 PM PST 23
Peak memory 273772 kb
Host smart-43fb28c2-0170-40db-96c0-f2ee3249888a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370980999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3370980999
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.549917752
Short name T1055
Test name
Test status
Simulation time 70770894754 ps
CPU time 36.64 seconds
Started Dec 27 01:33:31 PM PST 23
Finished Dec 27 01:34:09 PM PST 23
Peak memory 257804 kb
Host smart-621a07a7-6ac5-4cb9-a1f0-5b89a1c61a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549917752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.549917752
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3845361902
Short name T1312
Test name
Test status
Simulation time 529394937 ps
CPU time 3.49 seconds
Started Dec 27 01:32:50 PM PST 23
Finished Dec 27 01:32:57 PM PST 23
Peak memory 218576 kb
Host smart-64fa9856-fdcd-4a8c-a876-adbcbfeac3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845361902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3845361902
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_intr.2148005817
Short name T1161
Test name
Test status
Simulation time 11195578307 ps
CPU time 18.07 seconds
Started Dec 27 01:32:51 PM PST 23
Finished Dec 27 01:33:11 PM PST 23
Peak memory 220076 kb
Host smart-37710874-3585-4db8-961f-a412da1868c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148005817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intr.2148005817
Directory /workspace/26.spi_device_intr/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2765975005
Short name T1513
Test name
Test status
Simulation time 11564450973 ps
CPU time 19.97 seconds
Started Dec 27 01:33:15 PM PST 23
Finished Dec 27 01:33:36 PM PST 23
Peak memory 241304 kb
Host smart-c441840e-8476-4449-8219-662b90e31ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765975005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2765975005
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3972864916
Short name T1207
Test name
Test status
Simulation time 1265145500 ps
CPU time 9.25 seconds
Started Dec 27 01:33:37 PM PST 23
Finished Dec 27 01:33:47 PM PST 23
Peak memory 228652 kb
Host smart-834c8ef7-0ca7-4b3e-adba-06c05ed54193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972864916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3972864916
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.662064983
Short name T644
Test name
Test status
Simulation time 6479021654 ps
CPU time 17.67 seconds
Started Dec 27 01:33:15 PM PST 23
Finished Dec 27 01:33:34 PM PST 23
Peak memory 229284 kb
Host smart-3108e069-0578-43a2-8538-8c0d55210bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662064983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.662064983
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_perf.3162041645
Short name T118
Test name
Test status
Simulation time 93133138577 ps
CPU time 588.21 seconds
Started Dec 27 01:33:29 PM PST 23
Finished Dec 27 01:43:17 PM PST 23
Peak memory 252836 kb
Host smart-27d255fb-773e-4273-8f4b-adf6a8033f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162041645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_perf.3162041645
Directory /workspace/26.spi_device_perf/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.372963085
Short name T189
Test name
Test status
Simulation time 1464872276 ps
CPU time 4.49 seconds
Started Dec 27 01:33:19 PM PST 23
Finished Dec 27 01:33:25 PM PST 23
Peak memory 235772 kb
Host smart-2bd7ea92-a37d-497a-a418-56442bb37e17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=372963085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.372963085
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_rx_async_fifo_reset.3534647175
Short name T1585
Test name
Test status
Simulation time 18295062 ps
CPU time 0.84 seconds
Started Dec 27 01:33:24 PM PST 23
Finished Dec 27 01:33:25 PM PST 23
Peak memory 208392 kb
Host smart-947b4c90-664e-4f48-b82a-c9c8abf07489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534647175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_rx_async_fifo_reset.3534647175
Directory /workspace/26.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/26.spi_device_rx_timeout.2190682404
Short name T1567
Test name
Test status
Simulation time 414602969 ps
CPU time 4.69 seconds
Started Dec 27 01:33:15 PM PST 23
Finished Dec 27 01:33:20 PM PST 23
Peak memory 216864 kb
Host smart-4d394b49-8851-4365-b908-784f7ecdd118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190682404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_rx_timeout.2190682404
Directory /workspace/26.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/26.spi_device_smoke.2193556205
Short name T1670
Test name
Test status
Simulation time 13301386 ps
CPU time 0.89 seconds
Started Dec 27 01:32:54 PM PST 23
Finished Dec 27 01:32:58 PM PST 23
Peak memory 207776 kb
Host smart-b3f7827a-7437-4371-bf06-c96e340d8577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193556205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_smoke.2193556205
Directory /workspace/26.spi_device_smoke/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.304983976
Short name T1117
Test name
Test status
Simulation time 1855958101 ps
CPU time 23.11 seconds
Started Dec 27 01:33:31 PM PST 23
Finished Dec 27 01:33:55 PM PST 23
Peak memory 216844 kb
Host smart-5798f90a-66da-46d2-bd6f-ecba6babf49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304983976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.304983976
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.358874379
Short name T1407
Test name
Test status
Simulation time 216321449 ps
CPU time 2.14 seconds
Started Dec 27 01:33:15 PM PST 23
Finished Dec 27 01:33:18 PM PST 23
Peak memory 216820 kb
Host smart-f5f283da-ea84-4cef-9c01-41d889478836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358874379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.358874379
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1542493364
Short name T984
Test name
Test status
Simulation time 85891164 ps
CPU time 1.39 seconds
Started Dec 27 01:33:35 PM PST 23
Finished Dec 27 01:33:37 PM PST 23
Peak memory 216764 kb
Host smart-46325332-e9e7-41d5-99c7-2b2a6e10ace0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542493364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1542493364
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1034166707
Short name T998
Test name
Test status
Simulation time 476173152 ps
CPU time 1.13 seconds
Started Dec 27 01:33:20 PM PST 23
Finished Dec 27 01:33:23 PM PST 23
Peak memory 208036 kb
Host smart-fe18868d-c1cb-4421-994c-c300c530b1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034166707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1034166707
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_tx_async_fifo_reset.3615062100
Short name T1243
Test name
Test status
Simulation time 53459833 ps
CPU time 0.79 seconds
Started Dec 27 01:32:53 PM PST 23
Finished Dec 27 01:32:57 PM PST 23
Peak memory 208348 kb
Host smart-7e7a2949-377a-40e6-9c2b-9a26410800e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615062100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tx_async_fifo_reset.3615062100
Directory /workspace/26.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/26.spi_device_txrx.398071484
Short name T281
Test name
Test status
Simulation time 38292976230 ps
CPU time 294.71 seconds
Started Dec 27 01:33:39 PM PST 23
Finished Dec 27 01:38:35 PM PST 23
Peak memory 277960 kb
Host smart-c133924a-47f5-4b4a-8b41-c65c77d81a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398071484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_txrx.398071484
Directory /workspace/26.spi_device_txrx/latest

Test location /workspace/coverage/default/26.spi_device_upload.838592549
Short name T1002
Test name
Test status
Simulation time 6383800353 ps
CPU time 8.55 seconds
Started Dec 27 01:33:39 PM PST 23
Finished Dec 27 01:33:49 PM PST 23
Peak memory 237592 kb
Host smart-2fd82de8-d38f-4077-b50b-9ec0157f581a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838592549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.838592549
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_abort.1308894811
Short name T1544
Test name
Test status
Simulation time 13669320 ps
CPU time 0.75 seconds
Started Dec 27 01:33:25 PM PST 23
Finished Dec 27 01:33:28 PM PST 23
Peak memory 206636 kb
Host smart-095d03da-592c-4d8b-bb40-8019f921ffb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308894811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_abort.1308894811
Directory /workspace/27.spi_device_abort/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1827224113
Short name T1558
Test name
Test status
Simulation time 10738207 ps
CPU time 0.71 seconds
Started Dec 27 01:33:46 PM PST 23
Finished Dec 27 01:33:47 PM PST 23
Peak memory 206472 kb
Host smart-229de2fa-0bc7-47e4-a575-8adec965eaab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827224113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1827224113
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_bit_transfer.2917584080
Short name T1481
Test name
Test status
Simulation time 177088336 ps
CPU time 2.31 seconds
Started Dec 27 01:33:21 PM PST 23
Finished Dec 27 01:33:25 PM PST 23
Peak memory 216828 kb
Host smart-5f3ba580-b9f2-4bfe-92bd-cf0470fa8de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917584080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_bit_transfer.2917584080
Directory /workspace/27.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/27.spi_device_byte_transfer.2730327984
Short name T988
Test name
Test status
Simulation time 408804379 ps
CPU time 3.04 seconds
Started Dec 27 01:33:24 PM PST 23
Finished Dec 27 01:33:29 PM PST 23
Peak memory 216836 kb
Host smart-8aeaf611-e526-4116-8eef-12228c4e6068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730327984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_byte_transfer.2730327984
Directory /workspace/27.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1731163254
Short name T1134
Test name
Test status
Simulation time 1711743027 ps
CPU time 5.3 seconds
Started Dec 27 01:33:33 PM PST 23
Finished Dec 27 01:33:40 PM PST 23
Peak memory 239520 kb
Host smart-05fa14fe-5a1c-40e6-9808-b8dff058ccc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731163254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1731163254
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1449216135
Short name T1708
Test name
Test status
Simulation time 62196916 ps
CPU time 0.73 seconds
Started Dec 27 01:33:31 PM PST 23
Finished Dec 27 01:33:33 PM PST 23
Peak memory 206536 kb
Host smart-0e34afb3-4b16-43f9-8bf6-4302f27ba5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449216135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1449216135
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_dummy_item_extra_dly.1532871213
Short name T586
Test name
Test status
Simulation time 116263617560 ps
CPU time 286.53 seconds
Started Dec 27 01:33:38 PM PST 23
Finished Dec 27 01:38:26 PM PST 23
Peak memory 268496 kb
Host smart-06ad5541-4ec9-4c30-93fa-7262e59434ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532871213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_dummy_item_extra_dly.1532871213
Directory /workspace/27.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/27.spi_device_extreme_fifo_size.4068732819
Short name T1110
Test name
Test status
Simulation time 71294533148 ps
CPU time 933.97 seconds
Started Dec 27 01:34:00 PM PST 23
Finished Dec 27 01:49:34 PM PST 23
Peak memory 220296 kb
Host smart-3ec19449-5bf1-4c22-a4f1-3c392775f638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068732819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_extreme_fifo_size.4068732819
Directory /workspace/27.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/27.spi_device_fifo_full.616048712
Short name T541
Test name
Test status
Simulation time 103805299630 ps
CPU time 1375.32 seconds
Started Dec 27 01:33:31 PM PST 23
Finished Dec 27 01:56:27 PM PST 23
Peak memory 303816 kb
Host smart-b9bae2b3-5dae-4f9f-8caa-08c1c7535eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616048712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_fifo_full.616048712
Directory /workspace/27.spi_device_fifo_full/latest

Test location /workspace/coverage/default/27.spi_device_fifo_underflow_overflow.2188918681
Short name T770
Test name
Test status
Simulation time 164722070404 ps
CPU time 213.23 seconds
Started Dec 27 01:33:18 PM PST 23
Finished Dec 27 01:36:53 PM PST 23
Peak memory 333040 kb
Host smart-5b8a7705-000e-4fcb-a01b-042543d65639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188918681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_fifo_underflow_overf
low.2188918681
Directory /workspace/27.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1708406108
Short name T339
Test name
Test status
Simulation time 1550163887 ps
CPU time 7.34 seconds
Started Dec 27 01:33:14 PM PST 23
Finished Dec 27 01:33:23 PM PST 23
Peak memory 221052 kb
Host smart-03088078-dc84-4e00-be09-7c31c88f19f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708406108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1708406108
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1888280076
Short name T31
Test name
Test status
Simulation time 10449755358 ps
CPU time 53.74 seconds
Started Dec 27 01:33:45 PM PST 23
Finished Dec 27 01:34:39 PM PST 23
Peak memory 225224 kb
Host smart-0a655355-4301-4d7e-91a7-a723b102f63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888280076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1888280076
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2687355655
Short name T1266
Test name
Test status
Simulation time 281900190199 ps
CPU time 199.61 seconds
Started Dec 27 01:33:22 PM PST 23
Finished Dec 27 01:36:43 PM PST 23
Peak memory 257960 kb
Host smart-2106f8bf-a7fe-4d92-8ce6-39f0a0082b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687355655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2687355655
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3747268920
Short name T348
Test name
Test status
Simulation time 3022623590 ps
CPU time 19.95 seconds
Started Dec 27 01:33:26 PM PST 23
Finished Dec 27 01:33:47 PM PST 23
Peak memory 223908 kb
Host smart-aa4c3934-a904-439a-8c15-36b0c0e1da3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747268920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3747268920
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1381758789
Short name T1276
Test name
Test status
Simulation time 417306871 ps
CPU time 4.34 seconds
Started Dec 27 01:33:51 PM PST 23
Finished Dec 27 01:33:56 PM PST 23
Peak memory 219544 kb
Host smart-bf3c6867-1e11-4d66-b41c-ee8c74ec9945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381758789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1381758789
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_intr.1822061614
Short name T670
Test name
Test status
Simulation time 38043364232 ps
CPU time 81.32 seconds
Started Dec 27 01:33:21 PM PST 23
Finished Dec 27 01:34:44 PM PST 23
Peak memory 233316 kb
Host smart-5ed402d6-3619-4741-b115-1fbe938dfa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822061614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intr.1822061614
Directory /workspace/27.spi_device_intr/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2845655105
Short name T1225
Test name
Test status
Simulation time 11553564567 ps
CPU time 22.03 seconds
Started Dec 27 01:33:28 PM PST 23
Finished Dec 27 01:33:51 PM PST 23
Peak memory 233368 kb
Host smart-9ae2d701-6d66-4882-b133-924f13f58b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845655105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2845655105
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.228094906
Short name T1649
Test name
Test status
Simulation time 828711799 ps
CPU time 4.27 seconds
Started Dec 27 01:33:21 PM PST 23
Finished Dec 27 01:33:27 PM PST 23
Peak memory 218980 kb
Host smart-629f5b4a-292a-4928-bae3-48c72c5853ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228094906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.228094906
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_perf.2942695661
Short name T810
Test name
Test status
Simulation time 18489253489 ps
CPU time 474.28 seconds
Started Dec 27 01:33:32 PM PST 23
Finished Dec 27 01:41:27 PM PST 23
Peak memory 256196 kb
Host smart-d1777a6b-51d2-47dc-a54b-d989f25aa3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942695661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_perf.2942695661
Directory /workspace/27.spi_device_perf/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2065159468
Short name T1549
Test name
Test status
Simulation time 817170123 ps
CPU time 5.14 seconds
Started Dec 27 01:33:18 PM PST 23
Finished Dec 27 01:33:25 PM PST 23
Peak memory 220376 kb
Host smart-97ad113a-4f0c-4312-991c-3ea8cd4b2211
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2065159468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2065159468
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_rx_async_fifo_reset.577139071
Short name T1031
Test name
Test status
Simulation time 62196685 ps
CPU time 0.86 seconds
Started Dec 27 01:33:41 PM PST 23
Finished Dec 27 01:33:43 PM PST 23
Peak memory 208408 kb
Host smart-58939afb-ddc1-49ca-a727-535b1b37b5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577139071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_rx_async_fifo_reset.577139071
Directory /workspace/27.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/27.spi_device_rx_timeout.3352235048
Short name T129
Test name
Test status
Simulation time 1129428338 ps
CPU time 5.27 seconds
Started Dec 27 01:33:17 PM PST 23
Finished Dec 27 01:33:24 PM PST 23
Peak memory 216808 kb
Host smart-a9bd36d7-39b8-4c45-a060-29c1b1a8d098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352235048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_rx_timeout.3352235048
Directory /workspace/27.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/27.spi_device_smoke.2589331461
Short name T1419
Test name
Test status
Simulation time 72926568 ps
CPU time 1.24 seconds
Started Dec 27 01:33:16 PM PST 23
Finished Dec 27 01:33:19 PM PST 23
Peak memory 216632 kb
Host smart-1452b7db-86bd-4f87-8c52-f92a7d4e8934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589331461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_smoke.2589331461
Directory /workspace/27.spi_device_smoke/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2077473588
Short name T155
Test name
Test status
Simulation time 192640976602 ps
CPU time 262.32 seconds
Started Dec 27 01:33:15 PM PST 23
Finished Dec 27 01:37:38 PM PST 23
Peak memory 257920 kb
Host smart-d9ba63df-5ef0-45fb-9869-beab27b27603
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077473588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2077473588
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3185050608
Short name T1105
Test name
Test status
Simulation time 3496584769 ps
CPU time 37.31 seconds
Started Dec 27 01:33:25 PM PST 23
Finished Dec 27 01:34:04 PM PST 23
Peak memory 216784 kb
Host smart-6f1dda09-956b-466c-b449-6adf1eacc1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185050608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3185050608
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.489058463
Short name T1391
Test name
Test status
Simulation time 3030244203 ps
CPU time 9.76 seconds
Started Dec 27 01:33:51 PM PST 23
Finished Dec 27 01:34:01 PM PST 23
Peak memory 216788 kb
Host smart-bc995757-4765-4e68-8b65-8d37c5d26465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489058463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.489058463
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2872612006
Short name T1714
Test name
Test status
Simulation time 149957972 ps
CPU time 2.51 seconds
Started Dec 27 01:33:46 PM PST 23
Finished Dec 27 01:33:49 PM PST 23
Peak memory 208640 kb
Host smart-0adc4684-5b31-45b0-9f4a-dd128ef6c86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872612006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2872612006
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2226262619
Short name T1230
Test name
Test status
Simulation time 193802546 ps
CPU time 1.07 seconds
Started Dec 27 01:33:29 PM PST 23
Finished Dec 27 01:33:31 PM PST 23
Peak memory 208040 kb
Host smart-1afddd80-09c1-465c-ab83-3227aa587a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226262619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2226262619
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_tx_async_fifo_reset.1739709862
Short name T1293
Test name
Test status
Simulation time 60992190 ps
CPU time 0.77 seconds
Started Dec 27 01:33:17 PM PST 23
Finished Dec 27 01:33:19 PM PST 23
Peak memory 208384 kb
Host smart-8965f5df-9e86-470f-80d2-27c71aa24dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739709862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tx_async_fifo_reset.1739709862
Directory /workspace/27.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/27.spi_device_txrx.358894521
Short name T1485
Test name
Test status
Simulation time 20482720789 ps
CPU time 218.63 seconds
Started Dec 27 01:33:19 PM PST 23
Finished Dec 27 01:36:59 PM PST 23
Peak memory 249772 kb
Host smart-c905a37f-6e99-4412-830f-d80f0f769e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358894521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_txrx.358894521
Directory /workspace/27.spi_device_txrx/latest

Test location /workspace/coverage/default/27.spi_device_upload.2261054323
Short name T1158
Test name
Test status
Simulation time 5936221864 ps
CPU time 7.5 seconds
Started Dec 27 01:33:20 PM PST 23
Finished Dec 27 01:33:29 PM PST 23
Peak memory 219996 kb
Host smart-1d2e298e-9ec8-424c-9c39-889e7c348331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261054323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2261054323
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_abort.1092589089
Short name T1143
Test name
Test status
Simulation time 14824682 ps
CPU time 0.8 seconds
Started Dec 27 01:33:41 PM PST 23
Finished Dec 27 01:33:42 PM PST 23
Peak memory 206612 kb
Host smart-8d9b18a0-5eab-437d-afe2-0ed3806a10a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092589089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_abort.1092589089
Directory /workspace/28.spi_device_abort/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.422285207
Short name T518
Test name
Test status
Simulation time 22511282 ps
CPU time 0.69 seconds
Started Dec 27 01:33:20 PM PST 23
Finished Dec 27 01:33:21 PM PST 23
Peak memory 206524 kb
Host smart-7155d4d0-512e-4001-b759-0abd584af1c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422285207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.422285207
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_bit_transfer.2454528710
Short name T514
Test name
Test status
Simulation time 1287031996 ps
CPU time 2.69 seconds
Started Dec 27 01:33:19 PM PST 23
Finished Dec 27 01:33:23 PM PST 23
Peak memory 216788 kb
Host smart-c21b049d-a29b-4918-95be-9c08c140eed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454528710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_bit_transfer.2454528710
Directory /workspace/28.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/28.spi_device_byte_transfer.1287057926
Short name T605
Test name
Test status
Simulation time 189659672 ps
CPU time 2.19 seconds
Started Dec 27 01:33:26 PM PST 23
Finished Dec 27 01:33:30 PM PST 23
Peak memory 216852 kb
Host smart-9ec0d55d-dabb-4294-ae18-01705fb2e1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287057926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_byte_transfer.1287057926
Directory /workspace/28.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2713446940
Short name T1400
Test name
Test status
Simulation time 318200192 ps
CPU time 3.52 seconds
Started Dec 27 01:33:55 PM PST 23
Finished Dec 27 01:33:59 PM PST 23
Peak memory 220588 kb
Host smart-aee3b791-dc65-4815-8817-a413b8a13093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713446940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2713446940
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2982803135
Short name T479
Test name
Test status
Simulation time 17064945 ps
CPU time 0.79 seconds
Started Dec 27 01:33:54 PM PST 23
Finished Dec 27 01:33:55 PM PST 23
Peak memory 206592 kb
Host smart-50f86f2d-87fb-4f01-9caa-2e58f58c0424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982803135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2982803135
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_dummy_item_extra_dly.956054437
Short name T954
Test name
Test status
Simulation time 117784636548 ps
CPU time 372.52 seconds
Started Dec 27 01:33:57 PM PST 23
Finished Dec 27 01:40:11 PM PST 23
Peak memory 289556 kb
Host smart-716311d5-ecf7-4c9f-9204-12ab5ac5b484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956054437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_dummy_item_extra_dly.956054437
Directory /workspace/28.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/28.spi_device_fifo_full.799734882
Short name T906
Test name
Test status
Simulation time 194137475814 ps
CPU time 923.32 seconds
Started Dec 27 01:33:12 PM PST 23
Finished Dec 27 01:48:36 PM PST 23
Peak memory 261112 kb
Host smart-e2af80e7-16e8-40ee-9d04-9b7dbe202a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799734882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_fifo_full.799734882
Directory /workspace/28.spi_device_fifo_full/latest

Test location /workspace/coverage/default/28.spi_device_fifo_underflow_overflow.396751555
Short name T559
Test name
Test status
Simulation time 28183984125 ps
CPU time 255.93 seconds
Started Dec 27 01:33:34 PM PST 23
Finished Dec 27 01:37:51 PM PST 23
Peak memory 400916 kb
Host smart-f4f1cea2-b436-42ba-ad9d-56b81e50f179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396751555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_fifo_underflow_overfl
ow.396751555
Directory /workspace/28.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.673016329
Short name T77
Test name
Test status
Simulation time 37776629679 ps
CPU time 244.67 seconds
Started Dec 27 01:33:23 PM PST 23
Finished Dec 27 01:37:29 PM PST 23
Peak memory 268732 kb
Host smart-7c37bac1-489a-4632-80c6-693a9af2276b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673016329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.673016329
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1315265192
Short name T1033
Test name
Test status
Simulation time 5664683653 ps
CPU time 49.95 seconds
Started Dec 27 01:33:38 PM PST 23
Finished Dec 27 01:34:30 PM PST 23
Peak memory 241564 kb
Host smart-90f0e08d-e689-4036-8cf8-11669576b4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315265192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1315265192
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.417007238
Short name T258
Test name
Test status
Simulation time 314793435 ps
CPU time 11.32 seconds
Started Dec 27 01:33:33 PM PST 23
Finished Dec 27 01:33:46 PM PST 23
Peak memory 247584 kb
Host smart-13fd98c5-e4bc-4753-bddb-fcb583f9594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417007238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.417007238
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3325735588
Short name T1537
Test name
Test status
Simulation time 2995728302 ps
CPU time 6.4 seconds
Started Dec 27 01:33:18 PM PST 23
Finished Dec 27 01:33:25 PM PST 23
Peak memory 241464 kb
Host smart-ffa43995-c22e-445b-a875-946ac57f8803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325735588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3325735588
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_intr.3588283908
Short name T48
Test name
Test status
Simulation time 49787792418 ps
CPU time 63.49 seconds
Started Dec 27 01:33:24 PM PST 23
Finished Dec 27 01:34:29 PM PST 23
Peak memory 241580 kb
Host smart-86d14845-3fe9-453b-b2ad-bb47c4cd600b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588283908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intr.3588283908
Directory /workspace/28.spi_device_intr/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1512255931
Short name T1671
Test name
Test status
Simulation time 3522082821 ps
CPU time 11.6 seconds
Started Dec 27 01:34:09 PM PST 23
Finished Dec 27 01:34:21 PM PST 23
Peak memory 225144 kb
Host smart-a9bcacf0-1a14-492a-b936-9314173dfaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512255931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1512255931
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3064564609
Short name T11
Test name
Test status
Simulation time 11166273001 ps
CPU time 18.29 seconds
Started Dec 27 01:33:22 PM PST 23
Finished Dec 27 01:33:42 PM PST 23
Peak memory 218144 kb
Host smart-fe960fd0-7614-4d9d-b473-993a9103d02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064564609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3064564609
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2998838770
Short name T1253
Test name
Test status
Simulation time 823649752 ps
CPU time 7.05 seconds
Started Dec 27 01:33:18 PM PST 23
Finished Dec 27 01:33:26 PM PST 23
Peak memory 239596 kb
Host smart-3db1294a-3c78-4ed4-b847-ef5724dd710d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998838770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2998838770
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_perf.2731939477
Short name T712
Test name
Test status
Simulation time 81590347169 ps
CPU time 1473.73 seconds
Started Dec 27 01:33:27 PM PST 23
Finished Dec 27 01:58:01 PM PST 23
Peak memory 249916 kb
Host smart-ab03ac10-69a0-40cc-8f61-ae81f4e793e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731939477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_perf.2731939477
Directory /workspace/28.spi_device_perf/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.465634171
Short name T660
Test name
Test status
Simulation time 176311796 ps
CPU time 3.62 seconds
Started Dec 27 01:33:33 PM PST 23
Finished Dec 27 01:33:37 PM PST 23
Peak memory 220920 kb
Host smart-6a87f464-b4d9-426d-b7c3-2ff68e1fadb1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=465634171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.465634171
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_rx_async_fifo_reset.1849675308
Short name T1665
Test name
Test status
Simulation time 104580369 ps
CPU time 0.85 seconds
Started Dec 27 01:33:20 PM PST 23
Finished Dec 27 01:33:22 PM PST 23
Peak memory 208468 kb
Host smart-e5e7fbc5-0d2e-41c3-a1e3-dba910ac7a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849675308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_rx_async_fifo_reset.1849675308
Directory /workspace/28.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/28.spi_device_rx_timeout.997777440
Short name T1114
Test name
Test status
Simulation time 3631812935 ps
CPU time 6.13 seconds
Started Dec 27 01:33:37 PM PST 23
Finished Dec 27 01:33:45 PM PST 23
Peak memory 216804 kb
Host smart-dc58749e-44d7-41b4-9718-d0d9de0c37b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997777440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_rx_timeout.997777440
Directory /workspace/28.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/28.spi_device_smoke.946982861
Short name T492
Test name
Test status
Simulation time 50069597 ps
CPU time 1.12 seconds
Started Dec 27 01:33:22 PM PST 23
Finished Dec 27 01:33:25 PM PST 23
Peak memory 216472 kb
Host smart-09b71eb7-f738-4f09-b0b9-147428b2b59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946982861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_smoke.946982861
Directory /workspace/28.spi_device_smoke/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2645738983
Short name T1308
Test name
Test status
Simulation time 799222031 ps
CPU time 14.08 seconds
Started Dec 27 01:33:52 PM PST 23
Finished Dec 27 01:34:06 PM PST 23
Peak memory 217144 kb
Host smart-ad4b9750-37be-48f0-a3ae-ffc164c2cf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645738983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2645738983
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1800768919
Short name T1184
Test name
Test status
Simulation time 1661196181 ps
CPU time 5.5 seconds
Started Dec 27 01:33:25 PM PST 23
Finished Dec 27 01:33:33 PM PST 23
Peak memory 216728 kb
Host smart-328d62a0-93a7-4c25-8ff0-e4b0e56e1b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800768919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1800768919
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2195651292
Short name T359
Test name
Test status
Simulation time 44115053 ps
CPU time 0.77 seconds
Started Dec 27 01:33:28 PM PST 23
Finished Dec 27 01:33:29 PM PST 23
Peak memory 206900 kb
Host smart-bfa5940c-160f-493a-94a5-15cff432eb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195651292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2195651292
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1115750549
Short name T1058
Test name
Test status
Simulation time 200684687 ps
CPU time 0.99 seconds
Started Dec 27 01:33:21 PM PST 23
Finished Dec 27 01:33:23 PM PST 23
Peak memory 208028 kb
Host smart-79396411-0db6-45b6-85ce-83748a09d6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115750549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1115750549
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_tx_async_fifo_reset.2243082253
Short name T591
Test name
Test status
Simulation time 17142987 ps
CPU time 0.77 seconds
Started Dec 27 01:33:31 PM PST 23
Finished Dec 27 01:33:33 PM PST 23
Peak memory 208472 kb
Host smart-1fc4d5de-ca8d-4e73-a9db-0c47a4089362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243082253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tx_async_fifo_reset.2243082253
Directory /workspace/28.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/28.spi_device_txrx.966529341
Short name T491
Test name
Test status
Simulation time 17003879406 ps
CPU time 155.78 seconds
Started Dec 27 01:33:17 PM PST 23
Finished Dec 27 01:35:54 PM PST 23
Peak memory 253760 kb
Host smart-2f7334ca-d407-44eb-a193-fed448bfa1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966529341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_txrx.966529341
Directory /workspace/28.spi_device_txrx/latest

Test location /workspace/coverage/default/28.spi_device_upload.3608760701
Short name T808
Test name
Test status
Simulation time 855626675 ps
CPU time 4.94 seconds
Started Dec 27 01:33:23 PM PST 23
Finished Dec 27 01:33:29 PM PST 23
Peak memory 219336 kb
Host smart-a4ca6c8e-e82b-4969-ac8d-7ac9dbba5682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608760701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3608760701
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_abort.2402761656
Short name T1339
Test name
Test status
Simulation time 17477790 ps
CPU time 0.81 seconds
Started Dec 27 01:33:47 PM PST 23
Finished Dec 27 01:33:48 PM PST 23
Peak memory 206572 kb
Host smart-fb4cf611-32d6-4961-a989-52e0ddf181ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402761656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_abort.2402761656
Directory /workspace/29.spi_device_abort/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2301451637
Short name T1080
Test name
Test status
Simulation time 15838226 ps
CPU time 0.73 seconds
Started Dec 27 01:33:52 PM PST 23
Finished Dec 27 01:33:54 PM PST 23
Peak memory 206484 kb
Host smart-91cd3ade-4704-40ca-a018-f6d790957d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301451637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2301451637
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_bit_transfer.4253088521
Short name T1511
Test name
Test status
Simulation time 224147733 ps
CPU time 2.88 seconds
Started Dec 27 01:33:50 PM PST 23
Finished Dec 27 01:33:55 PM PST 23
Peak memory 216880 kb
Host smart-70110d11-c88e-4f6f-acd4-4de46f8dbcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253088521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_bit_transfer.4253088521
Directory /workspace/29.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/29.spi_device_byte_transfer.1947853683
Short name T811
Test name
Test status
Simulation time 582228163 ps
CPU time 2.88 seconds
Started Dec 27 01:33:37 PM PST 23
Finished Dec 27 01:33:40 PM PST 23
Peak memory 216788 kb
Host smart-6e446057-e8bd-4d4c-bf29-cd3ceeddcf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947853683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_byte_transfer.1947853683
Directory /workspace/29.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3699893891
Short name T298
Test name
Test status
Simulation time 919786552 ps
CPU time 8.92 seconds
Started Dec 27 01:33:55 PM PST 23
Finished Dec 27 01:34:05 PM PST 23
Peak memory 239960 kb
Host smart-8ae36e6b-124d-4e9b-89f9-d10b2e2726fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699893891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3699893891
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.457574293
Short name T1017
Test name
Test status
Simulation time 23520667 ps
CPU time 0.77 seconds
Started Dec 27 01:33:38 PM PST 23
Finished Dec 27 01:33:40 PM PST 23
Peak memory 206560 kb
Host smart-08e8afce-f742-48a5-a4c8-5327c3f1ad0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457574293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.457574293
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_dummy_item_extra_dly.332155737
Short name T1255
Test name
Test status
Simulation time 141570373735 ps
CPU time 125.56 seconds
Started Dec 27 01:33:46 PM PST 23
Finished Dec 27 01:35:52 PM PST 23
Peak memory 252720 kb
Host smart-fdead5bc-b9cd-4b73-b9c3-e8eb0c0c54b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332155737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_dummy_item_extra_dly.332155737
Directory /workspace/29.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/29.spi_device_extreme_fifo_size.1062246868
Short name T571
Test name
Test status
Simulation time 17508691095 ps
CPU time 102.28 seconds
Started Dec 27 01:33:23 PM PST 23
Finished Dec 27 01:35:07 PM PST 23
Peak memory 236928 kb
Host smart-b87d08b5-9279-4148-a0ce-33a3dc68edd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062246868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_extreme_fifo_size.1062246868
Directory /workspace/29.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/29.spi_device_fifo_full.686274724
Short name T1700
Test name
Test status
Simulation time 29675464055 ps
CPU time 599.22 seconds
Started Dec 27 01:33:50 PM PST 23
Finished Dec 27 01:43:51 PM PST 23
Peak memory 261820 kb
Host smart-a7c90b46-fedb-449d-a5ca-d0ba0f9e3dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686274724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_fifo_full.686274724
Directory /workspace/29.spi_device_fifo_full/latest

Test location /workspace/coverage/default/29.spi_device_fifo_underflow_overflow.1448036180
Short name T70
Test name
Test status
Simulation time 68839611554 ps
CPU time 398.67 seconds
Started Dec 27 01:33:25 PM PST 23
Finished Dec 27 01:40:05 PM PST 23
Peak memory 412356 kb
Host smart-67cfd6ec-8b6f-45ec-9cf1-ccb304f7885d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448036180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_fifo_underflow_overf
low.1448036180
Directory /workspace/29.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.395163529
Short name T1710
Test name
Test status
Simulation time 11548453673 ps
CPU time 56.72 seconds
Started Dec 27 01:33:52 PM PST 23
Finished Dec 27 01:34:49 PM PST 23
Peak memory 255500 kb
Host smart-161a8b4e-369c-47db-b5ca-fcbb512df70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395163529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.395163529
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1853847822
Short name T701
Test name
Test status
Simulation time 105790637463 ps
CPU time 484.43 seconds
Started Dec 27 01:34:00 PM PST 23
Finished Dec 27 01:42:04 PM PST 23
Peak memory 267084 kb
Host smart-620859d3-270c-42ee-bea2-b0613678643b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853847822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1853847822
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2647449696
Short name T713
Test name
Test status
Simulation time 5514246862 ps
CPU time 64.58 seconds
Started Dec 27 01:34:09 PM PST 23
Finished Dec 27 01:35:14 PM PST 23
Peak memory 249804 kb
Host smart-6a9027f3-a5da-4f8c-a709-38e3011e3898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647449696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2647449696
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3982111204
Short name T1417
Test name
Test status
Simulation time 590646173 ps
CPU time 3.16 seconds
Started Dec 27 01:33:56 PM PST 23
Finished Dec 27 01:34:00 PM PST 23
Peak memory 219816 kb
Host smart-184ee887-d6a3-4920-b2a1-025bec3653b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982111204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3982111204
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_intr.922104846
Short name T1690
Test name
Test status
Simulation time 18728475086 ps
CPU time 26.37 seconds
Started Dec 27 01:33:55 PM PST 23
Finished Dec 27 01:34:22 PM PST 23
Peak memory 232120 kb
Host smart-17a35817-4627-48bb-a221-4a4cc2225b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922104846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intr.922104846
Directory /workspace/29.spi_device_intr/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2925996343
Short name T302
Test name
Test status
Simulation time 3989349075 ps
CPU time 18.85 seconds
Started Dec 27 01:33:37 PM PST 23
Finished Dec 27 01:33:56 PM PST 23
Peak memory 246968 kb
Host smart-f098d752-ac80-48f5-984e-1dc9055db5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925996343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2925996343
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1157487630
Short name T1239
Test name
Test status
Simulation time 3544843319 ps
CPU time 11.65 seconds
Started Dec 27 01:33:46 PM PST 23
Finished Dec 27 01:33:59 PM PST 23
Peak memory 246716 kb
Host smart-d260c176-1f2e-4402-8100-8d4359bd774c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157487630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1157487630
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3944366841
Short name T973
Test name
Test status
Simulation time 6492166919 ps
CPU time 21.56 seconds
Started Dec 27 01:33:50 PM PST 23
Finished Dec 27 01:34:13 PM PST 23
Peak memory 241496 kb
Host smart-8726b9dd-a19f-41d8-adaf-7e78de7a3547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944366841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3944366841
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_perf.614799710
Short name T1234
Test name
Test status
Simulation time 21073259736 ps
CPU time 458.37 seconds
Started Dec 27 01:33:53 PM PST 23
Finished Dec 27 01:41:32 PM PST 23
Peak memory 250792 kb
Host smart-8d6e403f-2c0f-4e28-aabb-42eea620e828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614799710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_perf.614799710
Directory /workspace/29.spi_device_perf/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1993914782
Short name T1496
Test name
Test status
Simulation time 144161931 ps
CPU time 3.63 seconds
Started Dec 27 01:33:55 PM PST 23
Finished Dec 27 01:34:00 PM PST 23
Peak memory 218748 kb
Host smart-95b61c34-aa2f-413b-8d9c-27f87f16448e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1993914782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1993914782
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_rx_async_fifo_reset.3495110680
Short name T680
Test name
Test status
Simulation time 64706348 ps
CPU time 0.84 seconds
Started Dec 27 01:34:02 PM PST 23
Finished Dec 27 01:34:03 PM PST 23
Peak memory 208436 kb
Host smart-9043a961-b696-48ed-8817-06075e7d394e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495110680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_rx_async_fifo_reset.3495110680
Directory /workspace/29.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/29.spi_device_rx_timeout.3196644552
Short name T517
Test name
Test status
Simulation time 11448240908 ps
CPU time 5.59 seconds
Started Dec 27 01:34:00 PM PST 23
Finished Dec 27 01:34:07 PM PST 23
Peak memory 216884 kb
Host smart-70cef392-2ef8-4951-b830-221f010852cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196644552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_rx_timeout.3196644552
Directory /workspace/29.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/29.spi_device_smoke.4104050990
Short name T534
Test name
Test status
Simulation time 66482442 ps
CPU time 0.97 seconds
Started Dec 27 01:33:22 PM PST 23
Finished Dec 27 01:33:25 PM PST 23
Peak memory 208388 kb
Host smart-e9f77235-d1f4-4a0b-9dfb-c3765ba4454c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104050990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_smoke.4104050990
Directory /workspace/29.spi_device_smoke/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2470139758
Short name T100
Test name
Test status
Simulation time 1102192037 ps
CPU time 7.96 seconds
Started Dec 27 01:33:39 PM PST 23
Finished Dec 27 01:33:48 PM PST 23
Peak memory 217080 kb
Host smart-9ba6a745-ecbd-489f-a452-95483a708de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470139758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2470139758
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1564170320
Short name T494
Test name
Test status
Simulation time 2549082177 ps
CPU time 15.01 seconds
Started Dec 27 01:33:50 PM PST 23
Finished Dec 27 01:34:06 PM PST 23
Peak memory 216888 kb
Host smart-6acee7a7-8d99-4704-8198-4f90ddb5ba54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564170320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1564170320
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3019798377
Short name T783
Test name
Test status
Simulation time 208307236 ps
CPU time 2.86 seconds
Started Dec 27 01:33:57 PM PST 23
Finished Dec 27 01:34:01 PM PST 23
Peak memory 216756 kb
Host smart-7cc4abe8-8640-45bc-bf8e-8ec32cf0ef58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019798377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3019798377
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3069301021
Short name T666
Test name
Test status
Simulation time 519280297 ps
CPU time 1.14 seconds
Started Dec 27 01:33:41 PM PST 23
Finished Dec 27 01:33:43 PM PST 23
Peak memory 207896 kb
Host smart-f4c78e08-4dbd-4d19-9325-0f13ddb61e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069301021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3069301021
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_tx_async_fifo_reset.4258588305
Short name T1434
Test name
Test status
Simulation time 13010891 ps
CPU time 0.79 seconds
Started Dec 27 01:33:22 PM PST 23
Finished Dec 27 01:33:24 PM PST 23
Peak memory 208404 kb
Host smart-eca4c875-0b05-4e8e-b36e-f987beb9a89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258588305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tx_async_fifo_reset.4258588305
Directory /workspace/29.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/29.spi_device_txrx.2385554280
Short name T950
Test name
Test status
Simulation time 26026851333 ps
CPU time 341.52 seconds
Started Dec 27 01:33:25 PM PST 23
Finished Dec 27 01:39:07 PM PST 23
Peak memory 282548 kb
Host smart-48bbac80-8290-4b9a-a0c6-ca627fc9ff3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385554280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_txrx.2385554280
Directory /workspace/29.spi_device_txrx/latest

Test location /workspace/coverage/default/29.spi_device_upload.3999887508
Short name T843
Test name
Test status
Simulation time 3311653527 ps
CPU time 12.37 seconds
Started Dec 27 01:33:57 PM PST 23
Finished Dec 27 01:34:10 PM PST 23
Peak memory 218704 kb
Host smart-88ae18a0-b5c9-474b-9c40-3a65ac2c7e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999887508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3999887508
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_abort.3827847371
Short name T772
Test name
Test status
Simulation time 51663484 ps
CPU time 0.74 seconds
Started Dec 27 01:30:10 PM PST 23
Finished Dec 27 01:30:14 PM PST 23
Peak memory 206688 kb
Host smart-2892f881-847b-4f1a-b78a-61bdf2bb6536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827847371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_abort.3827847371
Directory /workspace/3.spi_device_abort/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2067410989
Short name T883
Test name
Test status
Simulation time 12988673 ps
CPU time 0.72 seconds
Started Dec 27 01:30:18 PM PST 23
Finished Dec 27 01:30:21 PM PST 23
Peak memory 206564 kb
Host smart-6fb79fc6-7966-4161-93c9-5d08a46ef2b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067410989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
067410989
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_byte_transfer.3605478154
Short name T890
Test name
Test status
Simulation time 69652752 ps
CPU time 2.56 seconds
Started Dec 27 01:30:12 PM PST 23
Finished Dec 27 01:30:19 PM PST 23
Peak memory 216744 kb
Host smart-c1a83364-fd87-46b1-b389-640bef894fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605478154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_byte_transfer.3605478154
Directory /workspace/3.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.526326868
Short name T275
Test name
Test status
Simulation time 419152823 ps
CPU time 2.91 seconds
Started Dec 27 01:30:10 PM PST 23
Finished Dec 27 01:30:16 PM PST 23
Peak memory 218308 kb
Host smart-d2aaf794-8e73-4bcf-9cf7-575d0af5ed27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526326868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.526326868
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.797089038
Short name T138
Test name
Test status
Simulation time 20098545 ps
CPU time 0.8 seconds
Started Dec 27 01:30:29 PM PST 23
Finished Dec 27 01:30:31 PM PST 23
Peak memory 207548 kb
Host smart-3c922340-7492-46cf-8b11-daa1ad926860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797089038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.797089038
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_dummy_item_extra_dly.1015256138
Short name T523
Test name
Test status
Simulation time 66284763475 ps
CPU time 1537.28 seconds
Started Dec 27 01:30:12 PM PST 23
Finished Dec 27 01:55:54 PM PST 23
Peak memory 275916 kb
Host smart-cc6cd1f7-1020-46e1-9e3f-e164e152c04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015256138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_dummy_item_extra_dly.1015256138
Directory /workspace/3.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/3.spi_device_extreme_fifo_size.4046803613
Short name T736
Test name
Test status
Simulation time 15026511866 ps
CPU time 37.43 seconds
Started Dec 27 01:30:12 PM PST 23
Finished Dec 27 01:30:54 PM PST 23
Peak memory 238296 kb
Host smart-bb80532f-272c-452b-a02f-0424549b59e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046803613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_extreme_fifo_size.4046803613
Directory /workspace/3.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/3.spi_device_fifo_full.1975720453
Short name T1109
Test name
Test status
Simulation time 82993670639 ps
CPU time 1628.23 seconds
Started Dec 27 01:30:13 PM PST 23
Finished Dec 27 01:57:25 PM PST 23
Peak memory 303960 kb
Host smart-6799eeb3-4e4a-4cce-8198-10e71022f550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975720453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_fifo_full.1975720453
Directory /workspace/3.spi_device_fifo_full/latest

Test location /workspace/coverage/default/3.spi_device_fifo_underflow_overflow.3016343559
Short name T210
Test name
Test status
Simulation time 645755176196 ps
CPU time 938.62 seconds
Started Dec 27 01:29:56 PM PST 23
Finished Dec 27 01:45:38 PM PST 23
Peak memory 679932 kb
Host smart-f5f8705c-5652-4ff1-a421-dc13bf539e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016343559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_fifo_underflow_overfl
ow.3016343559
Directory /workspace/3.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1088890171
Short name T1052
Test name
Test status
Simulation time 83341339594 ps
CPU time 320.29 seconds
Started Dec 27 01:30:29 PM PST 23
Finished Dec 27 01:35:51 PM PST 23
Peak memory 266044 kb
Host smart-e9902c82-99c7-42a2-b6ad-0e499b4336d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088890171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1088890171
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3526644727
Short name T1435
Test name
Test status
Simulation time 9437354648 ps
CPU time 21.98 seconds
Started Dec 27 01:30:18 PM PST 23
Finished Dec 27 01:30:42 PM PST 23
Peak memory 243032 kb
Host smart-620deabd-8cc8-494d-81c9-d72c57a635d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526644727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3526644727
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2888873173
Short name T239
Test name
Test status
Simulation time 189353249 ps
CPU time 3.68 seconds
Started Dec 27 01:30:11 PM PST 23
Finished Dec 27 01:30:17 PM PST 23
Peak memory 238160 kb
Host smart-c67879b5-8905-4ae0-8e9e-cec0ccc30faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888873173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2888873173
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_intr.2416326644
Short name T1594
Test name
Test status
Simulation time 3447955962 ps
CPU time 16.6 seconds
Started Dec 27 01:30:29 PM PST 23
Finished Dec 27 01:30:47 PM PST 23
Peak memory 217860 kb
Host smart-43a60c70-39d3-4703-87a3-6ee100f00cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416326644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intr.2416326644
Directory /workspace/3.spi_device_intr/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1482337207
Short name T1083
Test name
Test status
Simulation time 74350258693 ps
CPU time 29.91 seconds
Started Dec 27 01:30:13 PM PST 23
Finished Dec 27 01:30:47 PM PST 23
Peak memory 248244 kb
Host smart-2663e9b5-0eb4-459e-8cb7-35fb1e6e827a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482337207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1482337207
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3229360489
Short name T3
Test name
Test status
Simulation time 24865688 ps
CPU time 1.06 seconds
Started Dec 27 01:30:21 PM PST 23
Finished Dec 27 01:30:24 PM PST 23
Peak memory 218772 kb
Host smart-9d2be898-9629-47f0-bbad-370e2d7287ff
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229360489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3229360489
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2452192751
Short name T307
Test name
Test status
Simulation time 11426857149 ps
CPU time 16.27 seconds
Started Dec 27 01:30:11 PM PST 23
Finished Dec 27 01:30:30 PM PST 23
Peak memory 238456 kb
Host smart-4f743364-cb3f-42be-b4b0-aa3ba31425dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452192751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2452192751
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1366922694
Short name T285
Test name
Test status
Simulation time 1670634109 ps
CPU time 8.17 seconds
Started Dec 27 01:30:26 PM PST 23
Finished Dec 27 01:30:35 PM PST 23
Peak memory 240600 kb
Host smart-6aad3bde-06aa-4e1a-b414-e0b6e8afaacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366922694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1366922694
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_perf.1954202240
Short name T1524
Test name
Test status
Simulation time 11909894391 ps
CPU time 249.38 seconds
Started Dec 27 01:29:57 PM PST 23
Finished Dec 27 01:34:09 PM PST 23
Peak memory 249808 kb
Host smart-3c253cb8-58dd-42b6-af52-90272a9bde7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954202240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_perf.1954202240
Directory /workspace/3.spi_device_perf/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.1648678608
Short name T107
Test name
Test status
Simulation time 29517379 ps
CPU time 0.74 seconds
Started Dec 27 01:30:26 PM PST 23
Finished Dec 27 01:30:28 PM PST 23
Peak memory 216736 kb
Host smart-b47c8727-6841-4f6a-b629-8c024b836783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648678608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.1648678608
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.4024079643
Short name T744
Test name
Test status
Simulation time 3810639110 ps
CPU time 6.62 seconds
Started Dec 27 01:30:41 PM PST 23
Finished Dec 27 01:30:48 PM PST 23
Peak memory 236880 kb
Host smart-6be05211-ebc2-4be4-a760-740c9527562d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4024079643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.4024079643
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_rx_async_fifo_reset.3523955226
Short name T967
Test name
Test status
Simulation time 70366448 ps
CPU time 0.86 seconds
Started Dec 27 01:30:31 PM PST 23
Finished Dec 27 01:30:33 PM PST 23
Peak memory 208368 kb
Host smart-6e3ec2ee-6c1c-46e5-a0e5-d836f4107b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523955226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_rx_async_fifo_reset.3523955226
Directory /workspace/3.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/3.spi_device_rx_timeout.4189595972
Short name T1298
Test name
Test status
Simulation time 2849230832 ps
CPU time 6.56 seconds
Started Dec 27 01:30:14 PM PST 23
Finished Dec 27 01:30:25 PM PST 23
Peak memory 216772 kb
Host smart-65f7df98-bcd0-4889-95c8-8f6e0ab9ed71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189595972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_rx_timeout.4189595972
Directory /workspace/3.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.501684347
Short name T112
Test name
Test status
Simulation time 222502120 ps
CPU time 1.3 seconds
Started Dec 27 01:30:08 PM PST 23
Finished Dec 27 01:30:14 PM PST 23
Peak memory 238156 kb
Host smart-31ed6253-19de-4041-9cf8-7941b570a86e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501684347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.501684347
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_smoke.392089850
Short name T1231
Test name
Test status
Simulation time 247424201 ps
CPU time 1.31 seconds
Started Dec 27 01:30:39 PM PST 23
Finished Dec 27 01:30:41 PM PST 23
Peak memory 216836 kb
Host smart-58d90ccd-ea0d-4449-8f24-87b5f045f5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392089850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_smoke.392089850
Directory /workspace/3.spi_device_smoke/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2030158577
Short name T188
Test name
Test status
Simulation time 209096996256 ps
CPU time 1090.3 seconds
Started Dec 27 01:30:14 PM PST 23
Finished Dec 27 01:48:29 PM PST 23
Peak memory 379912 kb
Host smart-5142907e-3824-455c-8a34-1d2215a136ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030158577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2030158577
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3605914909
Short name T755
Test name
Test status
Simulation time 4292284292 ps
CPU time 37.7 seconds
Started Dec 27 01:30:26 PM PST 23
Finished Dec 27 01:31:05 PM PST 23
Peak memory 216908 kb
Host smart-a15c2a12-8328-4f00-99d7-79c590452423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605914909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3605914909
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1362481861
Short name T1075
Test name
Test status
Simulation time 1325501396 ps
CPU time 2.71 seconds
Started Dec 27 01:30:11 PM PST 23
Finished Dec 27 01:30:18 PM PST 23
Peak memory 207944 kb
Host smart-582c4b6c-7c52-4811-b4d0-f5eb1bcc01b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362481861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1362481861
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1568808833
Short name T616
Test name
Test status
Simulation time 405283561 ps
CPU time 2.16 seconds
Started Dec 27 01:30:22 PM PST 23
Finished Dec 27 01:30:26 PM PST 23
Peak memory 216824 kb
Host smart-ae28fb2a-7698-4c9f-9767-bad506dafd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568808833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1568808833
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.4216365105
Short name T136
Test name
Test status
Simulation time 151569788 ps
CPU time 0.82 seconds
Started Dec 27 01:30:39 PM PST 23
Finished Dec 27 01:30:40 PM PST 23
Peak memory 206940 kb
Host smart-ca0521ea-b312-45eb-890d-8f21b5e443c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216365105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.4216365105
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_tx_async_fifo_reset.1137646093
Short name T684
Test name
Test status
Simulation time 15996111 ps
CPU time 0.78 seconds
Started Dec 27 01:30:28 PM PST 23
Finished Dec 27 01:30:30 PM PST 23
Peak memory 208404 kb
Host smart-8e6e62b5-b457-43ce-ac71-5a52f78d4555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137646093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tx_async_fifo_reset.1137646093
Directory /workspace/3.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/3.spi_device_txrx.2998354387
Short name T1221
Test name
Test status
Simulation time 20121087405 ps
CPU time 320.5 seconds
Started Dec 27 01:30:19 PM PST 23
Finished Dec 27 01:35:42 PM PST 23
Peak memory 265176 kb
Host smart-6649bd6d-29e7-4a50-9fef-566ee0b0dfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998354387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_txrx.2998354387
Directory /workspace/3.spi_device_txrx/latest

Test location /workspace/coverage/default/3.spi_device_upload.3778891085
Short name T621
Test name
Test status
Simulation time 1172891892 ps
CPU time 5.68 seconds
Started Dec 27 01:30:13 PM PST 23
Finished Dec 27 01:30:23 PM PST 23
Peak memory 243456 kb
Host smart-9dddb531-f48a-423f-9d53-031cf5716742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778891085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3778891085
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_abort.1076970852
Short name T854
Test name
Test status
Simulation time 26505158 ps
CPU time 0.81 seconds
Started Dec 27 01:33:48 PM PST 23
Finished Dec 27 01:33:49 PM PST 23
Peak memory 206568 kb
Host smart-e8e02093-fd9c-4c55-9aa9-0f24f9a9be9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076970852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_abort.1076970852
Directory /workspace/30.spi_device_abort/latest

Test location /workspace/coverage/default/30.spi_device_bit_transfer.3559893325
Short name T1222
Test name
Test status
Simulation time 248888903 ps
CPU time 2.24 seconds
Started Dec 27 01:33:30 PM PST 23
Finished Dec 27 01:33:34 PM PST 23
Peak memory 216768 kb
Host smart-891980e6-47e8-45c9-bc0a-0efcc720a726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559893325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_bit_transfer.3559893325
Directory /workspace/30.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/30.spi_device_byte_transfer.3460114660
Short name T1494
Test name
Test status
Simulation time 910306039 ps
CPU time 3.01 seconds
Started Dec 27 01:34:12 PM PST 23
Finished Dec 27 01:34:16 PM PST 23
Peak memory 216724 kb
Host smart-5c83fbc7-eed1-4ec3-a7f3-0ef2201d21f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460114660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_byte_transfer.3460114660
Directory /workspace/30.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.367528018
Short name T716
Test name
Test status
Simulation time 1910336079 ps
CPU time 5.78 seconds
Started Dec 27 01:33:49 PM PST 23
Finished Dec 27 01:33:55 PM PST 23
Peak memory 221240 kb
Host smart-9def2acc-d2f4-4141-8175-136ae80d4576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367528018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.367528018
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.961502391
Short name T781
Test name
Test status
Simulation time 38374603 ps
CPU time 0.78 seconds
Started Dec 27 01:33:32 PM PST 23
Finished Dec 27 01:33:34 PM PST 23
Peak memory 207588 kb
Host smart-a682bf87-03fd-4d09-a8b5-44cca7ff760b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961502391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.961502391
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_dummy_item_extra_dly.2527571555
Short name T1180
Test name
Test status
Simulation time 35454422888 ps
CPU time 520.8 seconds
Started Dec 27 01:34:03 PM PST 23
Finished Dec 27 01:42:45 PM PST 23
Peak memory 290176 kb
Host smart-4efcfadc-cfbd-4021-8774-c11465fa99ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527571555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_dummy_item_extra_dly.2527571555
Directory /workspace/30.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/30.spi_device_extreme_fifo_size.498914986
Short name T502
Test name
Test status
Simulation time 73735260339 ps
CPU time 119.4 seconds
Started Dec 27 01:34:10 PM PST 23
Finished Dec 27 01:36:10 PM PST 23
Peak memory 228260 kb
Host smart-d2b3a9df-faf4-4def-9fc7-84b73955d22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498914986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_extreme_fifo_size.498914986
Directory /workspace/30.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/30.spi_device_fifo_full.8972106
Short name T659
Test name
Test status
Simulation time 58373743579 ps
CPU time 920.54 seconds
Started Dec 27 01:34:15 PM PST 23
Finished Dec 27 01:49:36 PM PST 23
Peak memory 253252 kb
Host smart-5cfe5b51-0080-4f8c-8f2d-59dc56a501dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8972106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_fifo_full.8972106
Directory /workspace/30.spi_device_fifo_full/latest

Test location /workspace/coverage/default/30.spi_device_fifo_underflow_overflow.1367179477
Short name T1279
Test name
Test status
Simulation time 214910724743 ps
CPU time 562.44 seconds
Started Dec 27 01:34:04 PM PST 23
Finished Dec 27 01:43:27 PM PST 23
Peak memory 464480 kb
Host smart-09fd2ff5-8cb8-4935-b831-30fd520424a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367179477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_fifo_underflow_overf
low.1367179477
Directory /workspace/30.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1672097989
Short name T7
Test name
Test status
Simulation time 8512925955 ps
CPU time 50.89 seconds
Started Dec 27 01:34:07 PM PST 23
Finished Dec 27 01:34:58 PM PST 23
Peak memory 249744 kb
Host smart-5202897b-547b-49a6-ba60-2e5f929a3408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672097989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1672097989
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.550076503
Short name T1188
Test name
Test status
Simulation time 15232071892 ps
CPU time 51.66 seconds
Started Dec 27 01:34:15 PM PST 23
Finished Dec 27 01:35:07 PM PST 23
Peak memory 239868 kb
Host smart-29c5ce82-10f2-4ca1-937b-4e734401cf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550076503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.550076503
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1067733716
Short name T257
Test name
Test status
Simulation time 35434695963 ps
CPU time 265.18 seconds
Started Dec 27 01:34:34 PM PST 23
Finished Dec 27 01:39:00 PM PST 23
Peak memory 257948 kb
Host smart-afcbca8c-7fb1-4541-a521-36dc123ebe33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067733716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1067733716
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3145430693
Short name T1261
Test name
Test status
Simulation time 1119459769 ps
CPU time 9.24 seconds
Started Dec 27 01:33:59 PM PST 23
Finished Dec 27 01:34:09 PM PST 23
Peak memory 242764 kb
Host smart-7d8df4ac-9f53-4c57-bc96-52bdf831872b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145430693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3145430693
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2507302553
Short name T1101
Test name
Test status
Simulation time 209596289 ps
CPU time 4.83 seconds
Started Dec 27 01:34:02 PM PST 23
Finished Dec 27 01:34:08 PM PST 23
Peak memory 238928 kb
Host smart-43ceb2e8-1e70-41d4-be5c-1c61d038ae7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507302553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2507302553
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_intr.1188668265
Short name T1357
Test name
Test status
Simulation time 118396511842 ps
CPU time 138.45 seconds
Started Dec 27 01:33:33 PM PST 23
Finished Dec 27 01:35:52 PM PST 23
Peak memory 248564 kb
Host smart-c025a7dd-eaf8-4262-b3da-1efa441b6b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188668265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intr.1188668265
Directory /workspace/30.spi_device_intr/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2231811543
Short name T1327
Test name
Test status
Simulation time 1498830940 ps
CPU time 5.63 seconds
Started Dec 27 01:33:38 PM PST 23
Finished Dec 27 01:33:45 PM PST 23
Peak memory 218856 kb
Host smart-c1b97a02-eb49-484f-b0c8-3a5ee0f71b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231811543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2231811543
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3096630994
Short name T1635
Test name
Test status
Simulation time 902504155 ps
CPU time 4.36 seconds
Started Dec 27 01:33:52 PM PST 23
Finished Dec 27 01:33:57 PM PST 23
Peak memory 218300 kb
Host smart-8997ac78-51dc-4950-8233-ec70805ab3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096630994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3096630994
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2357307951
Short name T1416
Test name
Test status
Simulation time 32158405733 ps
CPU time 22.52 seconds
Started Dec 27 01:33:46 PM PST 23
Finished Dec 27 01:34:09 PM PST 23
Peak memory 218860 kb
Host smart-39e2066b-28eb-4bc1-99e8-12bae7425939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357307951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2357307951
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_perf.490935474
Short name T1440
Test name
Test status
Simulation time 65778998042 ps
CPU time 462.86 seconds
Started Dec 27 01:33:38 PM PST 23
Finished Dec 27 01:41:22 PM PST 23
Peak memory 267212 kb
Host smart-829d1030-4aa3-49d4-8e1a-602eef20e77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490935474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_perf.490935474
Directory /workspace/30.spi_device_perf/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.542914577
Short name T1492
Test name
Test status
Simulation time 126609299 ps
CPU time 4.2 seconds
Started Dec 27 01:34:09 PM PST 23
Finished Dec 27 01:34:13 PM PST 23
Peak memory 234120 kb
Host smart-62ee19d7-7225-45a1-803f-700b4e6f2f48
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=542914577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.542914577
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_rx_async_fifo_reset.1852969550
Short name T1641
Test name
Test status
Simulation time 160312994 ps
CPU time 1.02 seconds
Started Dec 27 01:33:39 PM PST 23
Finished Dec 27 01:33:41 PM PST 23
Peak memory 208452 kb
Host smart-d1eea93a-f2eb-40a8-9d86-abbd6afc5000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852969550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_rx_async_fifo_reset.1852969550
Directory /workspace/30.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/30.spi_device_rx_timeout.1734256654
Short name T937
Test name
Test status
Simulation time 563887046 ps
CPU time 5.1 seconds
Started Dec 27 01:33:35 PM PST 23
Finished Dec 27 01:33:41 PM PST 23
Peak memory 216888 kb
Host smart-695d1231-d019-46f3-8c79-b949bedc3e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734256654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_rx_timeout.1734256654
Directory /workspace/30.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/30.spi_device_smoke.4022960214
Short name T760
Test name
Test status
Simulation time 71999626 ps
CPU time 1.07 seconds
Started Dec 27 01:33:55 PM PST 23
Finished Dec 27 01:33:57 PM PST 23
Peak memory 208344 kb
Host smart-a15d8b9c-859e-4a19-ac93-bf010a266c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022960214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_smoke.4022960214
Directory /workspace/30.spi_device_smoke/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2908475963
Short name T1447
Test name
Test status
Simulation time 546869814242 ps
CPU time 7083.28 seconds
Started Dec 27 01:33:46 PM PST 23
Finished Dec 27 03:31:51 PM PST 23
Peak memory 274096 kb
Host smart-80ba34c0-2515-4fd7-b52f-5605126e3fca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908475963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2908475963
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1309542887
Short name T799
Test name
Test status
Simulation time 610542308 ps
CPU time 5.34 seconds
Started Dec 27 01:33:27 PM PST 23
Finished Dec 27 01:33:33 PM PST 23
Peak memory 219840 kb
Host smart-622d76a7-5a8f-49d1-8b35-ec17020de5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309542887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1309542887
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3038457336
Short name T135
Test name
Test status
Simulation time 6860501342 ps
CPU time 9.89 seconds
Started Dec 27 01:33:32 PM PST 23
Finished Dec 27 01:33:43 PM PST 23
Peak memory 216860 kb
Host smart-7ae545da-3a35-4d11-a881-7d5e5a05465c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038457336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3038457336
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2863088241
Short name T1692
Test name
Test status
Simulation time 213715587 ps
CPU time 3.08 seconds
Started Dec 27 01:33:54 PM PST 23
Finished Dec 27 01:33:58 PM PST 23
Peak memory 216860 kb
Host smart-ee1d593a-39e8-41a0-9058-a12e90f70942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863088241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2863088241
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.4033752345
Short name T919
Test name
Test status
Simulation time 80616696 ps
CPU time 0.96 seconds
Started Dec 27 01:33:38 PM PST 23
Finished Dec 27 01:33:40 PM PST 23
Peak memory 206892 kb
Host smart-2ef04b3b-dade-4f55-953a-3b8cc003839d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033752345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.4033752345
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_tx_async_fifo_reset.963544188
Short name T1655
Test name
Test status
Simulation time 17754611 ps
CPU time 0.84 seconds
Started Dec 27 01:33:49 PM PST 23
Finished Dec 27 01:33:51 PM PST 23
Peak memory 208400 kb
Host smart-bb5b41af-e475-4e1e-b3b9-13c028d3a3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963544188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tx_async_fifo_reset.963544188
Directory /workspace/30.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/30.spi_device_txrx.1956015872
Short name T829
Test name
Test status
Simulation time 12571324283 ps
CPU time 130.13 seconds
Started Dec 27 01:34:05 PM PST 23
Finished Dec 27 01:36:16 PM PST 23
Peak memory 260120 kb
Host smart-08015aa0-9f2d-41ed-8d09-6363130404e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956015872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_txrx.1956015872
Directory /workspace/30.spi_device_txrx/latest

Test location /workspace/coverage/default/30.spi_device_upload.2719337874
Short name T213
Test name
Test status
Simulation time 287784655 ps
CPU time 6.62 seconds
Started Dec 27 01:34:10 PM PST 23
Finished Dec 27 01:34:17 PM PST 23
Peak memory 243612 kb
Host smart-dfae5b0b-8355-42d2-83d2-dd50d9fb62a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719337874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2719337874
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_abort.3692788884
Short name T1060
Test name
Test status
Simulation time 25373019 ps
CPU time 0.73 seconds
Started Dec 27 01:33:39 PM PST 23
Finished Dec 27 01:33:41 PM PST 23
Peak memory 206672 kb
Host smart-6a16a348-7851-4628-a656-e170cf92eb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692788884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_abort.3692788884
Directory /workspace/31.spi_device_abort/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3930101272
Short name T1487
Test name
Test status
Simulation time 20333312 ps
CPU time 0.7 seconds
Started Dec 27 01:33:39 PM PST 23
Finished Dec 27 01:33:41 PM PST 23
Peak memory 206408 kb
Host smart-51d006b6-2efb-4a30-acba-5a89a0e8bbae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930101272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3930101272
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_bit_transfer.2284519742
Short name T1362
Test name
Test status
Simulation time 824667007 ps
CPU time 2.47 seconds
Started Dec 27 01:33:34 PM PST 23
Finished Dec 27 01:33:38 PM PST 23
Peak memory 216816 kb
Host smart-43fcdca6-cdf2-475f-9c63-b48ed932a41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284519742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_bit_transfer.2284519742
Directory /workspace/31.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/31.spi_device_byte_transfer.2465916637
Short name T1730
Test name
Test status
Simulation time 246272780 ps
CPU time 2.5 seconds
Started Dec 27 01:33:41 PM PST 23
Finished Dec 27 01:33:44 PM PST 23
Peak memory 216752 kb
Host smart-20123994-7942-4195-ba7b-01f9132bf3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465916637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_byte_transfer.2465916637
Directory /workspace/31.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1001819820
Short name T47
Test name
Test status
Simulation time 609500736 ps
CPU time 6.46 seconds
Started Dec 27 01:33:54 PM PST 23
Finished Dec 27 01:34:01 PM PST 23
Peak memory 237440 kb
Host smart-b59640b6-c84f-447e-9602-e89ce9105d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001819820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1001819820
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1979641302
Short name T790
Test name
Test status
Simulation time 63580171 ps
CPU time 0.75 seconds
Started Dec 27 01:33:49 PM PST 23
Finished Dec 27 01:33:51 PM PST 23
Peak memory 206580 kb
Host smart-27cc8512-3933-4bcd-97ca-19b917849306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979641302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1979641302
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_dummy_item_extra_dly.2107222241
Short name T631
Test name
Test status
Simulation time 102864436129 ps
CPU time 436.29 seconds
Started Dec 27 01:33:42 PM PST 23
Finished Dec 27 01:40:59 PM PST 23
Peak memory 249012 kb
Host smart-308e22dd-b8b3-4f02-a28b-23ae9d1e2ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107222241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_dummy_item_extra_dly.2107222241
Directory /workspace/31.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/31.spi_device_extreme_fifo_size.2260455513
Short name T1169
Test name
Test status
Simulation time 86766605628 ps
CPU time 4036.79 seconds
Started Dec 27 01:34:03 PM PST 23
Finished Dec 27 02:41:21 PM PST 23
Peak memory 222308 kb
Host smart-b6bf198e-ddbc-4446-8140-affe83464bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260455513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_extreme_fifo_size.2260455513
Directory /workspace/31.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/31.spi_device_fifo_full.2968391568
Short name T1637
Test name
Test status
Simulation time 33442666400 ps
CPU time 963.82 seconds
Started Dec 27 01:33:56 PM PST 23
Finished Dec 27 01:50:01 PM PST 23
Peak memory 300492 kb
Host smart-6bfcb3fa-a408-4526-8350-541a44d12733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968391568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_fifo_full.2968391568
Directory /workspace/31.spi_device_fifo_full/latest

Test location /workspace/coverage/default/31.spi_device_fifo_underflow_overflow.595523700
Short name T69
Test name
Test status
Simulation time 12087798364 ps
CPU time 168.67 seconds
Started Dec 27 01:33:56 PM PST 23
Finished Dec 27 01:36:46 PM PST 23
Peak memory 360820 kb
Host smart-408a918c-d31a-46e6-a83f-484221c17152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595523700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_fifo_underflow_overfl
ow.595523700
Directory /workspace/31.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.4159114934
Short name T1289
Test name
Test status
Simulation time 3614515305 ps
CPU time 22.28 seconds
Started Dec 27 01:34:00 PM PST 23
Finished Dec 27 01:34:23 PM PST 23
Peak memory 241416 kb
Host smart-1e1d887b-2e8a-4ac7-8980-aa4def9a5a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159114934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.4159114934
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2715075153
Short name T1409
Test name
Test status
Simulation time 1201631447 ps
CPU time 11.33 seconds
Started Dec 27 01:34:11 PM PST 23
Finished Dec 27 01:34:23 PM PST 23
Peak memory 241388 kb
Host smart-ce074955-ffc7-4838-aa79-de8370f9d26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715075153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2715075153
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2492358985
Short name T116
Test name
Test status
Simulation time 8480592390 ps
CPU time 22.46 seconds
Started Dec 27 01:33:55 PM PST 23
Finished Dec 27 01:34:18 PM PST 23
Peak memory 231744 kb
Host smart-c6fd6613-4415-4532-80c4-dc40b1c9d504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492358985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2492358985
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4054469517
Short name T1301
Test name
Test status
Simulation time 602012199 ps
CPU time 4.39 seconds
Started Dec 27 01:33:51 PM PST 23
Finished Dec 27 01:33:57 PM PST 23
Peak memory 220968 kb
Host smart-63971bd2-2d39-4306-89d8-5717306bc2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054469517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4054469517
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_intr.3523088910
Short name T1723
Test name
Test status
Simulation time 9934308125 ps
CPU time 39.78 seconds
Started Dec 27 01:34:17 PM PST 23
Finished Dec 27 01:34:57 PM PST 23
Peak memory 233368 kb
Host smart-6e68c90b-eb79-4c03-818c-90e74a0ef9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523088910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intr.3523088910
Directory /workspace/31.spi_device_intr/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2767500275
Short name T927
Test name
Test status
Simulation time 6303008173 ps
CPU time 12.44 seconds
Started Dec 27 01:33:58 PM PST 23
Finished Dec 27 01:34:11 PM PST 23
Peak memory 220800 kb
Host smart-448a781e-e6c0-4ac1-a372-a8a285ff6624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767500275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2767500275
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2156230666
Short name T1210
Test name
Test status
Simulation time 1510042112 ps
CPU time 8.49 seconds
Started Dec 27 01:33:54 PM PST 23
Finished Dec 27 01:34:03 PM PST 23
Peak memory 218156 kb
Host smart-13e06420-4e82-4a65-8b0e-8aaeaecccee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156230666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2156230666
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3225854894
Short name T1659
Test name
Test status
Simulation time 1995505651 ps
CPU time 8.85 seconds
Started Dec 27 01:33:34 PM PST 23
Finished Dec 27 01:33:44 PM PST 23
Peak memory 219872 kb
Host smart-89dc1b6e-52bb-4bad-97d1-b4cecaa77abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225854894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3225854894
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_perf.4120134386
Short name T654
Test name
Test status
Simulation time 45333104943 ps
CPU time 1301.59 seconds
Started Dec 27 01:33:46 PM PST 23
Finished Dec 27 01:55:29 PM PST 23
Peak memory 256652 kb
Host smart-4f670752-0f96-4d77-bc91-b5e388a87f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120134386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_perf.4120134386
Directory /workspace/31.spi_device_perf/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1486929742
Short name T870
Test name
Test status
Simulation time 466346586 ps
CPU time 4.11 seconds
Started Dec 27 01:34:03 PM PST 23
Finished Dec 27 01:34:08 PM PST 23
Peak memory 235632 kb
Host smart-b24df450-1697-43dd-8dcf-ff07ac2578c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1486929742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1486929742
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_rx_async_fifo_reset.3112725641
Short name T1146
Test name
Test status
Simulation time 54799662 ps
CPU time 0.83 seconds
Started Dec 27 01:34:00 PM PST 23
Finished Dec 27 01:34:02 PM PST 23
Peak memory 208444 kb
Host smart-3f169140-d6f8-4af3-96dd-a1e1b00f8180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112725641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_rx_async_fifo_reset.3112725641
Directory /workspace/31.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/31.spi_device_rx_timeout.1832810105
Short name T1471
Test name
Test status
Simulation time 670046676 ps
CPU time 6.26 seconds
Started Dec 27 01:34:10 PM PST 23
Finished Dec 27 01:34:17 PM PST 23
Peak memory 216880 kb
Host smart-cc1b03a1-f158-48d9-86e8-0407eab5c9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832810105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_rx_timeout.1832810105
Directory /workspace/31.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/31.spi_device_smoke.2384032120
Short name T700
Test name
Test status
Simulation time 17474836 ps
CPU time 0.97 seconds
Started Dec 27 01:33:49 PM PST 23
Finished Dec 27 01:33:51 PM PST 23
Peak memory 208256 kb
Host smart-22624695-ca11-48ed-bc57-a8dcb5a42dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384032120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_smoke.2384032120
Directory /workspace/31.spi_device_smoke/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1250926111
Short name T211
Test name
Test status
Simulation time 91129437212 ps
CPU time 620.78 seconds
Started Dec 27 01:33:44 PM PST 23
Finished Dec 27 01:44:05 PM PST 23
Peak memory 288116 kb
Host smart-df918ba2-35cf-4811-a431-b3d17df3bf17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250926111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1250926111
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.569525853
Short name T662
Test name
Test status
Simulation time 13493947619 ps
CPU time 55.66 seconds
Started Dec 27 01:33:31 PM PST 23
Finished Dec 27 01:34:28 PM PST 23
Peak memory 216812 kb
Host smart-de67306d-b79e-48aa-9d74-e4ce41e303ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569525853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.569525853
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1106321218
Short name T515
Test name
Test status
Simulation time 1977438493 ps
CPU time 5.78 seconds
Started Dec 27 01:33:29 PM PST 23
Finished Dec 27 01:33:35 PM PST 23
Peak memory 216740 kb
Host smart-05098f6e-da62-46a0-ba30-67531c5f64fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106321218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1106321218
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3852484450
Short name T823
Test name
Test status
Simulation time 142407712 ps
CPU time 6.12 seconds
Started Dec 27 01:33:33 PM PST 23
Finished Dec 27 01:33:40 PM PST 23
Peak memory 216792 kb
Host smart-68177124-637c-443f-bf7e-6fc9fc880514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852484450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3852484450
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3147036692
Short name T607
Test name
Test status
Simulation time 47396180 ps
CPU time 0.76 seconds
Started Dec 27 01:33:39 PM PST 23
Finished Dec 27 01:33:42 PM PST 23
Peak memory 206952 kb
Host smart-c2d048e2-7f38-47dc-ba7c-ad8173e376a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147036692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3147036692
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_tx_async_fifo_reset.3927486316
Short name T675
Test name
Test status
Simulation time 110860033 ps
CPU time 0.78 seconds
Started Dec 27 01:33:33 PM PST 23
Finished Dec 27 01:33:35 PM PST 23
Peak memory 208420 kb
Host smart-b7bc7978-6283-46eb-9f87-0083f6b7e957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927486316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tx_async_fifo_reset.3927486316
Directory /workspace/31.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/31.spi_device_txrx.3846180395
Short name T1128
Test name
Test status
Simulation time 46060896655 ps
CPU time 376.55 seconds
Started Dec 27 01:33:54 PM PST 23
Finished Dec 27 01:40:12 PM PST 23
Peak memory 286724 kb
Host smart-cf81a44f-c7f7-49bb-92a3-fda609935020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846180395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_txrx.3846180395
Directory /workspace/31.spi_device_txrx/latest

Test location /workspace/coverage/default/31.spi_device_upload.3352417291
Short name T299
Test name
Test status
Simulation time 7035602548 ps
CPU time 23.42 seconds
Started Dec 27 01:33:43 PM PST 23
Finished Dec 27 01:34:07 PM PST 23
Peak memory 223280 kb
Host smart-c6917a66-7fbc-4f73-b7a9-85cc21da9875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352417291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3352417291
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_abort.122109740
Short name T957
Test name
Test status
Simulation time 29924698 ps
CPU time 0.75 seconds
Started Dec 27 01:34:00 PM PST 23
Finished Dec 27 01:34:01 PM PST 23
Peak memory 206668 kb
Host smart-7b1a4c89-d43e-4c15-b355-7ff84df61a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122109740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_abort.122109740
Directory /workspace/32.spi_device_abort/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.486258032
Short name T610
Test name
Test status
Simulation time 20630035 ps
CPU time 0.74 seconds
Started Dec 27 01:34:28 PM PST 23
Finished Dec 27 01:34:30 PM PST 23
Peak memory 206432 kb
Host smart-750641b5-ec08-4e97-b60b-51d0e3f04cdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486258032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.486258032
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_bit_transfer.941363979
Short name T1681
Test name
Test status
Simulation time 410929800 ps
CPU time 2.42 seconds
Started Dec 27 01:33:53 PM PST 23
Finished Dec 27 01:33:56 PM PST 23
Peak memory 216784 kb
Host smart-4b214c45-9e61-46f4-a1ef-c8c049f304fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941363979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_bit_transfer.941363979
Directory /workspace/32.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/32.spi_device_byte_transfer.814741368
Short name T1402
Test name
Test status
Simulation time 307214015 ps
CPU time 3.42 seconds
Started Dec 27 01:33:53 PM PST 23
Finished Dec 27 01:33:58 PM PST 23
Peak memory 216712 kb
Host smart-fc638faf-2f91-4f32-b95b-1ff60bf065be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814741368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_byte_transfer.814741368
Directory /workspace/32.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.4167093543
Short name T293
Test name
Test status
Simulation time 2004159295 ps
CPU time 8.13 seconds
Started Dec 27 01:34:12 PM PST 23
Finished Dec 27 01:34:21 PM PST 23
Peak memory 222320 kb
Host smart-862337a0-59a2-4338-adf4-be1d609b5571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167093543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.4167093543
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3435067127
Short name T1648
Test name
Test status
Simulation time 21925518 ps
CPU time 0.81 seconds
Started Dec 27 01:34:33 PM PST 23
Finished Dec 27 01:34:35 PM PST 23
Peak memory 207596 kb
Host smart-cd078abd-f8ae-4ca3-8bbd-3507c2989545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435067127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3435067127
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_dummy_item_extra_dly.1146260201
Short name T1359
Test name
Test status
Simulation time 82533819689 ps
CPU time 845.29 seconds
Started Dec 27 01:34:07 PM PST 23
Finished Dec 27 01:48:13 PM PST 23
Peak memory 247304 kb
Host smart-82b6b6b9-89a2-4b28-94ce-45055660d47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146260201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_dummy_item_extra_dly.1146260201
Directory /workspace/32.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/32.spi_device_extreme_fifo_size.3538476466
Short name T1004
Test name
Test status
Simulation time 3744219901 ps
CPU time 19.17 seconds
Started Dec 27 01:34:06 PM PST 23
Finished Dec 27 01:34:25 PM PST 23
Peak memory 224684 kb
Host smart-8e908f02-571d-43e3-8e4f-1adebd7e4884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538476466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_extreme_fifo_size.3538476466
Directory /workspace/32.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/32.spi_device_fifo_full.4102083956
Short name T871
Test name
Test status
Simulation time 155238470711 ps
CPU time 1960.37 seconds
Started Dec 27 01:33:54 PM PST 23
Finished Dec 27 02:06:35 PM PST 23
Peak memory 250888 kb
Host smart-b35d2674-5f56-44f4-a65a-f21035cff14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102083956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_fifo_full.4102083956
Directory /workspace/32.spi_device_fifo_full/latest

Test location /workspace/coverage/default/32.spi_device_fifo_underflow_overflow.1200219517
Short name T1085
Test name
Test status
Simulation time 32153107595 ps
CPU time 261.2 seconds
Started Dec 27 01:33:56 PM PST 23
Finished Dec 27 01:38:18 PM PST 23
Peak memory 412124 kb
Host smart-2a5183c5-2b41-4f2f-a2fd-ec5a056302fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200219517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_fifo_underflow_overf
low.1200219517
Directory /workspace/32.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3929696935
Short name T1437
Test name
Test status
Simulation time 52631178197 ps
CPU time 248.26 seconds
Started Dec 27 01:34:08 PM PST 23
Finished Dec 27 01:38:17 PM PST 23
Peak memory 266904 kb
Host smart-8c438fc1-daf9-4a83-891d-817f48238779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929696935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3929696935
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2966671150
Short name T336
Test name
Test status
Simulation time 54833066068 ps
CPU time 171.52 seconds
Started Dec 27 01:34:28 PM PST 23
Finished Dec 27 01:37:20 PM PST 23
Peak memory 266836 kb
Host smart-4c662d60-b013-4797-a92c-d942e629660d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966671150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2966671150
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1047842365
Short name T1160
Test name
Test status
Simulation time 730654728 ps
CPU time 4.95 seconds
Started Dec 27 01:33:56 PM PST 23
Finished Dec 27 01:34:02 PM PST 23
Peak memory 238536 kb
Host smart-b686d695-8932-48bc-8e31-81880acf6bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047842365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1047842365
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_intr.28446438
Short name T557
Test name
Test status
Simulation time 11234492702 ps
CPU time 12.08 seconds
Started Dec 27 01:33:58 PM PST 23
Finished Dec 27 01:34:11 PM PST 23
Peak memory 218168 kb
Host smart-42829607-347d-43ea-aecf-ae684cddc608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28446438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intr.28446438
Directory /workspace/32.spi_device_intr/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.526918374
Short name T1136
Test name
Test status
Simulation time 1711571082 ps
CPU time 3.33 seconds
Started Dec 27 01:33:54 PM PST 23
Finished Dec 27 01:33:58 PM PST 23
Peak memory 219596 kb
Host smart-d6afd223-0a5e-4cd5-bc10-b14b143ed235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526918374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.526918374
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.4063662934
Short name T323
Test name
Test status
Simulation time 12570524867 ps
CPU time 21.26 seconds
Started Dec 27 01:33:50 PM PST 23
Finished Dec 27 01:34:13 PM PST 23
Peak memory 238700 kb
Host smart-c00b2dea-419b-4cb1-99a7-d6f4cc06674c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063662934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.4063662934
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1272085575
Short name T1674
Test name
Test status
Simulation time 530640084 ps
CPU time 3.34 seconds
Started Dec 27 01:33:49 PM PST 23
Finished Dec 27 01:33:54 PM PST 23
Peak memory 218600 kb
Host smart-696f73ce-a4ac-4713-8419-08a6b063bbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272085575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1272085575
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_perf.947725518
Short name T1206
Test name
Test status
Simulation time 18836474570 ps
CPU time 1288.38 seconds
Started Dec 27 01:34:16 PM PST 23
Finished Dec 27 01:55:45 PM PST 23
Peak memory 265964 kb
Host smart-b748adec-ca61-4dea-819f-8a729e207f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947725518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_perf.947725518
Directory /workspace/32.spi_device_perf/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2564115890
Short name T901
Test name
Test status
Simulation time 214845568 ps
CPU time 3.67 seconds
Started Dec 27 01:34:00 PM PST 23
Finished Dec 27 01:34:05 PM PST 23
Peak memory 220568 kb
Host smart-1602c8ab-5a79-4a74-b999-37ed315271d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2564115890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2564115890
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_rx_async_fifo_reset.2183779173
Short name T776
Test name
Test status
Simulation time 49484726 ps
CPU time 0.88 seconds
Started Dec 27 01:33:53 PM PST 23
Finished Dec 27 01:33:55 PM PST 23
Peak memory 208440 kb
Host smart-27ea0a23-6b7e-49d2-abbc-4ce45f7ef674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183779173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_rx_async_fifo_reset.2183779173
Directory /workspace/32.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/32.spi_device_rx_timeout.1620835133
Short name T580
Test name
Test status
Simulation time 510299753 ps
CPU time 5 seconds
Started Dec 27 01:34:02 PM PST 23
Finished Dec 27 01:34:08 PM PST 23
Peak memory 216788 kb
Host smart-9772017e-0561-40ef-83dd-0199b967a4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620835133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_rx_timeout.1620835133
Directory /workspace/32.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/32.spi_device_smoke.562204811
Short name T1061
Test name
Test status
Simulation time 18839950 ps
CPU time 0.9 seconds
Started Dec 27 01:33:49 PM PST 23
Finished Dec 27 01:33:51 PM PST 23
Peak memory 207908 kb
Host smart-8e626476-eeb2-49ac-bcbc-027372840940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562204811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_smoke.562204811
Directory /workspace/32.spi_device_smoke/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.895924601
Short name T1696
Test name
Test status
Simulation time 10409627915 ps
CPU time 42.23 seconds
Started Dec 27 01:33:50 PM PST 23
Finished Dec 27 01:34:33 PM PST 23
Peak memory 216936 kb
Host smart-0aad1bea-6ef4-4f8c-9bb1-55082d6d8379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895924601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.895924601
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.306951598
Short name T1439
Test name
Test status
Simulation time 182657637 ps
CPU time 1.15 seconds
Started Dec 27 01:33:55 PM PST 23
Finished Dec 27 01:33:58 PM PST 23
Peak memory 207444 kb
Host smart-8aec8b85-6726-420b-b96f-b3fcc5d7b92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306951598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.306951598
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1924005705
Short name T1466
Test name
Test status
Simulation time 68951419 ps
CPU time 1.63 seconds
Started Dec 27 01:34:08 PM PST 23
Finished Dec 27 01:34:11 PM PST 23
Peak memory 216788 kb
Host smart-0533136b-b1f2-4b34-9e49-98724938ecc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924005705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1924005705
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.829193035
Short name T806
Test name
Test status
Simulation time 279287804 ps
CPU time 1.1 seconds
Started Dec 27 01:33:49 PM PST 23
Finished Dec 27 01:33:51 PM PST 23
Peak memory 206980 kb
Host smart-f2b1fd4a-7981-428f-92ca-c573b2a6c164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829193035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.829193035
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_tx_async_fifo_reset.3773309900
Short name T683
Test name
Test status
Simulation time 113510458 ps
CPU time 0.77 seconds
Started Dec 27 01:33:52 PM PST 23
Finished Dec 27 01:33:54 PM PST 23
Peak memory 208416 kb
Host smart-903effef-5f81-4386-bff7-4f287b2c0f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773309900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tx_async_fifo_reset.3773309900
Directory /workspace/32.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/32.spi_device_txrx.3919392456
Short name T1277
Test name
Test status
Simulation time 18485541243 ps
CPU time 136.31 seconds
Started Dec 27 01:33:58 PM PST 23
Finished Dec 27 01:36:15 PM PST 23
Peak memory 264996 kb
Host smart-4f39f412-4a74-4f52-aa41-4e27ba8fee56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919392456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_txrx.3919392456
Directory /workspace/32.spi_device_txrx/latest

Test location /workspace/coverage/default/32.spi_device_upload.1385977468
Short name T304
Test name
Test status
Simulation time 5144983955 ps
CPU time 6.35 seconds
Started Dec 27 01:33:48 PM PST 23
Finished Dec 27 01:33:56 PM PST 23
Peak memory 236244 kb
Host smart-df79e925-e78b-4d50-9bcf-dcbc76291570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385977468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1385977468
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_abort.2384086157
Short name T1042
Test name
Test status
Simulation time 25117986 ps
CPU time 0.79 seconds
Started Dec 27 01:34:12 PM PST 23
Finished Dec 27 01:34:13 PM PST 23
Peak memory 206588 kb
Host smart-a1f5ad89-e784-4ef6-ae36-2aab161a80a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384086157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_abort.2384086157
Directory /workspace/33.spi_device_abort/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1204883782
Short name T1733
Test name
Test status
Simulation time 46189583 ps
CPU time 0.71 seconds
Started Dec 27 01:35:40 PM PST 23
Finished Dec 27 01:35:42 PM PST 23
Peak memory 206420 kb
Host smart-6a22c334-74e6-467d-87de-cbd96dc18f84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204883782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1204883782
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_bit_transfer.2642358682
Short name T1302
Test name
Test status
Simulation time 1165021050 ps
CPU time 2.4 seconds
Started Dec 27 01:34:26 PM PST 23
Finished Dec 27 01:34:29 PM PST 23
Peak memory 216796 kb
Host smart-d52e09d1-a6f5-4e52-9c10-85940e4469c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642358682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_bit_transfer.2642358682
Directory /workspace/33.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/33.spi_device_byte_transfer.1370246551
Short name T1742
Test name
Test status
Simulation time 131524479 ps
CPU time 2.6 seconds
Started Dec 27 01:34:21 PM PST 23
Finished Dec 27 01:34:24 PM PST 23
Peak memory 216756 kb
Host smart-feed444d-41e1-4ae4-ba8c-95e028eb0a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370246551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_byte_transfer.1370246551
Directory /workspace/33.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1400197739
Short name T920
Test name
Test status
Simulation time 132044109 ps
CPU time 3 seconds
Started Dec 27 01:35:47 PM PST 23
Finished Dec 27 01:35:51 PM PST 23
Peak memory 218836 kb
Host smart-b787cca5-fb15-4a82-94db-7674cf09f949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400197739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1400197739
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2655237353
Short name T985
Test name
Test status
Simulation time 52879702 ps
CPU time 0.76 seconds
Started Dec 27 01:34:18 PM PST 23
Finished Dec 27 01:34:19 PM PST 23
Peak memory 207584 kb
Host smart-4c56a409-a8a8-44c7-9d32-118ff68a047c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655237353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2655237353
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_dummy_item_extra_dly.12408218
Short name T646
Test name
Test status
Simulation time 31250762052 ps
CPU time 193.37 seconds
Started Dec 27 01:34:55 PM PST 23
Finished Dec 27 01:38:09 PM PST 23
Peak memory 272292 kb
Host smart-66607b0b-667a-42c1-836a-192e9035daba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12408218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_dummy_item_extra_dly.12408218
Directory /workspace/33.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/33.spi_device_extreme_fifo_size.1672396192
Short name T278
Test name
Test status
Simulation time 319107910672 ps
CPU time 990.7 seconds
Started Dec 27 01:35:45 PM PST 23
Finished Dec 27 01:52:17 PM PST 23
Peak memory 220108 kb
Host smart-f6c8901c-eb70-4a6e-afad-053f6bc59a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672396192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_extreme_fifo_size.1672396192
Directory /workspace/33.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/33.spi_device_fifo_full.3380948049
Short name T721
Test name
Test status
Simulation time 259212122889 ps
CPU time 1059.78 seconds
Started Dec 27 01:34:36 PM PST 23
Finished Dec 27 01:52:16 PM PST 23
Peak memory 290528 kb
Host smart-d035fbc7-24f3-449a-88a1-e5c14810916f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380948049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_fifo_full.3380948049
Directory /workspace/33.spi_device_fifo_full/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2522804022
Short name T804
Test name
Test status
Simulation time 30540031042 ps
CPU time 44.61 seconds
Started Dec 27 01:35:12 PM PST 23
Finished Dec 27 01:35:59 PM PST 23
Peak memory 237968 kb
Host smart-2efc04d1-8817-424e-bd1b-d73902163150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522804022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2522804022
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1929055716
Short name T79
Test name
Test status
Simulation time 7845361262 ps
CPU time 83.03 seconds
Started Dec 27 01:36:03 PM PST 23
Finished Dec 27 01:37:27 PM PST 23
Peak memory 261936 kb
Host smart-d44db54a-a1ef-4702-8be1-0311c3ec5be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929055716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1929055716
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2135741594
Short name T334
Test name
Test status
Simulation time 55845791995 ps
CPU time 130.51 seconds
Started Dec 27 01:35:45 PM PST 23
Finished Dec 27 01:37:56 PM PST 23
Peak memory 266104 kb
Host smart-a6c2867d-3d46-4d91-b7be-ab6394a18e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135741594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2135741594
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1035156522
Short name T44
Test name
Test status
Simulation time 5991366651 ps
CPU time 14.55 seconds
Started Dec 27 01:35:40 PM PST 23
Finished Dec 27 01:35:56 PM PST 23
Peak memory 241588 kb
Host smart-6f9b6442-4024-4b4b-8bd8-3c734f7a254b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035156522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1035156522
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.45392790
Short name T893
Test name
Test status
Simulation time 88176347 ps
CPU time 3.06 seconds
Started Dec 27 01:34:24 PM PST 23
Finished Dec 27 01:34:28 PM PST 23
Peak memory 218376 kb
Host smart-f43d171f-d385-442b-9c46-61039ca167a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45392790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.45392790
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_intr.2970864351
Short name T1196
Test name
Test status
Simulation time 50516654686 ps
CPU time 52.08 seconds
Started Dec 27 01:35:02 PM PST 23
Finished Dec 27 01:36:01 PM PST 23
Peak memory 224980 kb
Host smart-e2d6053f-bc79-4ce0-b7d6-41dd64303d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970864351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intr.2970864351
Directory /workspace/33.spi_device_intr/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.940564007
Short name T310
Test name
Test status
Simulation time 13154191842 ps
CPU time 40.79 seconds
Started Dec 27 01:34:58 PM PST 23
Finished Dec 27 01:35:39 PM PST 23
Peak memory 233252 kb
Host smart-91f8e9a0-32b8-420b-83a1-0779f516c4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940564007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.940564007
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1121374554
Short name T37
Test name
Test status
Simulation time 4292806202 ps
CPU time 10.28 seconds
Started Dec 27 01:34:33 PM PST 23
Finished Dec 27 01:34:44 PM PST 23
Peak memory 238508 kb
Host smart-8ca3c539-2966-49b2-90dc-f583468eaf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121374554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1121374554
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.370384577
Short name T941
Test name
Test status
Simulation time 895367086 ps
CPU time 5.16 seconds
Started Dec 27 01:34:12 PM PST 23
Finished Dec 27 01:34:17 PM PST 23
Peak memory 238560 kb
Host smart-b3f6b572-7055-439e-b54b-ac7dca91ab59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370384577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.370384577
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_perf.2735284284
Short name T1218
Test name
Test status
Simulation time 46401545882 ps
CPU time 672.36 seconds
Started Dec 27 01:35:04 PM PST 23
Finished Dec 27 01:46:21 PM PST 23
Peak memory 265976 kb
Host smart-158cdbef-15a9-4026-a0c2-7dd638dfbf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735284284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_perf.2735284284
Directory /workspace/33.spi_device_perf/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3108265928
Short name T538
Test name
Test status
Simulation time 188827169 ps
CPU time 3.37 seconds
Started Dec 27 01:34:29 PM PST 23
Finished Dec 27 01:34:33 PM PST 23
Peak memory 219980 kb
Host smart-41af8f27-9a54-4144-98ea-5ab44105ecae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3108265928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3108265928
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_rx_timeout.2383322888
Short name T1589
Test name
Test status
Simulation time 883422945 ps
CPU time 4.99 seconds
Started Dec 27 01:34:31 PM PST 23
Finished Dec 27 01:34:37 PM PST 23
Peak memory 216784 kb
Host smart-23120f14-23db-4697-8a64-2767f9029d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383322888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_rx_timeout.2383322888
Directory /workspace/33.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/33.spi_device_smoke.2982085281
Short name T1618
Test name
Test status
Simulation time 32421803 ps
CPU time 1.01 seconds
Started Dec 27 01:35:00 PM PST 23
Finished Dec 27 01:35:02 PM PST 23
Peak memory 208168 kb
Host smart-b6e471a3-5885-4f9c-8db5-b84f1b77f917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982085281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_smoke.2982085281
Directory /workspace/33.spi_device_smoke/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.4067222885
Short name T331
Test name
Test status
Simulation time 197257039172 ps
CPU time 668.5 seconds
Started Dec 27 01:36:10 PM PST 23
Finished Dec 27 01:47:19 PM PST 23
Peak memory 347852 kb
Host smart-572e3bb5-c83c-4d8b-a6f3-2391f103ef50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067222885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.4067222885
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.22297260
Short name T1135
Test name
Test status
Simulation time 3292847996 ps
CPU time 13.16 seconds
Started Dec 27 01:34:06 PM PST 23
Finished Dec 27 01:34:20 PM PST 23
Peak memory 220640 kb
Host smart-5f506a99-9550-43c4-8830-b7fa8b73ad49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22297260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.22297260
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1120895788
Short name T1093
Test name
Test status
Simulation time 36715046400 ps
CPU time 30.45 seconds
Started Dec 27 01:34:19 PM PST 23
Finished Dec 27 01:34:50 PM PST 23
Peak memory 218900 kb
Host smart-65124102-4e8a-4def-a9dc-ef18bb87b27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120895788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1120895788
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2321812483
Short name T1728
Test name
Test status
Simulation time 33933319 ps
CPU time 0.74 seconds
Started Dec 27 01:34:36 PM PST 23
Finished Dec 27 01:34:38 PM PST 23
Peak memory 206916 kb
Host smart-b3b5174a-166e-4554-b70f-8e62c43c186d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321812483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2321812483
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tx_async_fifo_reset.3027179003
Short name T1224
Test name
Test status
Simulation time 44032698 ps
CPU time 0.75 seconds
Started Dec 27 01:34:12 PM PST 23
Finished Dec 27 01:34:14 PM PST 23
Peak memory 208376 kb
Host smart-4768cfbb-01d8-4715-88e0-3d832fb66c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027179003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tx_async_fifo_reset.3027179003
Directory /workspace/33.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/33.spi_device_txrx.117570873
Short name T693
Test name
Test status
Simulation time 78257403860 ps
CPU time 157.23 seconds
Started Dec 27 01:34:33 PM PST 23
Finished Dec 27 01:37:11 PM PST 23
Peak memory 285828 kb
Host smart-a7c56862-32a3-4669-884c-933d539a7149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117570873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_txrx.117570873
Directory /workspace/33.spi_device_txrx/latest

Test location /workspace/coverage/default/33.spi_device_upload.2474155598
Short name T694
Test name
Test status
Simulation time 44210008015 ps
CPU time 26.91 seconds
Started Dec 27 01:35:25 PM PST 23
Finished Dec 27 01:35:56 PM PST 23
Peak memory 222636 kb
Host smart-d2194c5b-839a-43af-8905-0b00bae13336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474155598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2474155598
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_abort.1461353613
Short name T698
Test name
Test status
Simulation time 12525845 ps
CPU time 0.76 seconds
Started Dec 27 01:34:37 PM PST 23
Finished Dec 27 01:34:38 PM PST 23
Peak memory 206588 kb
Host smart-cf48b004-97e5-4748-af8a-119afc39c3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461353613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_abort.1461353613
Directory /workspace/34.spi_device_abort/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4238533634
Short name T1304
Test name
Test status
Simulation time 36816401 ps
CPU time 0.71 seconds
Started Dec 27 01:34:38 PM PST 23
Finished Dec 27 01:34:39 PM PST 23
Peak memory 206508 kb
Host smart-4f27acfa-33ee-4c21-a8de-2d7dde378b05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238533634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4238533634
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_bit_transfer.1415335110
Short name T892
Test name
Test status
Simulation time 267867714 ps
CPU time 2.38 seconds
Started Dec 27 01:34:29 PM PST 23
Finished Dec 27 01:34:32 PM PST 23
Peak memory 216760 kb
Host smart-5e7e9711-8cea-4503-9b4e-44acc9dcabe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415335110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_bit_transfer.1415335110
Directory /workspace/34.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/34.spi_device_byte_transfer.3874501229
Short name T775
Test name
Test status
Simulation time 86740199 ps
CPU time 2.37 seconds
Started Dec 27 01:35:00 PM PST 23
Finished Dec 27 01:35:04 PM PST 23
Peak memory 216792 kb
Host smart-4c3535ef-cb0f-421b-81e1-b35e8c647a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874501229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_byte_transfer.3874501229
Directory /workspace/34.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3783625478
Short name T1138
Test name
Test status
Simulation time 1008536826 ps
CPU time 4.53 seconds
Started Dec 27 01:35:40 PM PST 23
Finished Dec 27 01:35:45 PM PST 23
Peak memory 221132 kb
Host smart-558536d2-4b1e-424e-a2f1-1c2d4cd3e07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783625478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3783625478
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1153160973
Short name T1459
Test name
Test status
Simulation time 21514931 ps
CPU time 0.82 seconds
Started Dec 27 01:35:47 PM PST 23
Finished Dec 27 01:35:48 PM PST 23
Peak memory 207500 kb
Host smart-b896a853-01a5-4de4-99ee-e53c99ce4ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153160973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1153160973
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_dummy_item_extra_dly.4018968701
Short name T989
Test name
Test status
Simulation time 73930431334 ps
CPU time 370.56 seconds
Started Dec 27 01:34:56 PM PST 23
Finished Dec 27 01:41:07 PM PST 23
Peak memory 300388 kb
Host smart-8291449b-054d-4b48-9b70-ea2ed7f6fef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018968701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_dummy_item_extra_dly.4018968701
Directory /workspace/34.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/34.spi_device_extreme_fifo_size.2228883691
Short name T966
Test name
Test status
Simulation time 237809711681 ps
CPU time 1055.92 seconds
Started Dec 27 01:34:40 PM PST 23
Finished Dec 27 01:52:16 PM PST 23
Peak memory 219164 kb
Host smart-929ca9b5-09ad-41ee-9966-82131a60285d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228883691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_extreme_fifo_size.2228883691
Directory /workspace/34.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/34.spi_device_fifo_underflow_overflow.940854349
Short name T1475
Test name
Test status
Simulation time 37683830034 ps
CPU time 195.12 seconds
Started Dec 27 01:34:35 PM PST 23
Finished Dec 27 01:37:51 PM PST 23
Peak memory 348140 kb
Host smart-abacd5c4-da77-4c28-9a7e-8bd37452347b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940854349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_fifo_underflow_overfl
ow.940854349
Directory /workspace/34.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.462269303
Short name T964
Test name
Test status
Simulation time 18822408931 ps
CPU time 29.99 seconds
Started Dec 27 01:34:51 PM PST 23
Finished Dec 27 01:35:22 PM PST 23
Peak memory 240548 kb
Host smart-c74de23d-9b04-4bca-a6b7-fc0320344cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462269303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.462269303
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1830938007
Short name T1007
Test name
Test status
Simulation time 5661865685 ps
CPU time 69.35 seconds
Started Dec 27 01:35:01 PM PST 23
Finished Dec 27 01:36:11 PM PST 23
Peak memory 249760 kb
Host smart-810cefde-bb33-4d10-b2ab-676c6439f933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830938007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1830938007
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2743527972
Short name T912
Test name
Test status
Simulation time 140982481433 ps
CPU time 289.82 seconds
Started Dec 27 01:35:00 PM PST 23
Finished Dec 27 01:39:51 PM PST 23
Peak memory 266156 kb
Host smart-fb022f6e-7c7b-4dd2-aac5-87622d428cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743527972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2743527972
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3237457446
Short name T193
Test name
Test status
Simulation time 2445359475 ps
CPU time 8.14 seconds
Started Dec 27 01:35:56 PM PST 23
Finished Dec 27 01:36:05 PM PST 23
Peak memory 230276 kb
Host smart-6bd3861d-8a21-4fa0-ae55-41c8d8467230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237457446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3237457446
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3204577560
Short name T1027
Test name
Test status
Simulation time 2313957560 ps
CPU time 11.17 seconds
Started Dec 27 01:35:05 PM PST 23
Finished Dec 27 01:35:20 PM PST 23
Peak memory 223212 kb
Host smart-c3ae0df5-0729-4cdd-8a8b-936a13bee213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204577560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3204577560
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_intr.3253547281
Short name T1022
Test name
Test status
Simulation time 48513366790 ps
CPU time 58.65 seconds
Started Dec 27 01:35:00 PM PST 23
Finished Dec 27 01:36:00 PM PST 23
Peak memory 231572 kb
Host smart-ced371bb-a7bf-4a2f-8046-30a3a09531d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253547281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intr.3253547281
Directory /workspace/34.spi_device_intr/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3002191317
Short name T1129
Test name
Test status
Simulation time 1924611767 ps
CPU time 5.89 seconds
Started Dec 27 01:35:48 PM PST 23
Finished Dec 27 01:35:55 PM PST 23
Peak memory 224800 kb
Host smart-e9970548-7b55-4ed1-bc7e-8d7c072168c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002191317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3002191317
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3419921875
Short name T803
Test name
Test status
Simulation time 49380412568 ps
CPU time 35.88 seconds
Started Dec 27 01:35:00 PM PST 23
Finished Dec 27 01:35:37 PM PST 23
Peak memory 257824 kb
Host smart-a593d5f9-d0d0-4fae-bd18-6000ac107c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419921875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3419921875
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_perf.2896492685
Short name T1444
Test name
Test status
Simulation time 18248939735 ps
CPU time 140.41 seconds
Started Dec 27 01:35:30 PM PST 23
Finished Dec 27 01:37:53 PM PST 23
Peak memory 265856 kb
Host smart-8fbc1252-c6a3-4b02-a425-2b0aabf433e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896492685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_perf.2896492685
Directory /workspace/34.spi_device_perf/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.876244498
Short name T1633
Test name
Test status
Simulation time 2935698883 ps
CPU time 6.78 seconds
Started Dec 27 01:34:36 PM PST 23
Finished Dec 27 01:34:43 PM PST 23
Peak memory 234256 kb
Host smart-7e58d3c0-2dd4-44c8-bc79-8d23dfd2ea0d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=876244498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.876244498
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_rx_async_fifo_reset.3347294212
Short name T1718
Test name
Test status
Simulation time 59445475 ps
CPU time 0.9 seconds
Started Dec 27 01:34:28 PM PST 23
Finished Dec 27 01:34:30 PM PST 23
Peak memory 208420 kb
Host smart-bf5ed4cc-53c1-4ed0-aa74-227589ed1aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347294212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_rx_async_fifo_reset.3347294212
Directory /workspace/34.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/34.spi_device_rx_timeout.3786591278
Short name T1683
Test name
Test status
Simulation time 7214071652 ps
CPU time 6.35 seconds
Started Dec 27 01:34:32 PM PST 23
Finished Dec 27 01:34:39 PM PST 23
Peak memory 216756 kb
Host smart-5cd1ec55-78a4-4ed7-a5a4-fa353704223d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786591278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_rx_timeout.3786591278
Directory /workspace/34.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/34.spi_device_smoke.2597370543
Short name T1685
Test name
Test status
Simulation time 31987670 ps
CPU time 1.02 seconds
Started Dec 27 01:34:10 PM PST 23
Finished Dec 27 01:34:11 PM PST 23
Peak memory 208100 kb
Host smart-227880d2-de72-4dfb-9a17-8568d81fa17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597370543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_smoke.2597370543
Directory /workspace/34.spi_device_smoke/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3732045299
Short name T992
Test name
Test status
Simulation time 7612296374 ps
CPU time 100.54 seconds
Started Dec 27 01:34:24 PM PST 23
Finished Dec 27 01:36:06 PM PST 23
Peak memory 216908 kb
Host smart-1564adf7-4e7e-43b3-a0a7-80030e183a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732045299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3732045299
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3293105355
Short name T856
Test name
Test status
Simulation time 3929399304 ps
CPU time 7.71 seconds
Started Dec 27 01:34:36 PM PST 23
Finished Dec 27 01:34:45 PM PST 23
Peak memory 216852 kb
Host smart-1a0d67f0-c443-4393-b50b-06971c2218cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293105355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3293105355
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1197820849
Short name T1595
Test name
Test status
Simulation time 29700083 ps
CPU time 1.59 seconds
Started Dec 27 01:34:57 PM PST 23
Finished Dec 27 01:34:59 PM PST 23
Peak memory 216900 kb
Host smart-ae9708df-bdef-4351-856a-96e1893db6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197820849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1197820849
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3020137069
Short name T1342
Test name
Test status
Simulation time 524756638 ps
CPU time 0.93 seconds
Started Dec 27 01:34:35 PM PST 23
Finished Dec 27 01:34:36 PM PST 23
Peak memory 207104 kb
Host smart-e98d3a5f-f75b-487f-be85-28c9f5fd8481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020137069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3020137069
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_tx_async_fifo_reset.3246986060
Short name T1489
Test name
Test status
Simulation time 17120549 ps
CPU time 0.79 seconds
Started Dec 27 01:34:32 PM PST 23
Finished Dec 27 01:34:33 PM PST 23
Peak memory 208340 kb
Host smart-43baaba7-1572-4339-9d5e-8c80a91900a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246986060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tx_async_fifo_reset.3246986060
Directory /workspace/34.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/34.spi_device_txrx.1535118378
Short name T606
Test name
Test status
Simulation time 16920016427 ps
CPU time 155.89 seconds
Started Dec 27 01:34:36 PM PST 23
Finished Dec 27 01:37:13 PM PST 23
Peak memory 241280 kb
Host smart-01853833-bee6-42b1-b3f1-19ff6b7cf5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535118378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_txrx.1535118378
Directory /workspace/34.spi_device_txrx/latest

Test location /workspace/coverage/default/34.spi_device_upload.4172054734
Short name T313
Test name
Test status
Simulation time 18382323224 ps
CPU time 18.25 seconds
Started Dec 27 01:35:39 PM PST 23
Finished Dec 27 01:35:58 PM PST 23
Peak memory 227196 kb
Host smart-ab5c619f-85c6-489c-9c59-35bef0545694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172054734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4172054734
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_abort.3495402378
Short name T1584
Test name
Test status
Simulation time 14707420 ps
CPU time 0.72 seconds
Started Dec 27 01:36:03 PM PST 23
Finished Dec 27 01:36:05 PM PST 23
Peak memory 206668 kb
Host smart-d507b65f-173d-44de-ba6d-44ef4a0d6950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495402378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_abort.3495402378
Directory /workspace/35.spi_device_abort/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3737588270
Short name T1526
Test name
Test status
Simulation time 40269043 ps
CPU time 0.73 seconds
Started Dec 27 01:36:02 PM PST 23
Finished Dec 27 01:36:04 PM PST 23
Peak memory 206468 kb
Host smart-ceb51e76-a422-458a-aa25-6e7dccec74e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737588270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3737588270
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_bit_transfer.4115110554
Short name T1571
Test name
Test status
Simulation time 591797808 ps
CPU time 2.68 seconds
Started Dec 27 01:36:11 PM PST 23
Finished Dec 27 01:36:15 PM PST 23
Peak memory 216852 kb
Host smart-72394c05-862e-4944-ab0a-a823e68053ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115110554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_bit_transfer.4115110554
Directory /workspace/35.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/35.spi_device_byte_transfer.1811395709
Short name T731
Test name
Test status
Simulation time 538276248 ps
CPU time 2.94 seconds
Started Dec 27 01:35:53 PM PST 23
Finished Dec 27 01:35:57 PM PST 23
Peak memory 216792 kb
Host smart-fd4bb009-88cc-42f3-a889-a6abc932cd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811395709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_byte_transfer.1811395709
Directory /workspace/35.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1412692117
Short name T26
Test name
Test status
Simulation time 2083248425 ps
CPU time 5.58 seconds
Started Dec 27 01:35:35 PM PST 23
Finished Dec 27 01:35:41 PM PST 23
Peak memory 241452 kb
Host smart-323fd808-9611-4212-af4e-2e8ad1e7be28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412692117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1412692117
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.456555901
Short name T1176
Test name
Test status
Simulation time 59523135 ps
CPU time 0.82 seconds
Started Dec 27 01:35:38 PM PST 23
Finished Dec 27 01:35:41 PM PST 23
Peak memory 207464 kb
Host smart-40b8046f-6669-400a-9de5-196915616d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456555901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.456555901
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_dummy_item_extra_dly.2463096564
Short name T1186
Test name
Test status
Simulation time 194907255591 ps
CPU time 1556.16 seconds
Started Dec 27 01:35:05 PM PST 23
Finished Dec 27 02:01:06 PM PST 23
Peak memory 265928 kb
Host smart-2e973fb6-c0ef-45b7-b382-2f79f140d044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463096564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_dummy_item_extra_dly.2463096564
Directory /workspace/35.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/35.spi_device_extreme_fifo_size.79264888
Short name T1194
Test name
Test status
Simulation time 122063806315 ps
CPU time 946.85 seconds
Started Dec 27 01:35:28 PM PST 23
Finished Dec 27 01:51:16 PM PST 23
Peak memory 220088 kb
Host smart-d68d5b66-cf2f-4da5-8660-8d1548cd3245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79264888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_extreme_fifo_size.79264888
Directory /workspace/35.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/35.spi_device_fifo_full.203315811
Short name T851
Test name
Test status
Simulation time 165563183250 ps
CPU time 1256.87 seconds
Started Dec 27 01:35:45 PM PST 23
Finished Dec 27 01:56:43 PM PST 23
Peak memory 290256 kb
Host smart-69c350f9-abe1-4f3d-8b11-4cae3e103841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203315811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_fifo_full.203315811
Directory /workspace/35.spi_device_fifo_full/latest

Test location /workspace/coverage/default/35.spi_device_fifo_underflow_overflow.4250244825
Short name T619
Test name
Test status
Simulation time 971011859499 ps
CPU time 1047.91 seconds
Started Dec 27 01:35:05 PM PST 23
Finished Dec 27 01:52:37 PM PST 23
Peak memory 779752 kb
Host smart-8965acfc-a8a6-4df7-8a96-aa87bc5cd3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250244825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_fifo_underflow_overf
low.4250244825
Directory /workspace/35.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.89026907
Short name T889
Test name
Test status
Simulation time 45844783449 ps
CPU time 126.8 seconds
Started Dec 27 01:35:41 PM PST 23
Finished Dec 27 01:37:49 PM PST 23
Peak memory 254628 kb
Host smart-fb6fb3d7-91c8-413d-96f3-ef686a7455ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89026907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.89026907
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3463070094
Short name T235
Test name
Test status
Simulation time 138339535262 ps
CPU time 484.98 seconds
Started Dec 27 01:35:34 PM PST 23
Finished Dec 27 01:43:39 PM PST 23
Peak memory 267348 kb
Host smart-d9b96c97-9976-4523-af5e-fb23835e63be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463070094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3463070094
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_intercept.252954747
Short name T1389
Test name
Test status
Simulation time 188493363 ps
CPU time 3.41 seconds
Started Dec 27 01:34:57 PM PST 23
Finished Dec 27 01:35:00 PM PST 23
Peak memory 219260 kb
Host smart-1ba6ab61-d98b-4e72-ba41-b1e02ed90268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252954747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.252954747
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1698349253
Short name T1299
Test name
Test status
Simulation time 16489402192 ps
CPU time 35.95 seconds
Started Dec 27 01:35:26 PM PST 23
Finished Dec 27 01:36:05 PM PST 23
Peak memory 255008 kb
Host smart-9beff388-5ee8-4e30-b4f3-cb48ef0fca16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698349253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1698349253
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.982306105
Short name T1199
Test name
Test status
Simulation time 4818149185 ps
CPU time 9.01 seconds
Started Dec 27 01:34:52 PM PST 23
Finished Dec 27 01:35:02 PM PST 23
Peak memory 219732 kb
Host smart-ee74769d-c504-4e07-baec-146fe42b38f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982306105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.982306105
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3942501856
Short name T288
Test name
Test status
Simulation time 49678697734 ps
CPU time 13.3 seconds
Started Dec 27 01:35:22 PM PST 23
Finished Dec 27 01:35:37 PM PST 23
Peak memory 241492 kb
Host smart-0146c1e0-487e-44fe-a66f-fabe9170c3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942501856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3942501856
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_perf.186592628
Short name T1593
Test name
Test status
Simulation time 70844758481 ps
CPU time 388.29 seconds
Started Dec 27 01:35:34 PM PST 23
Finished Dec 27 01:42:03 PM PST 23
Peak memory 272768 kb
Host smart-c3ac362e-48a1-481d-b015-7da41dda2ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186592628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_perf.186592628
Directory /workspace/35.spi_device_perf/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2821577655
Short name T1151
Test name
Test status
Simulation time 816822702 ps
CPU time 4.03 seconds
Started Dec 27 01:35:06 PM PST 23
Finished Dec 27 01:35:15 PM PST 23
Peak memory 234292 kb
Host smart-09b3edb5-8128-4c69-b8a5-6dfd9591a033
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2821577655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2821577655
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_rx_timeout.2398644196
Short name T1062
Test name
Test status
Simulation time 12323025333 ps
CPU time 5.14 seconds
Started Dec 27 01:35:54 PM PST 23
Finished Dec 27 01:36:01 PM PST 23
Peak memory 216900 kb
Host smart-e0672f89-919e-4dbe-a498-cbcd4e92c32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398644196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_rx_timeout.2398644196
Directory /workspace/35.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3317993076
Short name T327
Test name
Test status
Simulation time 492525234943 ps
CPU time 638.09 seconds
Started Dec 27 01:35:32 PM PST 23
Finished Dec 27 01:46:11 PM PST 23
Peak memory 273388 kb
Host smart-59b4dc8c-d936-4eb3-bf00-54fca08b850e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317993076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3317993076
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3804240167
Short name T1076
Test name
Test status
Simulation time 21172874310 ps
CPU time 184.75 seconds
Started Dec 27 01:36:11 PM PST 23
Finished Dec 27 01:39:16 PM PST 23
Peak memory 217080 kb
Host smart-025d0753-75c5-4a05-b939-d1b39e168a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804240167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3804240167
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2079929325
Short name T1203
Test name
Test status
Simulation time 6262665567 ps
CPU time 22.53 seconds
Started Dec 27 01:36:11 PM PST 23
Finished Dec 27 01:36:34 PM PST 23
Peak memory 218104 kb
Host smart-b32ef756-5a50-47d3-b829-5cd9d8b05ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079929325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2079929325
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2379473120
Short name T1111
Test name
Test status
Simulation time 28041418 ps
CPU time 0.91 seconds
Started Dec 27 01:34:39 PM PST 23
Finished Dec 27 01:34:40 PM PST 23
Peak memory 207440 kb
Host smart-6671f3f9-2d51-4d0d-8671-c897ad3a79fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379473120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2379473120
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3050044565
Short name T1632
Test name
Test status
Simulation time 15821030 ps
CPU time 0.73 seconds
Started Dec 27 01:36:03 PM PST 23
Finished Dec 27 01:36:04 PM PST 23
Peak memory 206892 kb
Host smart-dbc4b9fc-64f9-433c-acef-17c3a17dc670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050044565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3050044565
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_tx_async_fifo_reset.2364193350
Short name T1652
Test name
Test status
Simulation time 45260591 ps
CPU time 0.81 seconds
Started Dec 27 01:35:55 PM PST 23
Finished Dec 27 01:35:57 PM PST 23
Peak memory 208428 kb
Host smart-53494074-b37d-4242-86ef-3ccff78ba886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364193350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tx_async_fifo_reset.2364193350
Directory /workspace/35.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/35.spi_device_txrx.3039220221
Short name T1254
Test name
Test status
Simulation time 205255156670 ps
CPU time 2734.78 seconds
Started Dec 27 01:35:00 PM PST 23
Finished Dec 27 02:20:37 PM PST 23
Peak memory 265628 kb
Host smart-602511ae-e7ca-4f61-b951-665a7ab21394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039220221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_txrx.3039220221
Directory /workspace/35.spi_device_txrx/latest

Test location /workspace/coverage/default/36.spi_device_abort.3823410398
Short name T1363
Test name
Test status
Simulation time 149944431 ps
CPU time 0.79 seconds
Started Dec 27 01:36:14 PM PST 23
Finished Dec 27 01:36:15 PM PST 23
Peak memory 206688 kb
Host smart-13da0bcd-ccf7-4a14-bbe6-c12eec2e5412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823410398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_abort.3823410398
Directory /workspace/36.spi_device_abort/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.600804220
Short name T103
Test name
Test status
Simulation time 42880809 ps
CPU time 0.72 seconds
Started Dec 27 01:35:45 PM PST 23
Finished Dec 27 01:35:47 PM PST 23
Peak memory 206524 kb
Host smart-ff7aaf59-dd5d-4cb5-bd89-517275d5e411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600804220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.600804220
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_bit_transfer.2998423296
Short name T1562
Test name
Test status
Simulation time 454832276 ps
CPU time 2.52 seconds
Started Dec 27 01:35:58 PM PST 23
Finished Dec 27 01:36:02 PM PST 23
Peak memory 216780 kb
Host smart-8d10e924-d07c-457d-8d05-cd4d477cc17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998423296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_bit_transfer.2998423296
Directory /workspace/36.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/36.spi_device_byte_transfer.2403157656
Short name T1034
Test name
Test status
Simulation time 146089629 ps
CPU time 2.72 seconds
Started Dec 27 01:35:05 PM PST 23
Finished Dec 27 01:35:14 PM PST 23
Peak memory 216764 kb
Host smart-395a8a4e-ac71-4e09-9493-8df882c3502f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403157656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_byte_transfer.2403157656
Directory /workspace/36.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3433723247
Short name T855
Test name
Test status
Simulation time 202022708 ps
CPU time 3.02 seconds
Started Dec 27 01:35:58 PM PST 23
Finished Dec 27 01:36:02 PM PST 23
Peak memory 240556 kb
Host smart-2faf45f1-f1c3-4a5a-9e48-28fd30d8c402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433723247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3433723247
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3043256651
Short name T497
Test name
Test status
Simulation time 21554207 ps
CPU time 0.74 seconds
Started Dec 27 01:35:36 PM PST 23
Finished Dec 27 01:35:37 PM PST 23
Peak memory 206584 kb
Host smart-842a0612-86c0-4e89-8807-d16bb9e77a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043256651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3043256651
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_dummy_item_extra_dly.3851000297
Short name T590
Test name
Test status
Simulation time 36661571387 ps
CPU time 285.95 seconds
Started Dec 27 01:35:53 PM PST 23
Finished Dec 27 01:40:39 PM PST 23
Peak memory 254256 kb
Host smart-0a154bbd-8ad4-400f-ac41-916fc3775e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851000297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_dummy_item_extra_dly.3851000297
Directory /workspace/36.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/36.spi_device_extreme_fifo_size.104036156
Short name T1373
Test name
Test status
Simulation time 301629359670 ps
CPU time 812.48 seconds
Started Dec 27 01:35:52 PM PST 23
Finished Dec 27 01:49:26 PM PST 23
Peak memory 220104 kb
Host smart-d4c85331-b07c-40c3-a4c4-97d3c33c5f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104036156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_extreme_fifo_size.104036156
Directory /workspace/36.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/36.spi_device_fifo_full.3179171445
Short name T1448
Test name
Test status
Simulation time 57183499414 ps
CPU time 463.31 seconds
Started Dec 27 01:35:09 PM PST 23
Finished Dec 27 01:42:55 PM PST 23
Peak memory 288260 kb
Host smart-9353983c-7fa6-49b2-8b27-117955ac64a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179171445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_fifo_full.3179171445
Directory /workspace/36.spi_device_fifo_full/latest

Test location /workspace/coverage/default/36.spi_device_fifo_underflow_overflow.3474405495
Short name T1738
Test name
Test status
Simulation time 123142108011 ps
CPU time 162.42 seconds
Started Dec 27 01:35:58 PM PST 23
Finished Dec 27 01:38:41 PM PST 23
Peak memory 347400 kb
Host smart-080cb5ab-43ad-411b-a11b-937d6d4fbbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474405495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_fifo_underflow_overf
low.3474405495
Directory /workspace/36.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.4090587764
Short name T332
Test name
Test status
Simulation time 22389956828 ps
CPU time 155.77 seconds
Started Dec 27 01:35:27 PM PST 23
Finished Dec 27 01:38:05 PM PST 23
Peak memory 274200 kb
Host smart-0e485228-0878-4eb6-ac6a-e32b939843ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090587764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4090587764
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2714013226
Short name T289
Test name
Test status
Simulation time 34826945765 ps
CPU time 177.05 seconds
Started Dec 27 01:35:28 PM PST 23
Finished Dec 27 01:38:27 PM PST 23
Peak memory 256884 kb
Host smart-69534d19-78af-4dd2-986a-97963eee1c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714013226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2714013226
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2041750397
Short name T1106
Test name
Test status
Simulation time 2114547128 ps
CPU time 16.1 seconds
Started Dec 27 01:35:02 PM PST 23
Finished Dec 27 01:35:25 PM PST 23
Peak memory 249024 kb
Host smart-f43d055b-a090-4206-b112-40ee04493948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041750397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2041750397
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3262337454
Short name T1069
Test name
Test status
Simulation time 101345243 ps
CPU time 2.76 seconds
Started Dec 27 01:35:58 PM PST 23
Finished Dec 27 01:36:01 PM PST 23
Peak memory 218272 kb
Host smart-0e61e10f-de63-4ca5-8277-2af415ab43e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262337454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3262337454
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_intr.1889751403
Short name T544
Test name
Test status
Simulation time 29889996830 ps
CPU time 46.97 seconds
Started Dec 27 01:35:49 PM PST 23
Finished Dec 27 01:36:36 PM PST 23
Peak memory 233036 kb
Host smart-c739d2f1-78e2-41ce-b039-a8bcae807bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889751403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intr.1889751403
Directory /workspace/36.spi_device_intr/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.98846652
Short name T1139
Test name
Test status
Simulation time 2426371961 ps
CPU time 16.45 seconds
Started Dec 27 01:35:54 PM PST 23
Finished Dec 27 01:36:12 PM PST 23
Peak memory 231648 kb
Host smart-6d3700f3-b9c2-41fc-9f2f-0d81a40b5c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98846652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.98846652
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1645137890
Short name T1148
Test name
Test status
Simulation time 170903371 ps
CPU time 4.44 seconds
Started Dec 27 01:36:16 PM PST 23
Finished Dec 27 01:36:21 PM PST 23
Peak memory 241432 kb
Host smart-eaa692ca-cd7c-49e8-a36a-2311069df729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645137890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1645137890
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.629041085
Short name T1396
Test name
Test status
Simulation time 4939484472 ps
CPU time 9.3 seconds
Started Dec 27 01:36:03 PM PST 23
Finished Dec 27 01:36:14 PM PST 23
Peak memory 219860 kb
Host smart-1b218643-ab66-496b-85d2-aa0f4c4d37dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629041085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.629041085
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_perf.463342028
Short name T1200
Test name
Test status
Simulation time 29976317324 ps
CPU time 174.27 seconds
Started Dec 27 01:36:09 PM PST 23
Finished Dec 27 01:39:04 PM PST 23
Peak memory 255592 kb
Host smart-5aaa78bb-6145-4daf-8d2a-1c7250e53c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463342028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_perf.463342028
Directory /workspace/36.spi_device_perf/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3796885689
Short name T43
Test name
Test status
Simulation time 849804201 ps
CPU time 4.3 seconds
Started Dec 27 01:35:05 PM PST 23
Finished Dec 27 01:35:14 PM PST 23
Peak memory 219920 kb
Host smart-204010e1-032a-4a8c-92f9-950516b45e8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3796885689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3796885689
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_rx_async_fifo_reset.986348605
Short name T1278
Test name
Test status
Simulation time 36665443 ps
CPU time 0.88 seconds
Started Dec 27 01:36:01 PM PST 23
Finished Dec 27 01:36:03 PM PST 23
Peak memory 208504 kb
Host smart-d963c66d-7027-4848-b983-8382ceeba07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986348605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_rx_async_fifo_reset.986348605
Directory /workspace/36.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/36.spi_device_rx_timeout.1932349195
Short name T1469
Test name
Test status
Simulation time 3763136230 ps
CPU time 5.07 seconds
Started Dec 27 01:35:59 PM PST 23
Finished Dec 27 01:36:04 PM PST 23
Peak memory 216888 kb
Host smart-bf16ed7d-61be-4c7e-a4b3-ecaa448ef958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932349195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_rx_timeout.1932349195
Directory /workspace/36.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/36.spi_device_smoke.4128010475
Short name T507
Test name
Test status
Simulation time 210031479 ps
CPU time 1.17 seconds
Started Dec 27 01:35:38 PM PST 23
Finished Dec 27 01:35:40 PM PST 23
Peak memory 216556 kb
Host smart-e6de44b1-75dc-4563-87f8-18914b4de9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128010475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_smoke.4128010475
Directory /workspace/36.spi_device_smoke/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1919397669
Short name T1336
Test name
Test status
Simulation time 22993563188 ps
CPU time 187.4 seconds
Started Dec 27 01:35:52 PM PST 23
Finished Dec 27 01:39:00 PM PST 23
Peak memory 221996 kb
Host smart-38d91e62-b007-4f64-9f5a-2f2e5cf640f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919397669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1919397669
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2798250079
Short name T22
Test name
Test status
Simulation time 10661440100 ps
CPU time 20.51 seconds
Started Dec 27 01:35:46 PM PST 23
Finished Dec 27 01:36:07 PM PST 23
Peak memory 217976 kb
Host smart-27fa3016-86e8-4eca-9c80-cd663bceb293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798250079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2798250079
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2484005498
Short name T1740
Test name
Test status
Simulation time 80367025 ps
CPU time 1.71 seconds
Started Dec 27 01:36:09 PM PST 23
Finished Dec 27 01:36:12 PM PST 23
Peak memory 216836 kb
Host smart-8b79d0a3-bb1f-4d60-b8b9-b8298ad27e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484005498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2484005498
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1812489691
Short name T726
Test name
Test status
Simulation time 28725317 ps
CPU time 0.74 seconds
Started Dec 27 01:36:01 PM PST 23
Finished Dec 27 01:36:03 PM PST 23
Peak memory 206808 kb
Host smart-29cfdf4d-ccb6-4641-b12d-b73f7a502537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812489691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1812489691
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_tx_async_fifo_reset.2581750555
Short name T635
Test name
Test status
Simulation time 25158323 ps
CPU time 0.79 seconds
Started Dec 27 01:36:00 PM PST 23
Finished Dec 27 01:36:02 PM PST 23
Peak memory 208352 kb
Host smart-71093c9d-fd05-4f77-b7ef-8d5bbc706f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581750555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tx_async_fifo_reset.2581750555
Directory /workspace/36.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/36.spi_device_txrx.3841418905
Short name T677
Test name
Test status
Simulation time 69419241601 ps
CPU time 269.04 seconds
Started Dec 27 01:35:30 PM PST 23
Finished Dec 27 01:40:02 PM PST 23
Peak memory 239092 kb
Host smart-e7e52b37-51fe-4a14-be29-9dada7160d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841418905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_txrx.3841418905
Directory /workspace/36.spi_device_txrx/latest

Test location /workspace/coverage/default/36.spi_device_upload.2928361086
Short name T301
Test name
Test status
Simulation time 9953273898 ps
CPU time 33.95 seconds
Started Dec 27 01:35:50 PM PST 23
Finished Dec 27 01:36:25 PM PST 23
Peak memory 252048 kb
Host smart-64d5a21a-980f-472c-8fa3-461c92ce05b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928361086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2928361086
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_abort.1067683701
Short name T1095
Test name
Test status
Simulation time 18943725 ps
CPU time 0.8 seconds
Started Dec 27 01:35:50 PM PST 23
Finished Dec 27 01:35:51 PM PST 23
Peak memory 206648 kb
Host smart-39e1b86e-1762-4efe-a72a-f60a69130f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067683701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_abort.1067683701
Directory /workspace/37.spi_device_abort/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.520678601
Short name T552
Test name
Test status
Simulation time 11021280 ps
CPU time 0.74 seconds
Started Dec 27 01:35:44 PM PST 23
Finished Dec 27 01:35:45 PM PST 23
Peak memory 206512 kb
Host smart-9369ea51-5a7c-465d-b795-3253e88563ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520678601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.520678601
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_bit_transfer.2832322869
Short name T1383
Test name
Test status
Simulation time 1130288919 ps
CPU time 2.77 seconds
Started Dec 27 01:35:06 PM PST 23
Finished Dec 27 01:35:14 PM PST 23
Peak memory 216792 kb
Host smart-8d5d4460-2d5a-4013-ae82-099cc649dafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832322869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_bit_transfer.2832322869
Directory /workspace/37.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/37.spi_device_byte_transfer.1954921218
Short name T1084
Test name
Test status
Simulation time 374688670 ps
CPU time 2.87 seconds
Started Dec 27 01:35:04 PM PST 23
Finished Dec 27 01:35:12 PM PST 23
Peak memory 216804 kb
Host smart-b9045022-523f-4e8c-a871-614738abc6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954921218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_byte_transfer.1954921218
Directory /workspace/37.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1574233455
Short name T316
Test name
Test status
Simulation time 191491641 ps
CPU time 2.3 seconds
Started Dec 27 01:35:33 PM PST 23
Finished Dec 27 01:35:36 PM PST 23
Peak memory 218368 kb
Host smart-e626d945-ed74-4591-878f-54c25fbf7c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574233455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1574233455
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.4055087560
Short name T1024
Test name
Test status
Simulation time 40918601 ps
CPU time 0.77 seconds
Started Dec 27 01:35:56 PM PST 23
Finished Dec 27 01:35:57 PM PST 23
Peak memory 207484 kb
Host smart-f7910921-3fa8-43c4-89bf-e3e000c79546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055087560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4055087560
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_dummy_item_extra_dly.1413865070
Short name T798
Test name
Test status
Simulation time 73232513013 ps
CPU time 559.33 seconds
Started Dec 27 01:36:03 PM PST 23
Finished Dec 27 01:45:24 PM PST 23
Peak memory 289840 kb
Host smart-d2331729-0bf1-4daa-8cfa-08a7750bdf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413865070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_dummy_item_extra_dly.1413865070
Directory /workspace/37.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/37.spi_device_extreme_fifo_size.4246026426
Short name T1601
Test name
Test status
Simulation time 33530048035 ps
CPU time 357 seconds
Started Dec 27 01:35:28 PM PST 23
Finished Dec 27 01:41:27 PM PST 23
Peak memory 216908 kb
Host smart-d04a7a39-1fa4-4bd6-beaa-46362cb894f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246026426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_extreme_fifo_size.4246026426
Directory /workspace/37.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/37.spi_device_fifo_full.1505161080
Short name T561
Test name
Test status
Simulation time 26682012155 ps
CPU time 462.05 seconds
Started Dec 27 01:35:32 PM PST 23
Finished Dec 27 01:43:15 PM PST 23
Peak memory 269912 kb
Host smart-6015d713-7a23-4260-b298-02167130322f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505161080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_fifo_full.1505161080
Directory /workspace/37.spi_device_fifo_full/latest

Test location /workspace/coverage/default/37.spi_device_fifo_underflow_overflow.3033600409
Short name T1212
Test name
Test status
Simulation time 29289495102 ps
CPU time 134.33 seconds
Started Dec 27 01:35:52 PM PST 23
Finished Dec 27 01:38:07 PM PST 23
Peak memory 338312 kb
Host smart-320fe8ba-53d8-46ad-a4c0-7dae4dc685b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033600409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_fifo_underflow_overf
low.3033600409
Directory /workspace/37.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2658716792
Short name T696
Test name
Test status
Simulation time 448077822802 ps
CPU time 361.82 seconds
Started Dec 27 01:36:22 PM PST 23
Finished Dec 27 01:42:26 PM PST 23
Peak memory 257980 kb
Host smart-944f416d-9308-41e6-a52a-c2efe438c36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658716792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2658716792
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.87299202
Short name T350
Test name
Test status
Simulation time 14734520016 ps
CPU time 110.3 seconds
Started Dec 27 01:34:59 PM PST 23
Finished Dec 27 01:36:51 PM PST 23
Peak memory 249760 kb
Host smart-6f1091a2-bf47-4544-b229-4cd1dfc7577c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87299202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.87299202
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2725889856
Short name T265
Test name
Test status
Simulation time 3042462888 ps
CPU time 21.9 seconds
Started Dec 27 01:36:19 PM PST 23
Finished Dec 27 01:36:42 PM PST 23
Peak memory 223888 kb
Host smart-2ea09a15-20f4-42ea-ab88-b461c8d7ff9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725889856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2725889856
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1828534288
Short name T1408
Test name
Test status
Simulation time 139515711 ps
CPU time 2.69 seconds
Started Dec 27 01:35:58 PM PST 23
Finished Dec 27 01:36:01 PM PST 23
Peak memory 218652 kb
Host smart-343e3913-448a-4c01-807b-40d4bd31460b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828534288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1828534288
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_intr.3832197619
Short name T990
Test name
Test status
Simulation time 36300169156 ps
CPU time 20.07 seconds
Started Dec 27 01:35:44 PM PST 23
Finished Dec 27 01:36:05 PM PST 23
Peak memory 218816 kb
Host smart-a2d4e00b-1907-4b3a-971a-2c03d6097c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832197619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intr.3832197619
Directory /workspace/37.spi_device_intr/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.4208780436
Short name T1679
Test name
Test status
Simulation time 20064326888 ps
CPU time 22.84 seconds
Started Dec 27 01:36:01 PM PST 23
Finished Dec 27 01:36:25 PM PST 23
Peak memory 225128 kb
Host smart-ff55babb-db3d-47f7-a9bb-6c522e7009e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208780436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.4208780436
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.532638032
Short name T1087
Test name
Test status
Simulation time 9053911472 ps
CPU time 6.25 seconds
Started Dec 27 01:36:16 PM PST 23
Finished Dec 27 01:36:22 PM PST 23
Peak memory 241556 kb
Host smart-94508be7-415f-4986-afae-c659c278b428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532638032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.532638032
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_perf.1450313863
Short name T749
Test name
Test status
Simulation time 83551476201 ps
CPU time 541.68 seconds
Started Dec 27 01:36:04 PM PST 23
Finished Dec 27 01:45:07 PM PST 23
Peak memory 249820 kb
Host smart-94a729b9-cf44-4369-baef-dad0f18ab2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450313863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_perf.1450313863
Directory /workspace/37.spi_device_perf/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2426090014
Short name T1306
Test name
Test status
Simulation time 1605098731 ps
CPU time 4.67 seconds
Started Dec 27 01:35:50 PM PST 23
Finished Dec 27 01:35:55 PM PST 23
Peak memory 234056 kb
Host smart-6f5eabcf-3150-4c26-9bae-e2d838402df2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2426090014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2426090014
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_rx_async_fifo_reset.4273770024
Short name T1182
Test name
Test status
Simulation time 43051397 ps
CPU time 0.87 seconds
Started Dec 27 01:35:40 PM PST 23
Finished Dec 27 01:35:42 PM PST 23
Peak memory 208484 kb
Host smart-54991dfd-a0b5-435e-a5e8-c187ff98d939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273770024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_rx_async_fifo_reset.4273770024
Directory /workspace/37.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/37.spi_device_rx_timeout.816140498
Short name T960
Test name
Test status
Simulation time 1181892829 ps
CPU time 6.59 seconds
Started Dec 27 01:35:01 PM PST 23
Finished Dec 27 01:35:11 PM PST 23
Peak memory 216796 kb
Host smart-b49a7fa6-1134-4eea-a342-1259e5aeb588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816140498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_rx_timeout.816140498
Directory /workspace/37.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/37.spi_device_smoke.503937013
Short name T1330
Test name
Test status
Simulation time 68795174 ps
CPU time 0.97 seconds
Started Dec 27 01:35:01 PM PST 23
Finished Dec 27 01:35:06 PM PST 23
Peak memory 207984 kb
Host smart-4ed8d588-0107-4770-b1f8-bc7ca7bf4bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503937013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_smoke.503937013
Directory /workspace/37.spi_device_smoke/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2568215994
Short name T356
Test name
Test status
Simulation time 35077299759 ps
CPU time 70.64 seconds
Started Dec 27 01:35:48 PM PST 23
Finished Dec 27 01:36:59 PM PST 23
Peak memory 217036 kb
Host smart-5f630c09-8611-4ec6-83ae-1a8b3a133996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568215994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2568215994
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1455461675
Short name T751
Test name
Test status
Simulation time 910155131 ps
CPU time 7.69 seconds
Started Dec 27 01:35:02 PM PST 23
Finished Dec 27 01:35:17 PM PST 23
Peak memory 216776 kb
Host smart-bbfaac75-a7ec-4724-9838-2cdd0920b937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455461675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1455461675
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3358854633
Short name T734
Test name
Test status
Simulation time 160692836 ps
CPU time 4.88 seconds
Started Dec 27 01:35:55 PM PST 23
Finished Dec 27 01:36:01 PM PST 23
Peak memory 216772 kb
Host smart-39ee7156-0fe6-441e-9e86-c95d86195bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358854633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3358854633
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2300991975
Short name T1719
Test name
Test status
Simulation time 440049051 ps
CPU time 1.07 seconds
Started Dec 27 01:36:07 PM PST 23
Finished Dec 27 01:36:09 PM PST 23
Peak memory 208364 kb
Host smart-3755d750-e8e4-4b1e-adda-9e656a2208c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300991975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2300991975
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_tx_async_fifo_reset.1802338302
Short name T1581
Test name
Test status
Simulation time 78173769 ps
CPU time 0.78 seconds
Started Dec 27 01:35:48 PM PST 23
Finished Dec 27 01:35:49 PM PST 23
Peak memory 208404 kb
Host smart-ca543192-fa0b-4227-b322-43638f6c3dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802338302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tx_async_fifo_reset.1802338302
Directory /workspace/37.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/37.spi_device_txrx.2717609409
Short name T1669
Test name
Test status
Simulation time 76533201625 ps
CPU time 765.7 seconds
Started Dec 27 01:35:02 PM PST 23
Finished Dec 27 01:47:54 PM PST 23
Peak memory 239560 kb
Host smart-58dc1caa-b74b-4f91-8d56-14438b6b36d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717609409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_txrx.2717609409
Directory /workspace/37.spi_device_txrx/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.4278539857
Short name T1162
Test name
Test status
Simulation time 22086836 ps
CPU time 0.69 seconds
Started Dec 27 01:36:04 PM PST 23
Finished Dec 27 01:36:06 PM PST 23
Peak memory 206492 kb
Host smart-4d2d3102-03cd-47ab-87a1-daf05b5caf23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278539857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
4278539857
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_bit_transfer.1188096753
Short name T1645
Test name
Test status
Simulation time 114503884 ps
CPU time 2.5 seconds
Started Dec 27 01:36:01 PM PST 23
Finished Dec 27 01:36:04 PM PST 23
Peak memory 216816 kb
Host smart-8a9c2b1a-3486-4876-8f16-31fe1782693c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188096753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_bit_transfer.1188096753
Directory /workspace/38.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/38.spi_device_byte_transfer.2108882622
Short name T1731
Test name
Test status
Simulation time 393872866 ps
CPU time 3.09 seconds
Started Dec 27 01:35:51 PM PST 23
Finished Dec 27 01:35:56 PM PST 23
Peak memory 216772 kb
Host smart-c0b1f916-cd5b-4a8d-9b7b-728f1c29ec53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108882622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_byte_transfer.2108882622
Directory /workspace/38.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1377098851
Short name T1028
Test name
Test status
Simulation time 59162969 ps
CPU time 3.12 seconds
Started Dec 27 01:35:43 PM PST 23
Finished Dec 27 01:35:47 PM PST 23
Peak memory 241440 kb
Host smart-5a307915-e69f-4b75-b701-8a58c73d674b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377098851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1377098851
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1939716709
Short name T807
Test name
Test status
Simulation time 52914338 ps
CPU time 0.78 seconds
Started Dec 27 01:35:45 PM PST 23
Finished Dec 27 01:35:46 PM PST 23
Peak memory 207512 kb
Host smart-b1617abf-440f-48db-9ed6-626469103ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939716709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1939716709
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_dummy_item_extra_dly.590881194
Short name T1452
Test name
Test status
Simulation time 41417887296 ps
CPU time 291.75 seconds
Started Dec 27 01:35:46 PM PST 23
Finished Dec 27 01:40:39 PM PST 23
Peak memory 298460 kb
Host smart-15985f5e-d4f9-422c-906e-2d79da5fcbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590881194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_dummy_item_extra_dly.590881194
Directory /workspace/38.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/38.spi_device_extreme_fifo_size.2289536743
Short name T649
Test name
Test status
Simulation time 76437585374 ps
CPU time 1838.71 seconds
Started Dec 27 01:35:42 PM PST 23
Finished Dec 27 02:06:22 PM PST 23
Peak memory 217000 kb
Host smart-00843e22-cc9e-432b-99d9-7effa2fc2ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289536743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_extreme_fifo_size.2289536743
Directory /workspace/38.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/38.spi_device_fifo_full.1507702186
Short name T969
Test name
Test status
Simulation time 38498767370 ps
CPU time 425.38 seconds
Started Dec 27 01:36:15 PM PST 23
Finished Dec 27 01:43:21 PM PST 23
Peak memory 255776 kb
Host smart-cdfcd8e7-5af8-498f-b3f3-72b4a95d7dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507702186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_fifo_full.1507702186
Directory /workspace/38.spi_device_fifo_full/latest

Test location /workspace/coverage/default/38.spi_device_fifo_underflow_overflow.3465034516
Short name T1191
Test name
Test status
Simulation time 65226586555 ps
CPU time 379.3 seconds
Started Dec 27 01:35:42 PM PST 23
Finished Dec 27 01:42:03 PM PST 23
Peak memory 366648 kb
Host smart-430d0990-2322-4e5d-9e9d-129851624ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465034516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_fifo_underflow_overf
low.3465034516
Directory /workspace/38.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2672243994
Short name T24
Test name
Test status
Simulation time 13642159056 ps
CPU time 97.25 seconds
Started Dec 27 01:35:38 PM PST 23
Finished Dec 27 01:37:17 PM PST 23
Peak memory 251032 kb
Host smart-67686bd7-ed45-46f5-8d75-16e319d11de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672243994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2672243994
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3712008499
Short name T343
Test name
Test status
Simulation time 4385384117 ps
CPU time 78.24 seconds
Started Dec 27 01:35:38 PM PST 23
Finished Dec 27 01:36:58 PM PST 23
Peak memory 266232 kb
Host smart-ee8ac635-d103-422b-a842-7192c00a0d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712008499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3712008499
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.594402452
Short name T1426
Test name
Test status
Simulation time 327030677 ps
CPU time 12.06 seconds
Started Dec 27 01:35:54 PM PST 23
Finished Dec 27 01:36:07 PM PST 23
Peak memory 249532 kb
Host smart-d2abfb04-9703-4ec3-bc9e-1325970b7dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594402452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.594402452
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1118427246
Short name T1596
Test name
Test status
Simulation time 1423412974 ps
CPU time 6.49 seconds
Started Dec 27 01:36:16 PM PST 23
Finished Dec 27 01:36:23 PM PST 23
Peak memory 218552 kb
Host smart-988d87a5-7c69-443b-baee-704bace437a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118427246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1118427246
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_intr.287067868
Short name T980
Test name
Test status
Simulation time 8961017182 ps
CPU time 59.92 seconds
Started Dec 27 01:35:38 PM PST 23
Finished Dec 27 01:36:40 PM PST 23
Peak memory 249824 kb
Host smart-94fc85ab-df98-49cd-b4fd-486cbef85d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287067868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intr.287067868
Directory /workspace/38.spi_device_intr/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1898638009
Short name T725
Test name
Test status
Simulation time 2885732106 ps
CPU time 12.51 seconds
Started Dec 27 01:35:39 PM PST 23
Finished Dec 27 01:35:52 PM PST 23
Peak memory 249764 kb
Host smart-b4e5f9bf-3e0e-40c7-b9d8-0f0c80bb7d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898638009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1898638009
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.525819893
Short name T1384
Test name
Test status
Simulation time 44265411224 ps
CPU time 31.38 seconds
Started Dec 27 01:36:16 PM PST 23
Finished Dec 27 01:36:48 PM PST 23
Peak memory 238896 kb
Host smart-b1eb464c-e6c5-4471-bc13-788d1541894c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525819893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.525819893
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.350087946
Short name T1386
Test name
Test status
Simulation time 1424723966 ps
CPU time 5.27 seconds
Started Dec 27 01:36:00 PM PST 23
Finished Dec 27 01:36:07 PM PST 23
Peak memory 221536 kb
Host smart-9ddaf761-1ede-42f9-9f39-3da3f70d2840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350087946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.350087946
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_perf.3473894202
Short name T897
Test name
Test status
Simulation time 8026550182 ps
CPU time 217.44 seconds
Started Dec 27 01:35:43 PM PST 23
Finished Dec 27 01:39:21 PM PST 23
Peak memory 249736 kb
Host smart-7c1946a5-7a42-4d60-ad15-36741f9126ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473894202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_perf.3473894202
Directory /workspace/38.spi_device_perf/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.310619719
Short name T1257
Test name
Test status
Simulation time 1199309669 ps
CPU time 5.74 seconds
Started Dec 27 01:36:22 PM PST 23
Finished Dec 27 01:36:30 PM PST 23
Peak memory 219380 kb
Host smart-e0644767-4af2-4c3d-a3b4-58b377844d9e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=310619719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.310619719
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_rx_async_fifo_reset.1227778886
Short name T1453
Test name
Test status
Simulation time 51734660 ps
CPU time 0.87 seconds
Started Dec 27 01:35:53 PM PST 23
Finished Dec 27 01:35:55 PM PST 23
Peak memory 208388 kb
Host smart-954c9a3c-6364-45a7-97e9-7b64a5c513e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227778886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_rx_async_fifo_reset.1227778886
Directory /workspace/38.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/38.spi_device_rx_timeout.3836729497
Short name T1623
Test name
Test status
Simulation time 2447378244 ps
CPU time 5.62 seconds
Started Dec 27 01:35:29 PM PST 23
Finished Dec 27 01:35:36 PM PST 23
Peak memory 216936 kb
Host smart-8adeb04e-25bc-4df1-a2b0-c2be4c99f8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836729497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_rx_timeout.3836729497
Directory /workspace/38.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/38.spi_device_smoke.2926514814
Short name T1133
Test name
Test status
Simulation time 45609312 ps
CPU time 1.05 seconds
Started Dec 27 01:35:26 PM PST 23
Finished Dec 27 01:35:30 PM PST 23
Peak memory 208344 kb
Host smart-41b2eb01-a19a-4254-9b6c-f9824d2906e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926514814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_smoke.2926514814
Directory /workspace/38.spi_device_smoke/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3293169268
Short name T1484
Test name
Test status
Simulation time 68321769760 ps
CPU time 160.22 seconds
Started Dec 27 01:36:00 PM PST 23
Finished Dec 27 01:38:40 PM PST 23
Peak memory 222792 kb
Host smart-29eeea75-2642-4860-9825-358799460b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293169268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3293169268
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3639622087
Short name T1081
Test name
Test status
Simulation time 1850951189 ps
CPU time 6.53 seconds
Started Dec 27 01:35:43 PM PST 23
Finished Dec 27 01:35:50 PM PST 23
Peak memory 216864 kb
Host smart-4121272c-628e-4a6f-9a6b-18c5b5063751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639622087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3639622087
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.212392222
Short name T795
Test name
Test status
Simulation time 131616054 ps
CPU time 1.06 seconds
Started Dec 27 01:36:11 PM PST 23
Finished Dec 27 01:36:13 PM PST 23
Peak memory 207964 kb
Host smart-2db41ad5-0fba-421b-b3b8-4782c310bdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212392222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.212392222
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1358998665
Short name T730
Test name
Test status
Simulation time 121274368 ps
CPU time 1.1 seconds
Started Dec 27 01:35:54 PM PST 23
Finished Dec 27 01:35:56 PM PST 23
Peak memory 208096 kb
Host smart-87a17eea-4363-4c46-b14d-6646f641eb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358998665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1358998665
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_tx_async_fifo_reset.2748807597
Short name T158
Test name
Test status
Simulation time 38577906 ps
CPU time 0.74 seconds
Started Dec 27 01:36:00 PM PST 23
Finished Dec 27 01:36:01 PM PST 23
Peak memory 208440 kb
Host smart-0211c336-c4bc-46ca-ba3d-af9cd5c019af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748807597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tx_async_fifo_reset.2748807597
Directory /workspace/38.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/38.spi_device_txrx.164454254
Short name T1178
Test name
Test status
Simulation time 31781666781 ps
CPU time 274.67 seconds
Started Dec 27 01:35:48 PM PST 23
Finished Dec 27 01:40:24 PM PST 23
Peak memory 249620 kb
Host smart-292f83c1-283d-4202-abb7-c5241eb5fc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164454254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_txrx.164454254
Directory /workspace/38.spi_device_txrx/latest

Test location /workspace/coverage/default/38.spi_device_upload.1803174174
Short name T1023
Test name
Test status
Simulation time 779744332 ps
CPU time 8.7 seconds
Started Dec 27 01:35:39 PM PST 23
Finished Dec 27 01:35:49 PM PST 23
Peak memory 227364 kb
Host smart-ed9f16e1-f4ba-41ea-a525-a550d9ebdaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803174174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1803174174
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_abort.848720875
Short name T1337
Test name
Test status
Simulation time 17757331 ps
CPU time 0.74 seconds
Started Dec 27 01:35:51 PM PST 23
Finished Dec 27 01:35:53 PM PST 23
Peak memory 206644 kb
Host smart-7641e2e0-71fa-4640-b4c0-7ceb77139550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848720875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_abort.848720875
Directory /workspace/39.spi_device_abort/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4054304865
Short name T104
Test name
Test status
Simulation time 26872934 ps
CPU time 0.76 seconds
Started Dec 27 01:36:25 PM PST 23
Finished Dec 27 01:36:27 PM PST 23
Peak memory 206472 kb
Host smart-8265cb19-a544-402a-beb4-c7bfc841c8e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054304865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4054304865
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_bit_transfer.1229234583
Short name T1715
Test name
Test status
Simulation time 1692807768 ps
CPU time 2.3 seconds
Started Dec 27 01:36:00 PM PST 23
Finished Dec 27 01:36:03 PM PST 23
Peak memory 216680 kb
Host smart-35ed98ca-900a-4dfd-90f0-b2e3ec2de054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229234583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_bit_transfer.1229234583
Directory /workspace/39.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/39.spi_device_byte_transfer.1411071294
Short name T1137
Test name
Test status
Simulation time 623573185 ps
CPU time 3.69 seconds
Started Dec 27 01:36:19 PM PST 23
Finished Dec 27 01:36:24 PM PST 23
Peak memory 216820 kb
Host smart-fb8b11e8-e5fc-4adf-a9e9-2a2cda35358d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411071294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_byte_transfer.1411071294
Directory /workspace/39.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3450033453
Short name T1006
Test name
Test status
Simulation time 148379486 ps
CPU time 3.03 seconds
Started Dec 27 01:36:36 PM PST 23
Finished Dec 27 01:36:39 PM PST 23
Peak memory 238388 kb
Host smart-e1b30215-d51b-4785-a328-7e20001740d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450033453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3450033453
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3806213678
Short name T483
Test name
Test status
Simulation time 56092040 ps
CPU time 0.77 seconds
Started Dec 27 01:35:52 PM PST 23
Finished Dec 27 01:35:53 PM PST 23
Peak memory 207608 kb
Host smart-61e16811-660e-439f-9db9-fc5d867cc60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806213678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3806213678
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_dummy_item_extra_dly.139661265
Short name T801
Test name
Test status
Simulation time 71420542297 ps
CPU time 948.1 seconds
Started Dec 27 01:35:59 PM PST 23
Finished Dec 27 01:51:48 PM PST 23
Peak memory 277988 kb
Host smart-245121af-1221-410c-b9c0-b9ef6e2e306d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139661265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_dummy_item_extra_dly.139661265
Directory /workspace/39.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/39.spi_device_extreme_fifo_size.4184375214
Short name T613
Test name
Test status
Simulation time 4366309198 ps
CPU time 47 seconds
Started Dec 27 01:36:07 PM PST 23
Finished Dec 27 01:36:55 PM PST 23
Peak memory 241040 kb
Host smart-a4ed9f54-506c-4b73-bfbf-7bfa8e21aa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184375214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_extreme_fifo_size.4184375214
Directory /workspace/39.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/39.spi_device_fifo_full.3686561238
Short name T1094
Test name
Test status
Simulation time 43952028216 ps
CPU time 1167.37 seconds
Started Dec 27 01:36:12 PM PST 23
Finished Dec 27 01:55:40 PM PST 23
Peak memory 254900 kb
Host smart-0fd21283-d7f4-4a24-8645-8d3a4f1767e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686561238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_fifo_full.3686561238
Directory /workspace/39.spi_device_fifo_full/latest

Test location /workspace/coverage/default/39.spi_device_fifo_underflow_overflow.2827903992
Short name T718
Test name
Test status
Simulation time 35199737021 ps
CPU time 221 seconds
Started Dec 27 01:36:19 PM PST 23
Finished Dec 27 01:40:02 PM PST 23
Peak memory 336328 kb
Host smart-217e2365-6c9b-4ae8-9b21-35342bd8d8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827903992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_fifo_underflow_overf
low.2827903992
Directory /workspace/39.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.321306600
Short name T1349
Test name
Test status
Simulation time 101825994574 ps
CPU time 198.11 seconds
Started Dec 27 01:36:20 PM PST 23
Finished Dec 27 01:39:46 PM PST 23
Peak memory 265552 kb
Host smart-3ab35d93-983d-42ef-a4f0-7b206bfa4928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321306600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.321306600
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.705562259
Short name T322
Test name
Test status
Simulation time 178080004265 ps
CPU time 496.74 seconds
Started Dec 27 01:36:32 PM PST 23
Finished Dec 27 01:44:49 PM PST 23
Peak memory 273380 kb
Host smart-596af772-0ea2-4d6d-b144-7b0c27658509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705562259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.705562259
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3471948688
Short name T918
Test name
Test status
Simulation time 1859867028 ps
CPU time 20.12 seconds
Started Dec 27 01:36:21 PM PST 23
Finished Dec 27 01:36:42 PM PST 23
Peak memory 257820 kb
Host smart-42c8d813-edb9-4525-afc1-73bb8c9e3295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471948688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3471948688
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.294351081
Short name T1008
Test name
Test status
Simulation time 171218207 ps
CPU time 4.3 seconds
Started Dec 27 01:36:32 PM PST 23
Finished Dec 27 01:36:37 PM PST 23
Peak memory 238312 kb
Host smart-9f40a23c-194d-43cc-8f4f-0e68d7717ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294351081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.294351081
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_intr.3019833911
Short name T758
Test name
Test status
Simulation time 29737183645 ps
CPU time 38.15 seconds
Started Dec 27 01:35:58 PM PST 23
Finished Dec 27 01:36:37 PM PST 23
Peak memory 233344 kb
Host smart-f9c89ee9-cb5c-495a-b1aa-e801f3573836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019833911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intr.3019833911
Directory /workspace/39.spi_device_intr/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1356587194
Short name T820
Test name
Test status
Simulation time 5413952401 ps
CPU time 11.61 seconds
Started Dec 27 01:36:26 PM PST 23
Finished Dec 27 01:36:39 PM PST 23
Peak memory 234840 kb
Host smart-c2267b7b-bc74-4354-bb0e-2584d5227b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356587194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1356587194
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1163234934
Short name T1651
Test name
Test status
Simulation time 6757255958 ps
CPU time 10.86 seconds
Started Dec 27 01:36:13 PM PST 23
Finished Dec 27 01:36:25 PM PST 23
Peak memory 218844 kb
Host smart-b24cfc9d-d531-4a4f-9292-ed951e450e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163234934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1163234934
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.4127212068
Short name T594
Test name
Test status
Simulation time 235252067 ps
CPU time 3.19 seconds
Started Dec 27 01:36:01 PM PST 23
Finished Dec 27 01:36:06 PM PST 23
Peak memory 237940 kb
Host smart-107f0299-a3a8-4bf5-90a6-0643474f45d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127212068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.4127212068
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_perf.889926868
Short name T1037
Test name
Test status
Simulation time 17400900002 ps
CPU time 439.06 seconds
Started Dec 27 01:35:47 PM PST 23
Finished Dec 27 01:43:07 PM PST 23
Peak memory 250768 kb
Host smart-4236f6cc-653a-4ed5-901d-55e88ffac466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889926868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_perf.889926868
Directory /workspace/39.spi_device_perf/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.589769731
Short name T1350
Test name
Test status
Simulation time 339690304 ps
CPU time 4.7 seconds
Started Dec 27 01:36:29 PM PST 23
Finished Dec 27 01:36:34 PM PST 23
Peak memory 220852 kb
Host smart-c4a8e0e4-f04e-427a-9208-1c878d504c69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=589769731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.589769731
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_rx_async_fifo_reset.574057686
Short name T867
Test name
Test status
Simulation time 166851987 ps
CPU time 0.92 seconds
Started Dec 27 01:36:03 PM PST 23
Finished Dec 27 01:36:05 PM PST 23
Peak memory 208428 kb
Host smart-11cf38e0-b68c-4aa9-a18b-3bc9534eb950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574057686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_rx_async_fifo_reset.574057686
Directory /workspace/39.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/39.spi_device_rx_timeout.4195977991
Short name T1573
Test name
Test status
Simulation time 2196858648 ps
CPU time 5.47 seconds
Started Dec 27 01:36:04 PM PST 23
Finished Dec 27 01:36:11 PM PST 23
Peak memory 216932 kb
Host smart-e1ac1dae-5dd2-49b7-8441-c06708a44404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195977991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_rx_timeout.4195977991
Directory /workspace/39.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/39.spi_device_smoke.4277950183
Short name T949
Test name
Test status
Simulation time 47705959 ps
CPU time 1.14 seconds
Started Dec 27 01:36:14 PM PST 23
Finished Dec 27 01:36:16 PM PST 23
Peak memory 207972 kb
Host smart-56372974-0ef9-4774-addb-edac3fd0c738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277950183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_smoke.4277950183
Directory /workspace/39.spi_device_smoke/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1755559164
Short name T152
Test name
Test status
Simulation time 42664617082 ps
CPU time 684.02 seconds
Started Dec 27 01:36:16 PM PST 23
Finished Dec 27 01:47:41 PM PST 23
Peak memory 348744 kb
Host smart-2d5b911a-9060-4dc7-9dee-c857a26b9216
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755559164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1755559164
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.801386138
Short name T657
Test name
Test status
Simulation time 3068590694 ps
CPU time 14.92 seconds
Started Dec 27 01:36:11 PM PST 23
Finished Dec 27 01:36:27 PM PST 23
Peak memory 220916 kb
Host smart-01de8d0a-7c77-4891-88b2-f07522c2de52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801386138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.801386138
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2328524871
Short name T1353
Test name
Test status
Simulation time 5355164470 ps
CPU time 9.69 seconds
Started Dec 27 01:36:09 PM PST 23
Finished Dec 27 01:36:20 PM PST 23
Peak memory 216956 kb
Host smart-7ce8d543-958b-4e5d-995e-0d68d7dddc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328524871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2328524871
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3040763217
Short name T565
Test name
Test status
Simulation time 47395480 ps
CPU time 0.81 seconds
Started Dec 27 01:36:17 PM PST 23
Finished Dec 27 01:36:20 PM PST 23
Peak memory 206772 kb
Host smart-793fba26-2f74-46f4-874a-87e9c2fd9c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040763217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3040763217
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_tx_async_fifo_reset.2094308458
Short name T529
Test name
Test status
Simulation time 16019677 ps
CPU time 0.76 seconds
Started Dec 27 01:36:08 PM PST 23
Finished Dec 27 01:36:10 PM PST 23
Peak memory 208340 kb
Host smart-399d140c-f1b4-40dc-ae19-c03d63b0a7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094308458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tx_async_fifo_reset.2094308458
Directory /workspace/39.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/39.spi_device_txrx.3590686140
Short name T858
Test name
Test status
Simulation time 23605642605 ps
CPU time 287.8 seconds
Started Dec 27 01:36:08 PM PST 23
Finished Dec 27 01:40:57 PM PST 23
Peak memory 337496 kb
Host smart-534003da-418c-44a4-8f4d-cfda93cab8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590686140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_txrx.3590686140
Directory /workspace/39.spi_device_txrx/latest

Test location /workspace/coverage/default/39.spi_device_upload.3205552763
Short name T1108
Test name
Test status
Simulation time 3307908813 ps
CPU time 8.27 seconds
Started Dec 27 01:36:19 PM PST 23
Finished Dec 27 01:36:28 PM PST 23
Peak memory 221376 kb
Host smart-df2861d3-4a31-41c3-9bf2-acdd903eee56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205552763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3205552763
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_abort.3620016563
Short name T825
Test name
Test status
Simulation time 41318246 ps
CPU time 0.75 seconds
Started Dec 27 01:30:17 PM PST 23
Finished Dec 27 01:30:20 PM PST 23
Peak memory 206656 kb
Host smart-06458e0d-0dd9-4357-ae2a-4b4f40d2174d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620016563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_abort.3620016563
Directory /workspace/4.spi_device_abort/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.4235306222
Short name T1744
Test name
Test status
Simulation time 11359717 ps
CPU time 0.69 seconds
Started Dec 27 01:30:22 PM PST 23
Finished Dec 27 01:30:24 PM PST 23
Peak memory 206464 kb
Host smart-4c2f216b-4493-41cb-80f0-a20e94ef3a8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235306222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.4
235306222
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_bit_transfer.423753222
Short name T643
Test name
Test status
Simulation time 309555921 ps
CPU time 2.21 seconds
Started Dec 27 01:30:38 PM PST 23
Finished Dec 27 01:30:41 PM PST 23
Peak memory 216776 kb
Host smart-6166f823-ad86-4a13-a1c9-4b6fa6a11f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423753222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_bit_transfer.423753222
Directory /workspace/4.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/4.spi_device_byte_transfer.3616551863
Short name T844
Test name
Test status
Simulation time 122402744 ps
CPU time 2.68 seconds
Started Dec 27 01:30:17 PM PST 23
Finished Dec 27 01:30:22 PM PST 23
Peak memory 216876 kb
Host smart-9fa2e2de-2f2f-4f6f-a004-d3ed5b21c1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616551863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_byte_transfer.3616551863
Directory /workspace/4.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.4216841405
Short name T1003
Test name
Test status
Simulation time 752224888 ps
CPU time 4.03 seconds
Started Dec 27 01:30:23 PM PST 23
Finished Dec 27 01:30:28 PM PST 23
Peak memory 220484 kb
Host smart-313dcc5a-d704-47ed-864b-c20957033351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216841405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.4216841405
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3833385709
Short name T860
Test name
Test status
Simulation time 36148827 ps
CPU time 0.76 seconds
Started Dec 27 01:30:30 PM PST 23
Finished Dec 27 01:30:32 PM PST 23
Peak memory 206468 kb
Host smart-739be092-eb3f-40cf-8333-78e3e573ba17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833385709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3833385709
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_dummy_item_extra_dly.3069181843
Short name T626
Test name
Test status
Simulation time 63846027005 ps
CPU time 526.81 seconds
Started Dec 27 01:30:14 PM PST 23
Finished Dec 27 01:39:05 PM PST 23
Peak memory 250740 kb
Host smart-2bee839d-e935-470a-8515-48144dacbb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069181843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_dummy_item_extra_dly.3069181843
Directory /workspace/4.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/4.spi_device_extreme_fifo_size.759749934
Short name T962
Test name
Test status
Simulation time 319208709257 ps
CPU time 1449.12 seconds
Started Dec 27 01:30:09 PM PST 23
Finished Dec 27 01:54:22 PM PST 23
Peak memory 225088 kb
Host smart-a6a4b06b-9a04-4bdf-a0fa-1df0faa3894f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759749934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_extreme_fifo_size.759749934
Directory /workspace/4.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/4.spi_device_fifo_full.3420056503
Short name T1401
Test name
Test status
Simulation time 43657105826 ps
CPU time 210.36 seconds
Started Dec 27 01:30:46 PM PST 23
Finished Dec 27 01:34:17 PM PST 23
Peak memory 275372 kb
Host smart-63cc1dfc-ba32-4064-9c8e-df0d37af87bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420056503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_fifo_full.3420056503
Directory /workspace/4.spi_device_fifo_full/latest

Test location /workspace/coverage/default/4.spi_device_fifo_underflow_overflow.458744691
Short name T1579
Test name
Test status
Simulation time 18562301927 ps
CPU time 192.99 seconds
Started Dec 27 01:30:22 PM PST 23
Finished Dec 27 01:33:37 PM PST 23
Peak memory 368808 kb
Host smart-4f3fbe0c-9854-4c65-ab15-1b32a7d78007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458744691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_fifo_underflow_overflo
w.458744691
Directory /workspace/4.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3374330086
Short name T1432
Test name
Test status
Simulation time 9446140710 ps
CPU time 49.98 seconds
Started Dec 27 01:30:43 PM PST 23
Finished Dec 27 01:31:34 PM PST 23
Peak memory 237400 kb
Host smart-5e659a48-1cb6-4fa9-8c51-ca76c19968bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374330086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3374330086
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2528389341
Short name T817
Test name
Test status
Simulation time 57843372959 ps
CPU time 131.5 seconds
Started Dec 27 01:30:21 PM PST 23
Finished Dec 27 01:32:34 PM PST 23
Peak memory 255952 kb
Host smart-a5d48433-da46-4fa3-bb13-f72bfb708a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528389341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2528389341
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1401116937
Short name T1490
Test name
Test status
Simulation time 21798354606 ps
CPU time 209.85 seconds
Started Dec 27 01:30:23 PM PST 23
Finished Dec 27 01:33:54 PM PST 23
Peak memory 257972 kb
Host smart-c5449ecf-8a75-4ed3-8943-6fc6e160f58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401116937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1401116937
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3750588954
Short name T1525
Test name
Test status
Simulation time 1121137566 ps
CPU time 5.18 seconds
Started Dec 27 01:30:37 PM PST 23
Finished Dec 27 01:30:43 PM PST 23
Peak memory 221652 kb
Host smart-50461079-c497-44c1-803b-1d9d7b715eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750588954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3750588954
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_intr.1957347425
Short name T533
Test name
Test status
Simulation time 11184460195 ps
CPU time 28.63 seconds
Started Dec 27 01:30:15 PM PST 23
Finished Dec 27 01:30:47 PM PST 23
Peak memory 218048 kb
Host smart-ecc77ac8-0eb7-4f94-822f-900e19c20449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957347425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intr.1957347425
Directory /workspace/4.spi_device_intr/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1736717906
Short name T1219
Test name
Test status
Simulation time 2982666463 ps
CPU time 6.48 seconds
Started Dec 27 01:30:26 PM PST 23
Finished Dec 27 01:30:34 PM PST 23
Peak memory 219944 kb
Host smart-2c774772-cfad-4a1e-8326-7ef209a9bd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736717906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1736717906
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2780980024
Short name T915
Test name
Test status
Simulation time 106362277 ps
CPU time 1.07 seconds
Started Dec 27 01:30:34 PM PST 23
Finished Dec 27 01:30:36 PM PST 23
Peak memory 218884 kb
Host smart-9041c756-a4a6-490d-81a5-eedf4c3bdf0b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780980024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2780980024
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3546111292
Short name T1012
Test name
Test status
Simulation time 2483923860 ps
CPU time 11.16 seconds
Started Dec 27 01:30:33 PM PST 23
Finished Dec 27 01:30:51 PM PST 23
Peak memory 241388 kb
Host smart-935eb3a8-45cd-40ec-a9f7-14c2d9f7d4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546111292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3546111292
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1106350331
Short name T1082
Test name
Test status
Simulation time 4850546556 ps
CPU time 17.24 seconds
Started Dec 27 01:30:31 PM PST 23
Finished Dec 27 01:30:50 PM PST 23
Peak memory 234560 kb
Host smart-5bd4a858-2b9f-4d34-b679-44a5058aafb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106350331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1106350331
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_perf.1750080131
Short name T908
Test name
Test status
Simulation time 57914840506 ps
CPU time 1199.9 seconds
Started Dec 27 01:30:22 PM PST 23
Finished Dec 27 01:50:24 PM PST 23
Peak memory 265688 kb
Host smart-cb698ee4-2b05-4dec-841b-58f8c528e246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750080131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_perf.1750080131
Directory /workspace/4.spi_device_perf/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.862933566
Short name T1590
Test name
Test status
Simulation time 28772865 ps
CPU time 0.75 seconds
Started Dec 27 01:30:21 PM PST 23
Finished Dec 27 01:30:23 PM PST 23
Peak memory 216736 kb
Host smart-2e8b4c8d-ba44-4d2f-aabe-379cb7f8b75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862933566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.862933566
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3077368283
Short name T792
Test name
Test status
Simulation time 1700665603 ps
CPU time 8.19 seconds
Started Dec 27 01:30:56 PM PST 23
Finished Dec 27 01:31:05 PM PST 23
Peak memory 220732 kb
Host smart-7b92dc6d-af06-495b-8cad-d17ac6748fb6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3077368283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3077368283
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_rx_async_fifo_reset.3016416398
Short name T1051
Test name
Test status
Simulation time 28476849 ps
CPU time 0.91 seconds
Started Dec 27 01:30:33 PM PST 23
Finished Dec 27 01:30:35 PM PST 23
Peak memory 208508 kb
Host smart-d548d939-e04b-4255-afd4-16b1bb2d86c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016416398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_rx_async_fifo_reset.3016416398
Directory /workspace/4.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/4.spi_device_rx_timeout.674259567
Short name T1629
Test name
Test status
Simulation time 3144006627 ps
CPU time 6.01 seconds
Started Dec 27 01:30:30 PM PST 23
Finished Dec 27 01:30:38 PM PST 23
Peak memory 216800 kb
Host smart-5f4edd82-d6a1-41a4-8bc8-677100b06300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674259567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_rx_timeout.674259567
Directory /workspace/4.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1771817195
Short name T111
Test name
Test status
Simulation time 596550168 ps
CPU time 1.1 seconds
Started Dec 27 01:30:15 PM PST 23
Finished Dec 27 01:30:20 PM PST 23
Peak memory 237068 kb
Host smart-ebbdbd82-380f-47dc-aa1e-a5daf5cfe96c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771817195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1771817195
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_smoke.849786496
Short name T842
Test name
Test status
Simulation time 41957660 ps
CPU time 1.02 seconds
Started Dec 27 01:30:11 PM PST 23
Finished Dec 27 01:30:17 PM PST 23
Peak memory 208252 kb
Host smart-e81a74df-917b-409b-9c7d-25fbaecfe639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849786496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_smoke.849786496
Directory /workspace/4.spi_device_smoke/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.666164563
Short name T1020
Test name
Test status
Simulation time 8528255912 ps
CPU time 32.44 seconds
Started Dec 27 01:30:30 PM PST 23
Finished Dec 27 01:31:04 PM PST 23
Peak memory 216860 kb
Host smart-bce1bb0f-c2aa-47bc-9ed2-3eb453f9badb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666164563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.666164563
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3068643545
Short name T1009
Test name
Test status
Simulation time 796585508 ps
CPU time 3.98 seconds
Started Dec 27 01:30:09 PM PST 23
Finished Dec 27 01:30:16 PM PST 23
Peak memory 216756 kb
Host smart-7cd41ddf-f916-4132-9299-a8e0823b89f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068643545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3068643545
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3200194429
Short name T656
Test name
Test status
Simulation time 141912760 ps
CPU time 0.98 seconds
Started Dec 27 01:30:30 PM PST 23
Finished Dec 27 01:30:32 PM PST 23
Peak memory 206868 kb
Host smart-5898aed7-a845-4aec-ae2b-69b1e797ff3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200194429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3200194429
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_tx_async_fifo_reset.2687299
Short name T56
Test name
Test status
Simulation time 16951408 ps
CPU time 0.79 seconds
Started Dec 27 01:30:26 PM PST 23
Finished Dec 27 01:30:28 PM PST 23
Peak memory 208476 kb
Host smart-ae1f0708-062d-4d71-b1ec-c9646c5bac3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tx_async_fifo_reset.2687299
Directory /workspace/4.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/4.spi_device_txrx.2008871316
Short name T625
Test name
Test status
Simulation time 31064472087 ps
CPU time 211.69 seconds
Started Dec 27 01:30:29 PM PST 23
Finished Dec 27 01:34:02 PM PST 23
Peak memory 268000 kb
Host smart-6eb25d6f-021c-4df1-a06e-94ccea25db21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008871316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_txrx.2008871316
Directory /workspace/4.spi_device_txrx/latest

Test location /workspace/coverage/default/4.spi_device_upload.2485271907
Short name T290
Test name
Test status
Simulation time 1340210908 ps
CPU time 10.64 seconds
Started Dec 27 01:30:34 PM PST 23
Finished Dec 27 01:30:46 PM PST 23
Peak memory 244992 kb
Host smart-e35ca882-946b-4414-9c7e-ada345afa8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485271907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2485271907
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_abort.1138111791
Short name T837
Test name
Test status
Simulation time 15741041 ps
CPU time 0.76 seconds
Started Dec 27 01:36:32 PM PST 23
Finished Dec 27 01:36:33 PM PST 23
Peak memory 206536 kb
Host smart-34670505-4892-4d21-8246-5b00f081b308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138111791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_abort.1138111791
Directory /workspace/40.spi_device_abort/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3526947988
Short name T658
Test name
Test status
Simulation time 106799074 ps
CPU time 0.7 seconds
Started Dec 27 01:37:22 PM PST 23
Finished Dec 27 01:37:24 PM PST 23
Peak memory 206420 kb
Host smart-1007c192-f422-4c5e-9e43-359cf6777052
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526947988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3526947988
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_bit_transfer.1634855029
Short name T671
Test name
Test status
Simulation time 577396782 ps
CPU time 1.78 seconds
Started Dec 27 01:36:29 PM PST 23
Finished Dec 27 01:36:32 PM PST 23
Peak memory 216800 kb
Host smart-2ac7df0e-bc8a-49a1-bab8-8ec59d0cd319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634855029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_bit_transfer.1634855029
Directory /workspace/40.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/40.spi_device_byte_transfer.1128906829
Short name T750
Test name
Test status
Simulation time 409158750 ps
CPU time 2.74 seconds
Started Dec 27 01:36:31 PM PST 23
Finished Dec 27 01:36:34 PM PST 23
Peak memory 216768 kb
Host smart-b89146d7-865b-44b9-8f5a-c7c4e4ba6865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128906829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_byte_transfer.1128906829
Directory /workspace/40.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.725903056
Short name T1527
Test name
Test status
Simulation time 1303549019 ps
CPU time 4.17 seconds
Started Dec 27 01:36:53 PM PST 23
Finished Dec 27 01:36:58 PM PST 23
Peak memory 222176 kb
Host smart-68a5b89f-799c-435e-975a-08f27cecc342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725903056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.725903056
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.4026560392
Short name T872
Test name
Test status
Simulation time 65179222 ps
CPU time 0.77 seconds
Started Dec 27 01:36:26 PM PST 23
Finished Dec 27 01:36:28 PM PST 23
Peak memory 206464 kb
Host smart-2b82735d-4192-4b7c-87c2-a0cffdd51703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026560392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4026560392
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_dummy_item_extra_dly.342219533
Short name T1398
Test name
Test status
Simulation time 47911271304 ps
CPU time 379.92 seconds
Started Dec 27 01:36:22 PM PST 23
Finished Dec 27 01:42:44 PM PST 23
Peak memory 266100 kb
Host smart-0b0db43b-e8d2-4765-8149-65cd6bc37305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342219533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_dummy_item_extra_dly.342219533
Directory /workspace/40.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/40.spi_device_extreme_fifo_size.2535278142
Short name T789
Test name
Test status
Simulation time 62786848376 ps
CPU time 840.53 seconds
Started Dec 27 01:36:17 PM PST 23
Finished Dec 27 01:50:20 PM PST 23
Peak memory 221052 kb
Host smart-b146b0c5-9d53-43de-a0a9-833ec54a0f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535278142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_extreme_fifo_size.2535278142
Directory /workspace/40.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/40.spi_device_fifo_full.2225604021
Short name T564
Test name
Test status
Simulation time 55920335801 ps
CPU time 1633.17 seconds
Started Dec 27 01:36:21 PM PST 23
Finished Dec 27 02:03:36 PM PST 23
Peak memory 249780 kb
Host smart-012b975b-9a65-4712-93ad-b7c82e2a071c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225604021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_fifo_full.2225604021
Directory /workspace/40.spi_device_fifo_full/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3262372970
Short name T975
Test name
Test status
Simulation time 101999576998 ps
CPU time 137.17 seconds
Started Dec 27 01:36:49 PM PST 23
Finished Dec 27 01:39:07 PM PST 23
Peak memory 257436 kb
Host smart-56723bc9-7590-4bb8-8dfb-d1127f0821ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262372970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3262372970
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3107031420
Short name T785
Test name
Test status
Simulation time 4973017168 ps
CPU time 31.77 seconds
Started Dec 27 01:36:57 PM PST 23
Finished Dec 27 01:37:29 PM PST 23
Peak memory 241028 kb
Host smart-c1da9cc9-34ee-4776-b6d4-bb10f884e5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107031420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3107031420
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.4077868326
Short name T622
Test name
Test status
Simulation time 5207785281 ps
CPU time 84.23 seconds
Started Dec 27 01:37:38 PM PST 23
Finished Dec 27 01:39:08 PM PST 23
Peak memory 256128 kb
Host smart-32ba7c3b-6e75-4128-8968-e8d8a541b092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077868326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.4077868326
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.97089935
Short name T1328
Test name
Test status
Simulation time 18286305140 ps
CPU time 25.19 seconds
Started Dec 27 01:37:30 PM PST 23
Finished Dec 27 01:37:56 PM PST 23
Peak memory 232492 kb
Host smart-3ff8caf3-db17-444a-b463-e6ee64e2b71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97089935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.97089935
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2676769028
Short name T1214
Test name
Test status
Simulation time 2925619724 ps
CPU time 5.61 seconds
Started Dec 27 01:36:47 PM PST 23
Finished Dec 27 01:36:54 PM PST 23
Peak memory 238724 kb
Host smart-c62255df-3952-404a-a049-6757a79622fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676769028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2676769028
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_intr.2554585112
Short name T1713
Test name
Test status
Simulation time 10966794613 ps
CPU time 27.86 seconds
Started Dec 27 01:36:33 PM PST 23
Finished Dec 27 01:37:01 PM PST 23
Peak memory 222892 kb
Host smart-7ccd6b17-bc07-42df-8a43-38514f805de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554585112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intr.2554585112
Directory /workspace/40.spi_device_intr/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.304418587
Short name T1441
Test name
Test status
Simulation time 7645069521 ps
CPU time 25.22 seconds
Started Dec 27 01:36:50 PM PST 23
Finished Dec 27 01:37:16 PM PST 23
Peak memory 231088 kb
Host smart-65a0f494-39ef-4db5-ae4a-e5663aca0b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304418587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.304418587
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2827315541
Short name T270
Test name
Test status
Simulation time 6191801543 ps
CPU time 12.73 seconds
Started Dec 27 01:36:51 PM PST 23
Finished Dec 27 01:37:04 PM PST 23
Peak memory 219548 kb
Host smart-c3605d38-489f-4f7b-8d6d-b8c682231c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827315541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2827315541
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2871455386
Short name T217
Test name
Test status
Simulation time 2186532165 ps
CPU time 6.64 seconds
Started Dec 27 01:36:33 PM PST 23
Finished Dec 27 01:36:40 PM PST 23
Peak memory 249616 kb
Host smart-0d8487bf-3fb6-4866-ac66-9b22ad7e1602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871455386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2871455386
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_perf.3117313250
Short name T1250
Test name
Test status
Simulation time 6518934642 ps
CPU time 468.69 seconds
Started Dec 27 01:36:16 PM PST 23
Finished Dec 27 01:44:05 PM PST 23
Peak memory 257412 kb
Host smart-0dcd9f34-2ecd-49cb-9478-7b23caf6bec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117313250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_perf.3117313250
Directory /workspace/40.spi_device_perf/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4072602607
Short name T1711
Test name
Test status
Simulation time 389894664 ps
CPU time 4.1 seconds
Started Dec 27 01:37:28 PM PST 23
Finished Dec 27 01:37:33 PM PST 23
Peak memory 218572 kb
Host smart-80bcedc2-b0ed-47b2-ae32-eca659477bef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4072602607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4072602607
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_rx_async_fifo_reset.3782068761
Short name T1712
Test name
Test status
Simulation time 425220895 ps
CPU time 0.88 seconds
Started Dec 27 01:36:21 PM PST 23
Finished Dec 27 01:36:23 PM PST 23
Peak memory 208452 kb
Host smart-e070fd72-a47c-4924-9339-ebcfb2292adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782068761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_rx_async_fifo_reset.3782068761
Directory /workspace/40.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/40.spi_device_rx_timeout.1479488702
Short name T859
Test name
Test status
Simulation time 508764509 ps
CPU time 5.06 seconds
Started Dec 27 01:37:22 PM PST 23
Finished Dec 27 01:37:28 PM PST 23
Peak memory 216732 kb
Host smart-dc4dc1b8-ba2f-44ef-a3aa-eb0c673a6648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479488702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_rx_timeout.1479488702
Directory /workspace/40.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/40.spi_device_smoke.2001241651
Short name T833
Test name
Test status
Simulation time 34683489 ps
CPU time 0.85 seconds
Started Dec 27 01:36:30 PM PST 23
Finished Dec 27 01:36:31 PM PST 23
Peak memory 207860 kb
Host smart-abbf8c34-44ff-48ce-88dc-e6df9be50630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001241651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_smoke.2001241651
Directory /workspace/40.spi_device_smoke/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2377498287
Short name T1703
Test name
Test status
Simulation time 649021752687 ps
CPU time 2750.66 seconds
Started Dec 27 01:37:34 PM PST 23
Finished Dec 27 02:23:27 PM PST 23
Peak memory 353360 kb
Host smart-8e5a8cb3-19fc-498c-a054-7ce1032633fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377498287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2377498287
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1109795850
Short name T117
Test name
Test status
Simulation time 766957157 ps
CPU time 14.19 seconds
Started Dec 27 01:36:50 PM PST 23
Finished Dec 27 01:37:05 PM PST 23
Peak memory 220440 kb
Host smart-bd00956d-f809-432c-a43c-52e78d73bac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109795850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1109795850
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2271117962
Short name T1603
Test name
Test status
Simulation time 15966483333 ps
CPU time 9.54 seconds
Started Dec 27 01:37:25 PM PST 23
Finished Dec 27 01:37:36 PM PST 23
Peak memory 216852 kb
Host smart-500b317d-9caa-4043-962e-a779fc53469c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271117962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2271117962
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1155879900
Short name T1166
Test name
Test status
Simulation time 407010778 ps
CPU time 9.5 seconds
Started Dec 27 01:36:15 PM PST 23
Finished Dec 27 01:36:25 PM PST 23
Peak memory 216848 kb
Host smart-c5fe8c17-c71d-4dc6-847f-56c1ed9ec878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155879900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1155879900
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.447852219
Short name T1600
Test name
Test status
Simulation time 110515973 ps
CPU time 0.86 seconds
Started Dec 27 01:36:32 PM PST 23
Finished Dec 27 01:36:34 PM PST 23
Peak memory 206852 kb
Host smart-b8057371-4e86-49e6-8980-30989d3d05c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447852219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.447852219
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_tx_async_fifo_reset.735192894
Short name T1737
Test name
Test status
Simulation time 25463912 ps
CPU time 0.78 seconds
Started Dec 27 01:36:12 PM PST 23
Finished Dec 27 01:36:13 PM PST 23
Peak memory 208440 kb
Host smart-a6a5d14c-3748-4e57-9486-39ed7e6b3473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735192894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tx_async_fifo_reset.735192894
Directory /workspace/40.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/40.spi_device_txrx.3617744816
Short name T791
Test name
Test status
Simulation time 18791736303 ps
CPU time 204.61 seconds
Started Dec 27 01:36:25 PM PST 23
Finished Dec 27 01:39:51 PM PST 23
Peak memory 297800 kb
Host smart-399f6fdf-3722-4356-8088-d2f8b11a4016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617744816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_txrx.3617744816
Directory /workspace/40.spi_device_txrx/latest

Test location /workspace/coverage/default/40.spi_device_upload.3231665918
Short name T1072
Test name
Test status
Simulation time 36792686743 ps
CPU time 28.29 seconds
Started Dec 27 01:36:56 PM PST 23
Finished Dec 27 01:37:25 PM PST 23
Peak memory 247340 kb
Host smart-79b4f6cc-e1b0-4ccf-80d4-bc90243b772b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231665918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3231665918
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_abort.1957353017
Short name T91
Test name
Test status
Simulation time 37563176 ps
CPU time 0.75 seconds
Started Dec 27 01:37:05 PM PST 23
Finished Dec 27 01:37:06 PM PST 23
Peak memory 206548 kb
Host smart-3819bbee-f0bc-4fd1-9546-a46a018dd3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957353017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_abort.1957353017
Directory /workspace/41.spi_device_abort/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1247151898
Short name T797
Test name
Test status
Simulation time 81054910 ps
CPU time 0.72 seconds
Started Dec 27 01:37:18 PM PST 23
Finished Dec 27 01:37:20 PM PST 23
Peak memory 206504 kb
Host smart-6030fac1-10a1-490e-b796-7cf9c0eb63c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247151898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1247151898
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_bit_transfer.2169906907
Short name T939
Test name
Test status
Simulation time 552752469 ps
CPU time 2.78 seconds
Started Dec 27 01:37:26 PM PST 23
Finished Dec 27 01:37:31 PM PST 23
Peak memory 216704 kb
Host smart-7deeae24-2cdc-412b-86a5-ff4962df053a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169906907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_bit_transfer.2169906907
Directory /workspace/41.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/41.spi_device_byte_transfer.3503190717
Short name T639
Test name
Test status
Simulation time 466100227 ps
CPU time 3.49 seconds
Started Dec 27 01:37:01 PM PST 23
Finished Dec 27 01:37:05 PM PST 23
Peak memory 216780 kb
Host smart-40aa3451-f74f-4871-96f7-50f1a7b3e77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503190717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_byte_transfer.3503190717
Directory /workspace/41.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1658045459
Short name T857
Test name
Test status
Simulation time 3349877761 ps
CPU time 5.72 seconds
Started Dec 27 01:37:01 PM PST 23
Finished Dec 27 01:37:07 PM PST 23
Peak memory 238508 kb
Host smart-235cee4b-4047-4af5-973a-5a8be8f77b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658045459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1658045459
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1934222734
Short name T826
Test name
Test status
Simulation time 34231853 ps
CPU time 0.76 seconds
Started Dec 27 01:37:07 PM PST 23
Finished Dec 27 01:37:08 PM PST 23
Peak memory 207604 kb
Host smart-1e4f9a8d-7b2b-4a4b-9138-c4da09790851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934222734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1934222734
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_dummy_item_extra_dly.3702104249
Short name T1734
Test name
Test status
Simulation time 53735791732 ps
CPU time 217.61 seconds
Started Dec 27 01:37:22 PM PST 23
Finished Dec 27 01:41:01 PM PST 23
Peak memory 296680 kb
Host smart-763dfe53-3572-44f5-bb4e-9143a2451582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702104249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_dummy_item_extra_dly.3702104249
Directory /workspace/41.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/41.spi_device_extreme_fifo_size.715492311
Short name T620
Test name
Test status
Simulation time 8299225845 ps
CPU time 60.15 seconds
Started Dec 27 01:37:20 PM PST 23
Finished Dec 27 01:38:21 PM PST 23
Peak memory 232144 kb
Host smart-5d3f8c8a-e787-4830-b243-cf7d1c24673a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715492311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_extreme_fifo_size.715492311
Directory /workspace/41.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/41.spi_device_fifo_full.2946816226
Short name T604
Test name
Test status
Simulation time 64652083845 ps
CPU time 951.03 seconds
Started Dec 27 01:36:52 PM PST 23
Finished Dec 27 01:52:44 PM PST 23
Peak memory 255008 kb
Host smart-fa9f3056-0f3f-4ffd-abac-e9143bee9c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946816226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_fifo_full.2946816226
Directory /workspace/41.spi_device_fifo_full/latest

Test location /workspace/coverage/default/41.spi_device_fifo_underflow_overflow.4005895107
Short name T1502
Test name
Test status
Simulation time 69659090602 ps
CPU time 484.53 seconds
Started Dec 27 01:36:56 PM PST 23
Finished Dec 27 01:45:02 PM PST 23
Peak memory 380924 kb
Host smart-c2fd9e61-f1eb-4594-85f7-c563d8b9c10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005895107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_fifo_underflow_overf
low.4005895107
Directory /workspace/41.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2463792749
Short name T1120
Test name
Test status
Simulation time 2979612460 ps
CPU time 8.39 seconds
Started Dec 27 01:36:55 PM PST 23
Finished Dec 27 01:37:04 PM PST 23
Peak memory 223480 kb
Host smart-347466e4-7025-4f73-9f80-4aa786f99769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463792749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2463792749
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2546314520
Short name T1311
Test name
Test status
Simulation time 13817889536 ps
CPU time 9.7 seconds
Started Dec 27 01:37:23 PM PST 23
Finished Dec 27 01:37:34 PM PST 23
Peak memory 221844 kb
Host smart-e2e4894a-8b21-4646-89e1-3095e09e244b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546314520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2546314520
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_intr.2569484310
Short name T763
Test name
Test status
Simulation time 27902598030 ps
CPU time 106.22 seconds
Started Dec 27 01:37:01 PM PST 23
Finished Dec 27 01:38:48 PM PST 23
Peak memory 237404 kb
Host smart-e596514d-3899-4fcf-8e86-40a3aa36e5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569484310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intr.2569484310
Directory /workspace/41.spi_device_intr/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1620884140
Short name T256
Test name
Test status
Simulation time 51891849666 ps
CPU time 40.2 seconds
Started Dec 27 01:36:54 PM PST 23
Finished Dec 27 01:37:36 PM PST 23
Peak memory 224948 kb
Host smart-4a6510c1-63b3-48e1-a042-cecaec0001dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620884140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1620884140
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3386087065
Short name T1150
Test name
Test status
Simulation time 3413577256 ps
CPU time 5.98 seconds
Started Dec 27 01:37:20 PM PST 23
Finished Dec 27 01:37:27 PM PST 23
Peak memory 219120 kb
Host smart-78386a37-28b7-4cef-a781-4b55c1524bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386087065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3386087065
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4153588764
Short name T1518
Test name
Test status
Simulation time 1058135016 ps
CPU time 6.81 seconds
Started Dec 27 01:36:52 PM PST 23
Finished Dec 27 01:36:59 PM PST 23
Peak memory 230540 kb
Host smart-00a24087-19d4-4f65-ba13-ff91a4d88839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153588764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4153588764
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_perf.3362379742
Short name T52
Test name
Test status
Simulation time 56933890092 ps
CPU time 347.67 seconds
Started Dec 27 01:37:21 PM PST 23
Finished Dec 27 01:43:10 PM PST 23
Peak memory 283384 kb
Host smart-7b124195-1185-4108-bc1c-7eacda066c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362379742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_perf.3362379742
Directory /workspace/41.spi_device_perf/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2654056241
Short name T1264
Test name
Test status
Simulation time 488078293 ps
CPU time 4.53 seconds
Started Dec 27 01:37:18 PM PST 23
Finished Dec 27 01:37:24 PM PST 23
Peak memory 234416 kb
Host smart-97155410-7315-4887-adb2-4630f8cbeb62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2654056241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2654056241
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_rx_async_fifo_reset.2903795116
Short name T153
Test name
Test status
Simulation time 43446701 ps
CPU time 0.91 seconds
Started Dec 27 01:37:41 PM PST 23
Finished Dec 27 01:37:48 PM PST 23
Peak memory 208388 kb
Host smart-4adcd068-9c7a-40cb-b1cf-491e7cc05d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903795116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_rx_async_fifo_reset.2903795116
Directory /workspace/41.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/41.spi_device_rx_timeout.2844203142
Short name T1520
Test name
Test status
Simulation time 865220936 ps
CPU time 4.81 seconds
Started Dec 27 01:36:58 PM PST 23
Finished Dec 27 01:37:04 PM PST 23
Peak memory 216800 kb
Host smart-3f3adaf3-ac3c-4a60-8cf5-fa26cc29b9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844203142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_rx_timeout.2844203142
Directory /workspace/41.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/41.spi_device_smoke.3277501347
Short name T1235
Test name
Test status
Simulation time 97003732 ps
CPU time 0.94 seconds
Started Dec 27 01:37:51 PM PST 23
Finished Dec 27 01:37:56 PM PST 23
Peak memory 207976 kb
Host smart-ef62ef4f-6d98-40cc-a77c-fe311abf0e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277501347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_smoke.3277501347
Directory /workspace/41.spi_device_smoke/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3557036657
Short name T1103
Test name
Test status
Simulation time 180034925419 ps
CPU time 819.98 seconds
Started Dec 27 01:37:22 PM PST 23
Finished Dec 27 01:51:04 PM PST 23
Peak memory 379128 kb
Host smart-2807ac88-4032-4b8e-b93d-b588434aff65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557036657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3557036657
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1372840882
Short name T352
Test name
Test status
Simulation time 7275824508 ps
CPU time 15.6 seconds
Started Dec 27 01:37:20 PM PST 23
Finished Dec 27 01:37:37 PM PST 23
Peak memory 217060 kb
Host smart-4cd9cb46-5b83-4e68-aa8b-f519df2c6f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372840882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1372840882
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3724726038
Short name T1546
Test name
Test status
Simulation time 1783681685 ps
CPU time 1.72 seconds
Started Dec 27 01:37:15 PM PST 23
Finished Dec 27 01:37:17 PM PST 23
Peak memory 207972 kb
Host smart-5396e523-2fc6-42b7-90ed-fdd20c640e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724726038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3724726038
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3519622399
Short name T1329
Test name
Test status
Simulation time 21264037 ps
CPU time 0.87 seconds
Started Dec 27 01:36:47 PM PST 23
Finished Dec 27 01:36:49 PM PST 23
Peak memory 207972 kb
Host smart-54b411c2-eb10-4700-aca7-6c69c52a6aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519622399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3519622399
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.414947770
Short name T74
Test name
Test status
Simulation time 77859347 ps
CPU time 0.76 seconds
Started Dec 27 01:36:57 PM PST 23
Finished Dec 27 01:36:58 PM PST 23
Peak memory 206840 kb
Host smart-2190a98f-d1d2-4708-bc66-ac69c0570a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414947770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.414947770
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_tx_async_fifo_reset.1192999933
Short name T1118
Test name
Test status
Simulation time 14653701 ps
CPU time 0.75 seconds
Started Dec 27 01:37:22 PM PST 23
Finished Dec 27 01:37:23 PM PST 23
Peak memory 208432 kb
Host smart-7f457049-b29a-4c33-8474-ffeb1949d7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192999933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tx_async_fifo_reset.1192999933
Directory /workspace/41.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/41.spi_device_txrx.841700393
Short name T1152
Test name
Test status
Simulation time 20387105810 ps
CPU time 183.07 seconds
Started Dec 27 01:37:30 PM PST 23
Finished Dec 27 01:40:34 PM PST 23
Peak memory 292604 kb
Host smart-d3d41c63-c4c1-4bb0-a8b8-d002d4fe4053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841700393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_txrx.841700393
Directory /workspace/41.spi_device_txrx/latest

Test location /workspace/coverage/default/41.spi_device_upload.4073165481
Short name T1554
Test name
Test status
Simulation time 14852841937 ps
CPU time 15.83 seconds
Started Dec 27 01:36:55 PM PST 23
Finished Dec 27 01:37:12 PM PST 23
Peak memory 247772 kb
Host smart-78964e72-d851-4800-8b5b-dd4ac34b22fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073165481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.4073165481
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_abort.2993594839
Short name T1606
Test name
Test status
Simulation time 208871726 ps
CPU time 0.79 seconds
Started Dec 27 01:37:14 PM PST 23
Finished Dec 27 01:37:16 PM PST 23
Peak memory 206560 kb
Host smart-7a6c1019-97be-4165-9c01-f05bdcdbaf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993594839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_abort.2993594839
Directory /workspace/42.spi_device_abort/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.938348461
Short name T852
Test name
Test status
Simulation time 36160483 ps
CPU time 0.71 seconds
Started Dec 27 01:37:26 PM PST 23
Finished Dec 27 01:37:29 PM PST 23
Peak memory 206516 kb
Host smart-fefee9c7-717b-4fcb-aba6-44b8af5ba311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938348461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.938348461
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_bit_transfer.1474216761
Short name T1156
Test name
Test status
Simulation time 557214848 ps
CPU time 2.25 seconds
Started Dec 27 01:36:54 PM PST 23
Finished Dec 27 01:36:57 PM PST 23
Peak memory 216808 kb
Host smart-6cddc7d8-d02f-4f67-be72-53bd687e3afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474216761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_bit_transfer.1474216761
Directory /workspace/42.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/42.spi_device_byte_transfer.4098022394
Short name T821
Test name
Test status
Simulation time 199326953 ps
CPU time 2.98 seconds
Started Dec 27 01:37:42 PM PST 23
Finished Dec 27 01:37:51 PM PST 23
Peak memory 216712 kb
Host smart-d4cd8a3b-6fec-4927-9c49-cbabf40a5cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098022394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_byte_transfer.4098022394
Directory /workspace/42.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1541809827
Short name T938
Test name
Test status
Simulation time 5565993005 ps
CPU time 6.8 seconds
Started Dec 27 01:37:04 PM PST 23
Finished Dec 27 01:37:12 PM PST 23
Peak memory 220980 kb
Host smart-453f8446-ca9b-4f7f-bc67-20027dc34d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541809827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1541809827
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1068910283
Short name T895
Test name
Test status
Simulation time 19973030 ps
CPU time 0.73 seconds
Started Dec 27 01:37:42 PM PST 23
Finished Dec 27 01:37:48 PM PST 23
Peak memory 207512 kb
Host smart-6afd6369-aa2c-4718-b179-37d300a3f331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068910283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1068910283
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_dummy_item_extra_dly.2861245706
Short name T1404
Test name
Test status
Simulation time 164007374752 ps
CPU time 125.7 seconds
Started Dec 27 01:37:32 PM PST 23
Finished Dec 27 01:39:40 PM PST 23
Peak memory 257016 kb
Host smart-ea0c902c-f2ad-415a-9ce6-19efd4ab4aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861245706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_dummy_item_extra_dly.2861245706
Directory /workspace/42.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/42.spi_device_extreme_fifo_size.1915120683
Short name T1369
Test name
Test status
Simulation time 1078015705311 ps
CPU time 901.87 seconds
Started Dec 27 01:37:32 PM PST 23
Finished Dec 27 01:52:35 PM PST 23
Peak memory 225092 kb
Host smart-ac7fd554-4841-4298-a3ab-ab67bc793d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915120683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_extreme_fifo_size.1915120683
Directory /workspace/42.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/42.spi_device_fifo_full.1087949824
Short name T1145
Test name
Test status
Simulation time 282367488675 ps
CPU time 816.88 seconds
Started Dec 27 01:37:16 PM PST 23
Finished Dec 27 01:50:53 PM PST 23
Peak memory 300212 kb
Host smart-4fb01f94-da49-4a7e-acab-724ece763b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087949824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_fifo_full.1087949824
Directory /workspace/42.spi_device_fifo_full/latest

Test location /workspace/coverage/default/42.spi_device_fifo_underflow_overflow.2156208363
Short name T1676
Test name
Test status
Simulation time 13890160270 ps
CPU time 300.32 seconds
Started Dec 27 01:37:19 PM PST 23
Finished Dec 27 01:42:20 PM PST 23
Peak memory 391312 kb
Host smart-5d0bb5a1-2abc-476c-b5f8-a5651d296895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156208363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_fifo_underflow_overf
low.2156208363
Directory /workspace/42.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3484766347
Short name T341
Test name
Test status
Simulation time 14807919594 ps
CPU time 143.44 seconds
Started Dec 27 01:37:00 PM PST 23
Finished Dec 27 01:39:24 PM PST 23
Peak memory 265856 kb
Host smart-603de32b-6b11-432a-b951-c3c215edd0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484766347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3484766347
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.292477988
Short name T246
Test name
Test status
Simulation time 46427296352 ps
CPU time 333.21 seconds
Started Dec 27 01:36:53 PM PST 23
Finished Dec 27 01:42:27 PM PST 23
Peak memory 269088 kb
Host smart-b7cc7b5b-ac6c-47af-8ce0-0ad98f84ca40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292477988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.292477988
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3796342979
Short name T300
Test name
Test status
Simulation time 934191884 ps
CPU time 3.71 seconds
Started Dec 27 01:36:59 PM PST 23
Finished Dec 27 01:37:03 PM PST 23
Peak memory 218736 kb
Host smart-65882110-6886-4011-98e6-f6e2c0ffdfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796342979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3796342979
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_intr.3661346477
Short name T611
Test name
Test status
Simulation time 41460284902 ps
CPU time 40.09 seconds
Started Dec 27 01:38:21 PM PST 23
Finished Dec 27 01:39:03 PM PST 23
Peak memory 221320 kb
Host smart-2cc27f45-a308-49bc-9d43-2f289c1fc405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661346477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intr.3661346477
Directory /workspace/42.spi_device_intr/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1159683297
Short name T314
Test name
Test status
Simulation time 1891624220 ps
CPU time 5.87 seconds
Started Dec 27 01:36:48 PM PST 23
Finished Dec 27 01:36:55 PM PST 23
Peak memory 240120 kb
Host smart-28acdf91-9c0d-4a15-ba07-84ba7def7cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159683297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1159683297
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3374091294
Short name T342
Test name
Test status
Simulation time 7409887675 ps
CPU time 8.95 seconds
Started Dec 27 01:36:56 PM PST 23
Finished Dec 27 01:37:06 PM PST 23
Peak memory 220712 kb
Host smart-5dcb6554-7a53-41b9-8637-663b82f6e8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374091294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3374091294
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2705549030
Short name T317
Test name
Test status
Simulation time 8907499686 ps
CPU time 14.85 seconds
Started Dec 27 01:37:20 PM PST 23
Finished Dec 27 01:37:36 PM PST 23
Peak memory 230628 kb
Host smart-2f823fa1-1b84-4df9-b7fc-64c322b9665d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705549030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2705549030
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_perf.3689700892
Short name T509
Test name
Test status
Simulation time 39064768570 ps
CPU time 1317.94 seconds
Started Dec 27 01:37:23 PM PST 23
Finished Dec 27 01:59:22 PM PST 23
Peak memory 282304 kb
Host smart-5d80e3ab-963b-4f6c-8915-1bd0e6283fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689700892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_perf.3689700892
Directory /workspace/42.spi_device_perf/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.705150872
Short name T1405
Test name
Test status
Simulation time 925808417 ps
CPU time 4.52 seconds
Started Dec 27 01:37:00 PM PST 23
Finished Dec 27 01:37:05 PM PST 23
Peak memory 234132 kb
Host smart-6ee3692e-0420-4d6a-af6f-23fa738a073d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=705150872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.705150872
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_rx_async_fifo_reset.2087762818
Short name T1015
Test name
Test status
Simulation time 90496684 ps
CPU time 0.92 seconds
Started Dec 27 01:37:34 PM PST 23
Finished Dec 27 01:37:37 PM PST 23
Peak memory 208428 kb
Host smart-d9bb8d81-cdde-4262-8fad-c33d0676e9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087762818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_rx_async_fifo_reset.2087762818
Directory /workspace/42.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/42.spi_device_rx_timeout.1159954914
Short name T1578
Test name
Test status
Simulation time 643428574 ps
CPU time 5.06 seconds
Started Dec 27 01:37:30 PM PST 23
Finished Dec 27 01:37:35 PM PST 23
Peak memory 216720 kb
Host smart-b9cc80eb-53ad-4f03-b8fc-091c64d06446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159954914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_rx_timeout.1159954914
Directory /workspace/42.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/42.spi_device_smoke.375275848
Short name T1477
Test name
Test status
Simulation time 43649456 ps
CPU time 1.06 seconds
Started Dec 27 01:37:01 PM PST 23
Finished Dec 27 01:37:02 PM PST 23
Peak memory 207828 kb
Host smart-6dc6b67d-02c3-42c7-bdb3-3b4c0f7cd01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375275848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_smoke.375275848
Directory /workspace/42.spi_device_smoke/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.512990999
Short name T1591
Test name
Test status
Simulation time 169733644425 ps
CPU time 1099.12 seconds
Started Dec 27 01:36:55 PM PST 23
Finished Dec 27 01:55:15 PM PST 23
Peak memory 285036 kb
Host smart-3c9e8003-9d3e-46a4-95e4-779113e4b2dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512990999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.512990999
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2285160572
Short name T661
Test name
Test status
Simulation time 216319290 ps
CPU time 3.54 seconds
Started Dec 27 01:37:35 PM PST 23
Finished Dec 27 01:37:46 PM PST 23
Peak memory 216972 kb
Host smart-6bef043d-0e38-47fb-a46d-4e5bc09d40fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285160572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2285160572
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.508546250
Short name T1553
Test name
Test status
Simulation time 3024664485 ps
CPU time 9.18 seconds
Started Dec 27 01:37:55 PM PST 23
Finished Dec 27 01:38:07 PM PST 23
Peak memory 216784 kb
Host smart-0faf6466-4b9d-4a5f-8287-5277583ebe7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508546250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.508546250
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2148240486
Short name T1442
Test name
Test status
Simulation time 137846540 ps
CPU time 1.35 seconds
Started Dec 27 01:36:56 PM PST 23
Finished Dec 27 01:36:58 PM PST 23
Peak memory 208468 kb
Host smart-d04d234e-3873-4bb4-86d1-3ae150cd0d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148240486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2148240486
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tx_async_fifo_reset.753318758
Short name T756
Test name
Test status
Simulation time 19440231 ps
CPU time 0.78 seconds
Started Dec 27 01:37:08 PM PST 23
Finished Dec 27 01:37:09 PM PST 23
Peak memory 208460 kb
Host smart-a6ac2b00-16a7-47d6-9e0c-881c948927dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753318758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tx_async_fifo_reset.753318758
Directory /workspace/42.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/42.spi_device_txrx.3895514850
Short name T1198
Test name
Test status
Simulation time 83323239729 ps
CPU time 285.28 seconds
Started Dec 27 01:37:20 PM PST 23
Finished Dec 27 01:42:06 PM PST 23
Peak memory 272292 kb
Host smart-6b62255e-37cb-459f-86cf-a810a771a238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895514850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_txrx.3895514850
Directory /workspace/42.spi_device_txrx/latest

Test location /workspace/coverage/default/42.spi_device_upload.2971838642
Short name T214
Test name
Test status
Simulation time 32881033538 ps
CPU time 27.55 seconds
Started Dec 27 01:36:56 PM PST 23
Finished Dec 27 01:37:24 PM PST 23
Peak memory 224156 kb
Host smart-922b944e-c472-4148-8a84-3895125c75c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971838642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2971838642
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_abort.2989013136
Short name T1098
Test name
Test status
Simulation time 14748084 ps
CPU time 0.74 seconds
Started Dec 27 01:37:18 PM PST 23
Finished Dec 27 01:37:20 PM PST 23
Peak memory 206504 kb
Host smart-5663bbc0-8189-4fd5-99ee-2a7add67cdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989013136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_abort.2989013136
Directory /workspace/43.spi_device_abort/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2442356719
Short name T819
Test name
Test status
Simulation time 98780809 ps
CPU time 0.73 seconds
Started Dec 27 01:38:01 PM PST 23
Finished Dec 27 01:38:03 PM PST 23
Peak memory 206520 kb
Host smart-dc989789-1be8-4648-9a72-154cc3ae7c51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442356719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2442356719
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_bit_transfer.4010081070
Short name T886
Test name
Test status
Simulation time 460525171 ps
CPU time 2.35 seconds
Started Dec 27 01:37:19 PM PST 23
Finished Dec 27 01:37:22 PM PST 23
Peak memory 216716 kb
Host smart-26da4db6-9a87-46df-9c6f-b8619ab428d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010081070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_bit_transfer.4010081070
Directory /workspace/43.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/43.spi_device_byte_transfer.4201027305
Short name T924
Test name
Test status
Simulation time 135744641 ps
CPU time 2.48 seconds
Started Dec 27 01:36:53 PM PST 23
Finished Dec 27 01:36:56 PM PST 23
Peak memory 216888 kb
Host smart-1583bb40-f2a2-4f49-b5f2-25cc7c9fccf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201027305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_byte_transfer.4201027305
Directory /workspace/43.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.4147881124
Short name T1323
Test name
Test status
Simulation time 150536096 ps
CPU time 2.89 seconds
Started Dec 27 01:37:08 PM PST 23
Finished Dec 27 01:37:12 PM PST 23
Peak memory 237968 kb
Host smart-77c00856-7e1c-4d73-a939-a4a7e0978568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147881124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4147881124
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.238850345
Short name T728
Test name
Test status
Simulation time 76806100 ps
CPU time 0.79 seconds
Started Dec 27 01:37:00 PM PST 23
Finished Dec 27 01:37:01 PM PST 23
Peak memory 207624 kb
Host smart-33cbf689-eafc-48e7-8f18-68ea35d894ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238850345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.238850345
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_dummy_item_extra_dly.3355478857
Short name T1167
Test name
Test status
Simulation time 34005820121 ps
CPU time 567.4 seconds
Started Dec 27 01:37:07 PM PST 23
Finished Dec 27 01:46:35 PM PST 23
Peak memory 263460 kb
Host smart-b517b9e7-c258-4a37-abfd-4ef5d5eda4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355478857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_dummy_item_extra_dly.3355478857
Directory /workspace/43.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/43.spi_device_extreme_fifo_size.1949449320
Short name T1119
Test name
Test status
Simulation time 35040707804 ps
CPU time 457.05 seconds
Started Dec 27 01:36:54 PM PST 23
Finished Dec 27 01:44:32 PM PST 23
Peak memory 216964 kb
Host smart-e8b52e46-107e-496a-be72-8579fff31e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949449320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_extreme_fifo_size.1949449320
Directory /workspace/43.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/43.spi_device_fifo_full.213227688
Short name T876
Test name
Test status
Simulation time 31190911383 ps
CPU time 651.09 seconds
Started Dec 27 01:36:57 PM PST 23
Finished Dec 27 01:47:49 PM PST 23
Peak memory 256868 kb
Host smart-a4014bb3-d6bc-4ab8-abd7-69e76b946747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213227688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_fifo_full.213227688
Directory /workspace/43.spi_device_fifo_full/latest

Test location /workspace/coverage/default/43.spi_device_fifo_underflow_overflow.969635252
Short name T546
Test name
Test status
Simulation time 798935810118 ps
CPU time 377.26 seconds
Started Dec 27 01:37:01 PM PST 23
Finished Dec 27 01:43:19 PM PST 23
Peak memory 354556 kb
Host smart-aa90f8aa-93e0-4ad4-af99-1705d6c1c1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969635252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_fifo_underflow_overfl
ow.969635252
Directory /workspace/43.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.4014606439
Short name T243
Test name
Test status
Simulation time 30983690193 ps
CPU time 58.49 seconds
Started Dec 27 01:37:25 PM PST 23
Finished Dec 27 01:38:24 PM PST 23
Peak memory 265800 kb
Host smart-f34c644f-23e3-4c58-b7f9-6bcdf90f86f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014606439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.4014606439
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.810274738
Short name T1472
Test name
Test status
Simulation time 5452587195 ps
CPU time 127.11 seconds
Started Dec 27 01:37:27 PM PST 23
Finished Dec 27 01:39:35 PM PST 23
Peak memory 274316 kb
Host smart-89e24d8d-16e0-4f0e-b296-d23a425dd593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810274738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.810274738
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1115523864
Short name T1149
Test name
Test status
Simulation time 3908227608 ps
CPU time 24.97 seconds
Started Dec 27 01:37:03 PM PST 23
Finished Dec 27 01:37:28 PM PST 23
Peak memory 249624 kb
Host smart-931a356d-f4df-4b94-bb0b-91002bffd630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115523864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1115523864
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.789061476
Short name T1545
Test name
Test status
Simulation time 140124708 ps
CPU time 2.98 seconds
Started Dec 27 01:37:30 PM PST 23
Finished Dec 27 01:37:33 PM PST 23
Peak memory 218240 kb
Host smart-0916cad8-6641-4bd3-8f1b-bec7a235e06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789061476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.789061476
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_intr.12126602
Short name T477
Test name
Test status
Simulation time 31138972842 ps
CPU time 49.72 seconds
Started Dec 27 01:36:50 PM PST 23
Finished Dec 27 01:37:41 PM PST 23
Peak memory 241036 kb
Host smart-56f3b8c7-8697-4e4d-b897-76d92b6fc40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12126602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intr.12126602
Directory /workspace/43.spi_device_intr/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2261079861
Short name T238
Test name
Test status
Simulation time 5098702451 ps
CPU time 10.8 seconds
Started Dec 27 01:37:22 PM PST 23
Finished Dec 27 01:37:33 PM PST 23
Peak memory 225024 kb
Host smart-09146511-2a6d-4180-8a10-520ad368c7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261079861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2261079861
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2683713957
Short name T27
Test name
Test status
Simulation time 1091303805 ps
CPU time 10.08 seconds
Started Dec 27 01:37:22 PM PST 23
Finished Dec 27 01:37:33 PM PST 23
Peak memory 229960 kb
Host smart-c2fc70cf-0c21-42e1-b1a9-f9a0778a2b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683713957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2683713957
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.4094498758
Short name T220
Test name
Test status
Simulation time 4001725172 ps
CPU time 4.49 seconds
Started Dec 27 01:37:27 PM PST 23
Finished Dec 27 01:37:33 PM PST 23
Peak memory 218784 kb
Host smart-b61c3a2c-e5ba-4c52-bb99-eb39b2278471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094498758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.4094498758
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_perf.1713113598
Short name T1197
Test name
Test status
Simulation time 36743762261 ps
CPU time 343.01 seconds
Started Dec 27 01:36:50 PM PST 23
Finished Dec 27 01:42:34 PM PST 23
Peak memory 286000 kb
Host smart-e95e616d-0cd0-4d7a-92bf-b4319c00ec7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713113598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_perf.1713113598
Directory /workspace/43.spi_device_perf/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2728454377
Short name T1380
Test name
Test status
Simulation time 334267583 ps
CPU time 3.51 seconds
Started Dec 27 01:37:22 PM PST 23
Finished Dec 27 01:37:26 PM PST 23
Peak memory 220208 kb
Host smart-eb8536b7-4f12-4d4b-82b3-e381350d9aec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2728454377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2728454377
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_rx_async_fifo_reset.3020746165
Short name T1251
Test name
Test status
Simulation time 588234651 ps
CPU time 0.91 seconds
Started Dec 27 01:37:12 PM PST 23
Finished Dec 27 01:37:14 PM PST 23
Peak memory 208340 kb
Host smart-d45220fa-a64d-486d-b452-5703dd0e3276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020746165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_rx_async_fifo_reset.3020746165
Directory /workspace/43.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/43.spi_device_rx_timeout.710833919
Short name T1695
Test name
Test status
Simulation time 687651927 ps
CPU time 5.96 seconds
Started Dec 27 01:36:52 PM PST 23
Finished Dec 27 01:36:58 PM PST 23
Peak memory 216896 kb
Host smart-179aa1af-82dc-4d00-a795-65859d60bb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710833919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_rx_timeout.710833919
Directory /workspace/43.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/43.spi_device_smoke.1951510808
Short name T1181
Test name
Test status
Simulation time 45905189 ps
CPU time 0.85 seconds
Started Dec 27 01:37:40 PM PST 23
Finished Dec 27 01:37:48 PM PST 23
Peak memory 207772 kb
Host smart-fe7989d6-aec4-43a5-a732-f5ba551cbb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951510808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_smoke.1951510808
Directory /workspace/43.spi_device_smoke/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.887663897
Short name T888
Test name
Test status
Simulation time 6678135628 ps
CPU time 53.24 seconds
Started Dec 27 01:37:18 PM PST 23
Finished Dec 27 01:38:12 PM PST 23
Peak memory 222992 kb
Host smart-8c5c0444-da8b-452f-b482-934eeb820229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887663897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.887663897
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3160014046
Short name T965
Test name
Test status
Simulation time 14456710810 ps
CPU time 12.25 seconds
Started Dec 27 01:37:02 PM PST 23
Finished Dec 27 01:37:15 PM PST 23
Peak memory 217844 kb
Host smart-177659d5-b106-4e91-be0c-b290f88dbcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160014046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3160014046
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1818775762
Short name T127
Test name
Test status
Simulation time 290369337 ps
CPU time 3.49 seconds
Started Dec 27 01:37:22 PM PST 23
Finished Dec 27 01:37:27 PM PST 23
Peak memory 216788 kb
Host smart-bf11870f-63d0-489a-bfc2-707db3f766d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818775762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1818775762
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3327011770
Short name T1274
Test name
Test status
Simulation time 79874003 ps
CPU time 0.8 seconds
Started Dec 27 01:37:20 PM PST 23
Finished Dec 27 01:37:22 PM PST 23
Peak memory 206868 kb
Host smart-edc2baf6-2fe2-4ea2-b65f-ef0edcfd851e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327011770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3327011770
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_tx_async_fifo_reset.2134012405
Short name T1653
Test name
Test status
Simulation time 17887599 ps
CPU time 0.76 seconds
Started Dec 27 01:37:08 PM PST 23
Finished Dec 27 01:37:10 PM PST 23
Peak memory 208468 kb
Host smart-c89cec51-3723-4249-908e-3cc79a7e71a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134012405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tx_async_fifo_reset.2134012405
Directory /workspace/43.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/43.spi_device_txrx.1849942680
Short name T943
Test name
Test status
Simulation time 612874186172 ps
CPU time 1744.15 seconds
Started Dec 27 01:37:25 PM PST 23
Finished Dec 27 02:06:30 PM PST 23
Peak memory 284688 kb
Host smart-47684c42-b672-4041-b372-6d4ce0925424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849942680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_txrx.1849942680
Directory /workspace/43.spi_device_txrx/latest

Test location /workspace/coverage/default/43.spi_device_upload.3535803645
Short name T1413
Test name
Test status
Simulation time 6793867800 ps
CPU time 24.29 seconds
Started Dec 27 01:37:48 PM PST 23
Finished Dec 27 01:38:16 PM PST 23
Peak memory 218940 kb
Host smart-3ec1ba0f-1548-4d1f-a6f0-a12941657abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535803645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3535803645
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_abort.1055920835
Short name T1
Test name
Test status
Simulation time 74513566 ps
CPU time 0.73 seconds
Started Dec 27 01:37:27 PM PST 23
Finished Dec 27 01:37:29 PM PST 23
Peak memory 206644 kb
Host smart-0da169ed-14dc-4ba4-9658-54bbc253ca46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055920835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_abort.1055920835
Directory /workspace/44.spi_device_abort/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1584334889
Short name T1616
Test name
Test status
Simulation time 27838290 ps
CPU time 0.71 seconds
Started Dec 27 01:37:42 PM PST 23
Finished Dec 27 01:37:48 PM PST 23
Peak memory 206444 kb
Host smart-8123cbbb-1b7d-470c-89d9-96ade36cb50b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584334889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1584334889
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_bit_transfer.4032189970
Short name T125
Test name
Test status
Simulation time 199371229 ps
CPU time 2.4 seconds
Started Dec 27 01:37:19 PM PST 23
Finished Dec 27 01:37:23 PM PST 23
Peak memory 216704 kb
Host smart-830b5f94-e355-495a-89cf-157563e41aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032189970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_bit_transfer.4032189970
Directory /workspace/44.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/44.spi_device_byte_transfer.153620787
Short name T1570
Test name
Test status
Simulation time 139233967 ps
CPU time 2.59 seconds
Started Dec 27 01:37:27 PM PST 23
Finished Dec 27 01:37:31 PM PST 23
Peak memory 216852 kb
Host smart-9892b081-275f-4857-a1b2-59f4a83cfa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153620787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_byte_transfer.153620787
Directory /workspace/44.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2424998927
Short name T1164
Test name
Test status
Simulation time 11545734488 ps
CPU time 5.4 seconds
Started Dec 27 01:37:59 PM PST 23
Finished Dec 27 01:38:07 PM PST 23
Peak memory 218416 kb
Host smart-7d049218-0f48-4d51-ac40-3e1906022eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424998927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2424998927
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.4094583110
Short name T1735
Test name
Test status
Simulation time 13740966 ps
CPU time 0.74 seconds
Started Dec 27 01:37:10 PM PST 23
Finished Dec 27 01:37:12 PM PST 23
Peak memory 206608 kb
Host smart-0ddb8272-6ee0-49ba-8a7e-3ae187d8d720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094583110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.4094583110
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_dummy_item_extra_dly.2600566160
Short name T1316
Test name
Test status
Simulation time 96598468134 ps
CPU time 1008.43 seconds
Started Dec 27 01:37:20 PM PST 23
Finished Dec 27 01:54:10 PM PST 23
Peak memory 284984 kb
Host smart-657d4c78-9823-4671-b758-637d60cf4509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600566160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_dummy_item_extra_dly.2600566160
Directory /workspace/44.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/44.spi_device_extreme_fifo_size.3151130907
Short name T1177
Test name
Test status
Simulation time 282897810570 ps
CPU time 934.05 seconds
Started Dec 27 01:37:52 PM PST 23
Finished Dec 27 01:53:30 PM PST 23
Peak memory 219996 kb
Host smart-62fdbcda-3135-4216-a41f-3ee677b8a523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151130907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_extreme_fifo_size.3151130907
Directory /workspace/44.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/44.spi_device_fifo_full.3418373351
Short name T891
Test name
Test status
Simulation time 16398175723 ps
CPU time 290.29 seconds
Started Dec 27 01:37:58 PM PST 23
Finished Dec 27 01:42:52 PM PST 23
Peak memory 272064 kb
Host smart-8a49ce4d-80bb-4a33-85f9-6ab6c0ef91de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418373351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_fifo_full.3418373351
Directory /workspace/44.spi_device_fifo_full/latest

Test location /workspace/coverage/default/44.spi_device_fifo_underflow_overflow.3720557904
Short name T1370
Test name
Test status
Simulation time 44613264963 ps
CPU time 141.92 seconds
Started Dec 27 01:38:00 PM PST 23
Finished Dec 27 01:40:24 PM PST 23
Peak memory 336220 kb
Host smart-1783cf34-051f-4b6a-9e37-3ad822b6df06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720557904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_fifo_underflow_overf
low.3720557904
Directory /workspace/44.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1711114859
Short name T242
Test name
Test status
Simulation time 44194141822 ps
CPU time 214.01 seconds
Started Dec 27 01:37:52 PM PST 23
Finished Dec 27 01:41:30 PM PST 23
Peak memory 249676 kb
Host smart-6dcdce65-18e2-4a5f-849d-50205825739b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711114859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1711114859
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.4065085512
Short name T61
Test name
Test status
Simulation time 27385164123 ps
CPU time 209.97 seconds
Started Dec 27 01:37:58 PM PST 23
Finished Dec 27 01:41:31 PM PST 23
Peak memory 268448 kb
Host smart-d725396f-c9e9-43a7-ad27-d509bdfb1c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065085512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.4065085512
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3092090174
Short name T1116
Test name
Test status
Simulation time 322171581969 ps
CPU time 121.17 seconds
Started Dec 27 01:37:40 PM PST 23
Finished Dec 27 01:39:52 PM PST 23
Peak memory 251200 kb
Host smart-6c138d8c-176f-4ab8-9464-352d05efc728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092090174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3092090174
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3158408038
Short name T1074
Test name
Test status
Simulation time 36785698441 ps
CPU time 40.63 seconds
Started Dec 27 01:37:28 PM PST 23
Finished Dec 27 01:38:09 PM PST 23
Peak memory 257784 kb
Host smart-2df87759-0c0d-42b2-9179-92f9736b1c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158408038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3158408038
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1290391383
Short name T260
Test name
Test status
Simulation time 2481423605 ps
CPU time 7.83 seconds
Started Dec 27 01:37:36 PM PST 23
Finished Dec 27 01:37:51 PM PST 23
Peak memory 220796 kb
Host smart-5a02df6e-8a6a-4978-85bd-60ebd65c15e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290391383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1290391383
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_intr.2887481817
Short name T1290
Test name
Test status
Simulation time 14059371485 ps
CPU time 17.75 seconds
Started Dec 27 01:37:33 PM PST 23
Finished Dec 27 01:37:53 PM PST 23
Peak memory 225052 kb
Host smart-ea231c83-3cfc-47d1-aa27-22f131947ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887481817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intr.2887481817
Directory /workspace/44.spi_device_intr/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.4133574492
Short name T261
Test name
Test status
Simulation time 21881025659 ps
CPU time 24.67 seconds
Started Dec 27 01:37:24 PM PST 23
Finished Dec 27 01:37:49 PM PST 23
Peak memory 247212 kb
Host smart-22aa5191-9f00-49b0-a3b0-68bb99d8307b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133574492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.4133574492
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.627599946
Short name T963
Test name
Test status
Simulation time 115589035493 ps
CPU time 37.12 seconds
Started Dec 27 01:37:23 PM PST 23
Finished Dec 27 01:38:01 PM PST 23
Peak memory 231772 kb
Host smart-93e874c5-6cd4-4ae7-a78f-a7c83df70932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627599946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.627599946
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_perf.3725322094
Short name T585
Test name
Test status
Simulation time 9155182683 ps
CPU time 237.49 seconds
Started Dec 27 01:37:10 PM PST 23
Finished Dec 27 01:41:08 PM PST 23
Peak memory 257572 kb
Host smart-4a7657db-8186-4dc0-93ab-bfe69db566d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725322094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_perf.3725322094
Directory /workspace/44.spi_device_perf/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.695825180
Short name T913
Test name
Test status
Simulation time 1034644388 ps
CPU time 4.5 seconds
Started Dec 27 01:37:52 PM PST 23
Finished Dec 27 01:38:01 PM PST 23
Peak memory 234084 kb
Host smart-00409316-85c3-4dee-ac62-0f66779ed84e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=695825180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.695825180
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_rx_async_fifo_reset.3873920743
Short name T99
Test name
Test status
Simulation time 18341586 ps
CPU time 0.85 seconds
Started Dec 27 01:37:22 PM PST 23
Finished Dec 27 01:37:23 PM PST 23
Peak memory 208340 kb
Host smart-9df8ffab-96fb-4312-b35b-0ef34a2b4ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873920743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_rx_async_fifo_reset.3873920743
Directory /workspace/44.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/44.spi_device_rx_timeout.1400501874
Short name T1049
Test name
Test status
Simulation time 509369879 ps
CPU time 5.23 seconds
Started Dec 27 01:37:20 PM PST 23
Finished Dec 27 01:37:26 PM PST 23
Peak memory 216760 kb
Host smart-fe60d622-db6c-4a03-8ff4-2913e7d77800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400501874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_rx_timeout.1400501874
Directory /workspace/44.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/44.spi_device_smoke.2433672525
Short name T1269
Test name
Test status
Simulation time 20990200 ps
CPU time 1.01 seconds
Started Dec 27 01:37:37 PM PST 23
Finished Dec 27 01:37:45 PM PST 23
Peak memory 207992 kb
Host smart-c5531270-1146-4f83-a53e-548586e3cce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433672525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_smoke.2433672525
Directory /workspace/44.spi_device_smoke/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.506685489
Short name T972
Test name
Test status
Simulation time 2447885428 ps
CPU time 38.71 seconds
Started Dec 27 01:37:19 PM PST 23
Finished Dec 27 01:37:59 PM PST 23
Peak memory 218288 kb
Host smart-0f03bacd-8b3f-4a2d-a3ba-98a80960b8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506685489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.506685489
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1873230038
Short name T1415
Test name
Test status
Simulation time 342015227 ps
CPU time 1.74 seconds
Started Dec 27 01:37:37 PM PST 23
Finished Dec 27 01:37:46 PM PST 23
Peak memory 208016 kb
Host smart-9816971f-c5b1-44cf-b321-7277e8090c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873230038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1873230038
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2094436654
Short name T589
Test name
Test status
Simulation time 93947523 ps
CPU time 4.85 seconds
Started Dec 27 01:37:25 PM PST 23
Finished Dec 27 01:37:30 PM PST 23
Peak memory 216844 kb
Host smart-2802f3dc-7fb7-4680-8a51-f75a4f679b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094436654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2094436654
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2376502048
Short name T537
Test name
Test status
Simulation time 237833554 ps
CPU time 1.04 seconds
Started Dec 27 01:37:26 PM PST 23
Finished Dec 27 01:37:29 PM PST 23
Peak memory 208008 kb
Host smart-f243ad7c-66c6-427b-8549-3a1931ba5aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376502048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2376502048
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_tx_async_fifo_reset.926036902
Short name T818
Test name
Test status
Simulation time 29055343 ps
CPU time 0.76 seconds
Started Dec 27 01:37:25 PM PST 23
Finished Dec 27 01:37:26 PM PST 23
Peak memory 208448 kb
Host smart-34fb4b32-4388-4883-b165-51338da72b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926036902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tx_async_fifo_reset.926036902
Directory /workspace/44.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/44.spi_device_txrx.3081751432
Short name T828
Test name
Test status
Simulation time 205142754925 ps
CPU time 358.76 seconds
Started Dec 27 01:37:20 PM PST 23
Finished Dec 27 01:43:20 PM PST 23
Peak memory 284476 kb
Host smart-9b80c689-f98b-4e7c-8cb7-ddda49cc4057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081751432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_txrx.3081751432
Directory /workspace/44.spi_device_txrx/latest

Test location /workspace/coverage/default/44.spi_device_upload.2156302492
Short name T816
Test name
Test status
Simulation time 10386670210 ps
CPU time 16.33 seconds
Started Dec 27 01:37:21 PM PST 23
Finished Dec 27 01:37:38 PM PST 23
Peak memory 229640 kb
Host smart-350682be-9aa3-456d-b8e8-8c6becbea5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156302492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2156302492
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_abort.319559892
Short name T1247
Test name
Test status
Simulation time 24240064 ps
CPU time 0.75 seconds
Started Dec 27 01:39:20 PM PST 23
Finished Dec 27 01:39:21 PM PST 23
Peak memory 206524 kb
Host smart-8ce2c409-67b4-4a7a-9a65-bd99ecadcc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319559892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_abort.319559892
Directory /workspace/45.spi_device_abort/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1880372475
Short name T1506
Test name
Test status
Simulation time 25480472 ps
CPU time 0.73 seconds
Started Dec 27 01:37:38 PM PST 23
Finished Dec 27 01:37:45 PM PST 23
Peak memory 206500 kb
Host smart-3649f403-a5dc-4e05-95d0-7b19906c818e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880372475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1880372475
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_bit_transfer.4192994711
Short name T562
Test name
Test status
Simulation time 194646740 ps
CPU time 2.31 seconds
Started Dec 27 01:39:39 PM PST 23
Finished Dec 27 01:39:42 PM PST 23
Peak memory 216648 kb
Host smart-d95302a1-4b1f-4800-bf79-60d56911ffbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192994711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_bit_transfer.4192994711
Directory /workspace/45.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/45.spi_device_byte_transfer.3681906898
Short name T711
Test name
Test status
Simulation time 541700638 ps
CPU time 2.6 seconds
Started Dec 27 01:37:55 PM PST 23
Finished Dec 27 01:38:01 PM PST 23
Peak memory 216868 kb
Host smart-7db06432-9a1a-4164-aa4d-61e5ec93e85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681906898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_byte_transfer.3681906898
Directory /workspace/45.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1117037583
Short name T295
Test name
Test status
Simulation time 174208347 ps
CPU time 2.48 seconds
Started Dec 27 01:37:57 PM PST 23
Finished Dec 27 01:38:02 PM PST 23
Peak memory 218120 kb
Host smart-e54a543c-dd85-4b96-a49e-e95c328f70de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117037583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1117037583
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2388810108
Short name T722
Test name
Test status
Simulation time 69349486 ps
CPU time 0.82 seconds
Started Dec 27 01:37:59 PM PST 23
Finished Dec 27 01:38:03 PM PST 23
Peak memory 207448 kb
Host smart-e36137c5-e554-4998-acf4-3e143fa5020c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388810108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2388810108
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_dummy_item_extra_dly.2799788085
Short name T861
Test name
Test status
Simulation time 84121746051 ps
CPU time 184 seconds
Started Dec 27 01:37:47 PM PST 23
Finished Dec 27 01:40:56 PM PST 23
Peak memory 282524 kb
Host smart-bc362be5-b9fe-4feb-ac29-cdc064bd459b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799788085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_dummy_item_extra_dly.2799788085
Directory /workspace/45.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/45.spi_device_extreme_fifo_size.2302514169
Short name T1721
Test name
Test status
Simulation time 55513257502 ps
CPU time 616.07 seconds
Started Dec 27 01:37:41 PM PST 23
Finished Dec 27 01:48:00 PM PST 23
Peak memory 218976 kb
Host smart-35581e9b-0c04-499d-b869-99b8466a43a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302514169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_extreme_fifo_size.2302514169
Directory /workspace/45.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/45.spi_device_fifo_full.4222218642
Short name T1124
Test name
Test status
Simulation time 56204626116 ps
CPU time 833.01 seconds
Started Dec 27 01:37:44 PM PST 23
Finished Dec 27 01:51:45 PM PST 23
Peak memory 309128 kb
Host smart-7092234f-dc4b-43d8-ac79-39d0c6b240cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222218642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_fifo_full.4222218642
Directory /workspace/45.spi_device_fifo_full/latest

Test location /workspace/coverage/default/45.spi_device_fifo_underflow_overflow.2539114028
Short name T68
Test name
Test status
Simulation time 17726049950 ps
CPU time 196.79 seconds
Started Dec 27 01:37:45 PM PST 23
Finished Dec 27 01:41:09 PM PST 23
Peak memory 363416 kb
Host smart-cd76705b-b847-4b10-b50c-7ee6a07d7f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539114028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_fifo_underflow_overf
low.2539114028
Directory /workspace/45.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1901037464
Short name T1428
Test name
Test status
Simulation time 25409325115 ps
CPU time 105.03 seconds
Started Dec 27 01:38:26 PM PST 23
Finished Dec 27 01:40:13 PM PST 23
Peak memory 241604 kb
Host smart-7074737c-9ea1-4470-a675-d6604211e141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901037464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1901037464
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2546841990
Short name T615
Test name
Test status
Simulation time 1179403300 ps
CPU time 18.9 seconds
Started Dec 27 01:37:56 PM PST 23
Finished Dec 27 01:38:18 PM PST 23
Peak memory 253912 kb
Host smart-3127a727-89af-48ff-8455-452f05de2ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546841990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2546841990
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1243242107
Short name T230
Test name
Test status
Simulation time 1325306216 ps
CPU time 4.39 seconds
Started Dec 27 01:37:57 PM PST 23
Finished Dec 27 01:38:04 PM PST 23
Peak memory 221132 kb
Host smart-9b0051f1-87ca-4140-9471-d9b30dc8e3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243242107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1243242107
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_intr.1728566258
Short name T1704
Test name
Test status
Simulation time 25469235098 ps
CPU time 73.73 seconds
Started Dec 27 01:38:04 PM PST 23
Finished Dec 27 01:39:19 PM PST 23
Peak memory 240352 kb
Host smart-ff0ba8ea-b472-486f-85fe-ecff2612ae6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728566258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intr.1728566258
Directory /workspace/45.spi_device_intr/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3794752999
Short name T1352
Test name
Test status
Simulation time 8972068126 ps
CPU time 6.91 seconds
Started Dec 27 01:37:50 PM PST 23
Finished Dec 27 01:38:00 PM PST 23
Peak memory 236120 kb
Host smart-fb04ee5a-6ccd-49ad-900d-cca2c5ed491a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794752999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3794752999
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.866784935
Short name T319
Test name
Test status
Simulation time 1220818825 ps
CPU time 4.38 seconds
Started Dec 27 01:37:51 PM PST 23
Finished Dec 27 01:38:00 PM PST 23
Peak memory 218820 kb
Host smart-cf19c8e8-9bec-4a58-a315-6fd68ff02673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866784935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.866784935
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_perf.549164809
Short name T490
Test name
Test status
Simulation time 43172896054 ps
CPU time 1739.87 seconds
Started Dec 27 01:38:04 PM PST 23
Finished Dec 27 02:07:04 PM PST 23
Peak memory 257668 kb
Host smart-85421599-76b4-40eb-b1b4-ea6e3c8ed1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549164809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_perf.549164809
Directory /workspace/45.spi_device_perf/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3843758474
Short name T191
Test name
Test status
Simulation time 118371343 ps
CPU time 3.3 seconds
Started Dec 27 01:37:57 PM PST 23
Finished Dec 27 01:38:04 PM PST 23
Peak memory 219988 kb
Host smart-b1cd4202-6748-4412-9352-85f20946448c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3843758474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3843758474
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_rx_async_fifo_reset.2688203859
Short name T1190
Test name
Test status
Simulation time 19153656 ps
CPU time 0.93 seconds
Started Dec 27 01:38:57 PM PST 23
Finished Dec 27 01:38:59 PM PST 23
Peak memory 207456 kb
Host smart-dfd972f1-b7de-408a-9edf-022503b327b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688203859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_rx_async_fifo_reset.2688203859
Directory /workspace/45.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/45.spi_device_rx_timeout.4156514463
Short name T672
Test name
Test status
Simulation time 985227083 ps
CPU time 7 seconds
Started Dec 27 01:37:57 PM PST 23
Finished Dec 27 01:38:08 PM PST 23
Peak memory 216832 kb
Host smart-63feb8a4-bed9-4f7a-bc1f-c5422d5c3a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156514463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_rx_timeout.4156514463
Directory /workspace/45.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/45.spi_device_smoke.301326903
Short name T944
Test name
Test status
Simulation time 198616077 ps
CPU time 1.1 seconds
Started Dec 27 01:37:50 PM PST 23
Finished Dec 27 01:37:54 PM PST 23
Peak memory 216524 kb
Host smart-bdcd5b76-c182-471e-b75a-a7fa3a21fe0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301326903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_smoke.301326903
Directory /workspace/45.spi_device_smoke/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.4291510997
Short name T160
Test name
Test status
Simulation time 1661277729359 ps
CPU time 4235.71 seconds
Started Dec 27 01:37:47 PM PST 23
Finished Dec 27 02:48:28 PM PST 23
Peak memory 274368 kb
Host smart-644cd695-103a-46e6-9b77-c75166e055df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291510997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.4291510997
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1199137058
Short name T124
Test name
Test status
Simulation time 780223044 ps
CPU time 5.07 seconds
Started Dec 27 01:37:56 PM PST 23
Finished Dec 27 01:38:04 PM PST 23
Peak memory 220216 kb
Host smart-a7293975-3f67-4e58-9b0a-edca4f6756d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199137058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1199137058
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.950391665
Short name T738
Test name
Test status
Simulation time 8707709033 ps
CPU time 6.4 seconds
Started Dec 27 01:37:42 PM PST 23
Finished Dec 27 01:37:55 PM PST 23
Peak memory 216836 kb
Host smart-dffdce2d-fed7-4942-87ca-6f1c0e22f956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950391665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.950391665
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.378506467
Short name T573
Test name
Test status
Simulation time 61876016 ps
CPU time 1.58 seconds
Started Dec 27 01:37:50 PM PST 23
Finished Dec 27 01:37:54 PM PST 23
Peak memory 216776 kb
Host smart-07d5024a-63f0-4e86-8a40-fcf3b42dd469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378506467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.378506467
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1223218213
Short name T723
Test name
Test status
Simulation time 119832764 ps
CPU time 1.01 seconds
Started Dec 27 01:37:58 PM PST 23
Finished Dec 27 01:38:02 PM PST 23
Peak memory 206900 kb
Host smart-d2d707d8-2f51-4e30-a965-d0f72304bcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223218213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1223218213
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_tx_async_fifo_reset.195950507
Short name T1334
Test name
Test status
Simulation time 87367872 ps
CPU time 0.73 seconds
Started Dec 27 01:39:23 PM PST 23
Finished Dec 27 01:39:25 PM PST 23
Peak memory 208344 kb
Host smart-b01a90a9-e1e0-4e16-a66d-60bce9eb3c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195950507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tx_async_fifo_reset.195950507
Directory /workspace/45.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/45.spi_device_txrx.2551009056
Short name T1070
Test name
Test status
Simulation time 173366392106 ps
CPU time 938.85 seconds
Started Dec 27 01:37:53 PM PST 23
Finished Dec 27 01:53:36 PM PST 23
Peak memory 274892 kb
Host smart-732131a4-92cd-4e12-89b7-f840f72add14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551009056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_txrx.2551009056
Directory /workspace/45.spi_device_txrx/latest

Test location /workspace/coverage/default/45.spi_device_upload.3122496514
Short name T987
Test name
Test status
Simulation time 2708845628 ps
CPU time 5.9 seconds
Started Dec 27 01:37:55 PM PST 23
Finished Dec 27 01:38:04 PM PST 23
Peak memory 239512 kb
Host smart-ea31ef5a-6a6c-4025-81a7-5283ca88ae02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122496514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3122496514
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_abort.3413695792
Short name T1686
Test name
Test status
Simulation time 13291656 ps
CPU time 0.75 seconds
Started Dec 27 01:37:56 PM PST 23
Finished Dec 27 01:37:59 PM PST 23
Peak memory 206588 kb
Host smart-7e315758-9b1b-481e-9028-ecf1e6606544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413695792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_abort.3413695792
Directory /workspace/46.spi_device_abort/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2496822906
Short name T956
Test name
Test status
Simulation time 15322588 ps
CPU time 0.74 seconds
Started Dec 27 01:38:01 PM PST 23
Finished Dec 27 01:38:03 PM PST 23
Peak memory 206508 kb
Host smart-69e60425-dfa5-4a2d-b682-601e3a106b6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496822906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2496822906
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_bit_transfer.1886462226
Short name T1252
Test name
Test status
Simulation time 730865615 ps
CPU time 2.44 seconds
Started Dec 27 01:37:54 PM PST 23
Finished Dec 27 01:38:00 PM PST 23
Peak memory 216776 kb
Host smart-0f87aa4b-f723-4ae8-9cfa-8ede7709982d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886462226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_bit_transfer.1886462226
Directory /workspace/46.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/46.spi_device_byte_transfer.1920911456
Short name T489
Test name
Test status
Simulation time 321868566 ps
CPU time 3.45 seconds
Started Dec 27 01:37:53 PM PST 23
Finished Dec 27 01:38:00 PM PST 23
Peak memory 216872 kb
Host smart-7324d495-4b72-47db-ab87-f904261567e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920911456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_byte_transfer.1920911456
Directory /workspace/46.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4185340138
Short name T303
Test name
Test status
Simulation time 300229210 ps
CPU time 4.38 seconds
Started Dec 27 01:37:51 PM PST 23
Finished Dec 27 01:38:00 PM PST 23
Peak memory 224980 kb
Host smart-04fc12c2-6c47-4d14-9d8d-435f54455581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185340138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4185340138
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3032283418
Short name T512
Test name
Test status
Simulation time 29768754 ps
CPU time 0.75 seconds
Started Dec 27 01:37:51 PM PST 23
Finished Dec 27 01:37:56 PM PST 23
Peak memory 206604 kb
Host smart-d3e7c9bb-4481-4320-aaf3-edcc5bc84d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032283418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3032283418
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_dummy_item_extra_dly.4057552197
Short name T280
Test name
Test status
Simulation time 125107243508 ps
CPU time 496.79 seconds
Started Dec 27 01:37:57 PM PST 23
Finished Dec 27 01:46:17 PM PST 23
Peak memory 249676 kb
Host smart-f458e581-194c-44de-9068-15d0b5d323b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057552197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_dummy_item_extra_dly.4057552197
Directory /workspace/46.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/46.spi_device_extreme_fifo_size.3312857941
Short name T1086
Test name
Test status
Simulation time 70720707712 ps
CPU time 2888.55 seconds
Started Dec 27 01:39:15 PM PST 23
Finished Dec 27 02:27:25 PM PST 23
Peak memory 218860 kb
Host smart-c72ea842-507a-453b-8062-442993970e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312857941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_extreme_fifo_size.3312857941
Directory /workspace/46.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/46.spi_device_fifo_full.3827858853
Short name T802
Test name
Test status
Simulation time 82472001183 ps
CPU time 844.5 seconds
Started Dec 27 01:37:54 PM PST 23
Finished Dec 27 01:52:02 PM PST 23
Peak memory 262140 kb
Host smart-66d366d0-fc2b-4e14-be79-5031fe15e537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827858853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_fifo_full.3827858853
Directory /workspace/46.spi_device_fifo_full/latest

Test location /workspace/coverage/default/46.spi_device_fifo_underflow_overflow.2982293883
Short name T1039
Test name
Test status
Simulation time 16393622282 ps
CPU time 268.94 seconds
Started Dec 27 01:39:02 PM PST 23
Finished Dec 27 01:43:33 PM PST 23
Peak memory 347648 kb
Host smart-575d3a56-1ad6-4c29-9024-22d08f0b68d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982293883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_fifo_underflow_overf
low.2982293883
Directory /workspace/46.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.322696109
Short name T1547
Test name
Test status
Simulation time 16719882841 ps
CPU time 110.04 seconds
Started Dec 27 01:37:46 PM PST 23
Finished Dec 27 01:39:42 PM PST 23
Peak memory 266580 kb
Host smart-bc045f9e-50ba-48d8-8ed5-ed21980c8e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322696109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.322696109
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3441926948
Short name T1091
Test name
Test status
Simulation time 2873240196 ps
CPU time 26.28 seconds
Started Dec 27 01:37:58 PM PST 23
Finished Dec 27 01:38:28 PM PST 23
Peak memory 249820 kb
Host smart-bc2542e3-9029-4e45-8c5e-0145280815e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441926948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3441926948
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2023443934
Short name T1563
Test name
Test status
Simulation time 7419217155 ps
CPU time 97.28 seconds
Started Dec 27 01:37:58 PM PST 23
Finished Dec 27 01:39:38 PM PST 23
Peak memory 255268 kb
Host smart-6e6566ab-1937-47b1-b0ce-c3b0e311286d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023443934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2023443934
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3027189171
Short name T1533
Test name
Test status
Simulation time 1026185805 ps
CPU time 15.86 seconds
Started Dec 27 01:37:44 PM PST 23
Finished Dec 27 01:38:07 PM PST 23
Peak memory 247716 kb
Host smart-5ed88eb5-15fa-4361-8c61-a928e90b2d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027189171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3027189171
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2053687439
Short name T673
Test name
Test status
Simulation time 864003877 ps
CPU time 3.92 seconds
Started Dec 27 01:39:20 PM PST 23
Finished Dec 27 01:39:24 PM PST 23
Peak memory 241276 kb
Host smart-6efbcc58-ee97-4473-95ad-fe8866198e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053687439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2053687439
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_intr.2127122991
Short name T54
Test name
Test status
Simulation time 85832764426 ps
CPU time 59.32 seconds
Started Dec 27 01:37:58 PM PST 23
Finished Dec 27 01:39:00 PM PST 23
Peak memory 231404 kb
Host smart-b5059b6e-4d31-4007-b568-c57213a11ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127122991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intr.2127122991
Directory /workspace/46.spi_device_intr/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.485998321
Short name T309
Test name
Test status
Simulation time 15326091619 ps
CPU time 13.04 seconds
Started Dec 27 01:37:53 PM PST 23
Finished Dec 27 01:38:10 PM PST 23
Peak memory 222844 kb
Host smart-7da7bea4-75cb-46a2-859b-bced938bc4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485998321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.485998321
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1165056739
Short name T1208
Test name
Test status
Simulation time 25259271829 ps
CPU time 11.13 seconds
Started Dec 27 01:37:50 PM PST 23
Finished Dec 27 01:38:04 PM PST 23
Peak memory 247000 kb
Host smart-4570a7c5-6867-4c30-8993-437322dc4677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165056739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1165056739
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2493278924
Short name T215
Test name
Test status
Simulation time 285104854 ps
CPU time 4.93 seconds
Started Dec 27 01:37:38 PM PST 23
Finished Dec 27 01:37:49 PM PST 23
Peak memory 219212 kb
Host smart-19994c56-793f-41f3-8c6d-2084a8d3334d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493278924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2493278924
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_perf.1022418353
Short name T1716
Test name
Test status
Simulation time 86741634469 ps
CPU time 2607.65 seconds
Started Dec 27 01:37:56 PM PST 23
Finished Dec 27 02:21:27 PM PST 23
Peak memory 266188 kb
Host smart-f49d70c9-d9bb-4ac3-8e7c-5766abad7b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022418353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_perf.1022418353
Directory /workspace/46.spi_device_perf/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.4129232756
Short name T1343
Test name
Test status
Simulation time 7628280709 ps
CPU time 5.13 seconds
Started Dec 27 01:37:45 PM PST 23
Finished Dec 27 01:37:57 PM PST 23
Peak memory 235980 kb
Host smart-2c958ce1-ed1f-433e-93ca-eda157ef9b47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4129232756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.4129232756
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_rx_async_fifo_reset.1687433766
Short name T1519
Test name
Test status
Simulation time 21102426 ps
CPU time 0.88 seconds
Started Dec 27 01:38:25 PM PST 23
Finished Dec 27 01:38:26 PM PST 23
Peak memory 208496 kb
Host smart-d2c60478-b662-4135-8851-5b7095333a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687433766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_rx_async_fifo_reset.1687433766
Directory /workspace/46.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/46.spi_device_rx_timeout.2299995684
Short name T1292
Test name
Test status
Simulation time 577814432 ps
CPU time 4.97 seconds
Started Dec 27 01:37:50 PM PST 23
Finished Dec 27 01:37:58 PM PST 23
Peak memory 216824 kb
Host smart-c0be1633-6da5-49c5-9e73-c29c8c83485c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299995684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_rx_timeout.2299995684
Directory /workspace/46.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/46.spi_device_smoke.651304227
Short name T926
Test name
Test status
Simulation time 82825063 ps
CPU time 1.15 seconds
Started Dec 27 01:39:18 PM PST 23
Finished Dec 27 01:39:20 PM PST 23
Peak memory 216368 kb
Host smart-b20259de-2c74-4832-9606-a9d35f14956a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651304227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_smoke.651304227
Directory /workspace/46.spi_device_smoke/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2503117949
Short name T156
Test name
Test status
Simulation time 173097671609 ps
CPU time 3013.95 seconds
Started Dec 27 01:37:42 PM PST 23
Finished Dec 27 02:28:03 PM PST 23
Peak memory 389344 kb
Host smart-604605be-b106-416e-9dd3-3efd2ae16fed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503117949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2503117949
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2517428808
Short name T1246
Test name
Test status
Simulation time 7410673694 ps
CPU time 41.37 seconds
Started Dec 27 01:37:58 PM PST 23
Finished Dec 27 01:38:43 PM PST 23
Peak memory 217024 kb
Host smart-bd4a2bd4-2a24-4e68-b17f-7d7ad5d5dbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517428808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2517428808
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2403433758
Short name T1010
Test name
Test status
Simulation time 1304115010 ps
CPU time 4.9 seconds
Started Dec 27 01:37:55 PM PST 23
Finished Dec 27 01:38:03 PM PST 23
Peak memory 216852 kb
Host smart-b5b25143-e9da-41b2-ab85-081b05a3de5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403433758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2403433758
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.4092604274
Short name T1284
Test name
Test status
Simulation time 16309071 ps
CPU time 0.76 seconds
Started Dec 27 01:37:52 PM PST 23
Finished Dec 27 01:37:57 PM PST 23
Peak memory 206880 kb
Host smart-5e8b7fb6-bffa-4aed-a0c8-7c52e4e6d158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092604274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4092604274
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.793046581
Short name T1682
Test name
Test status
Simulation time 47145507 ps
CPU time 0.73 seconds
Started Dec 27 01:38:30 PM PST 23
Finished Dec 27 01:38:33 PM PST 23
Peak memory 206956 kb
Host smart-880a00c3-6d04-4f11-8bf8-af44dd6696eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793046581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.793046581
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_tx_async_fifo_reset.1015237511
Short name T1089
Test name
Test status
Simulation time 56660290 ps
CPU time 0.75 seconds
Started Dec 27 01:37:57 PM PST 23
Finished Dec 27 01:38:01 PM PST 23
Peak memory 208508 kb
Host smart-583c7126-5705-4d61-81f3-1596cfb1a136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015237511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tx_async_fifo_reset.1015237511
Directory /workspace/46.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/46.spi_device_txrx.179778564
Short name T1463
Test name
Test status
Simulation time 45198288294 ps
CPU time 322.59 seconds
Started Dec 27 01:37:40 PM PST 23
Finished Dec 27 01:43:10 PM PST 23
Peak memory 319336 kb
Host smart-b52c48fb-91e5-4a4b-9609-36dcf2e9abd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179778564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_txrx.179778564
Directory /workspace/46.spi_device_txrx/latest

Test location /workspace/coverage/default/46.spi_device_upload.3231674454
Short name T241
Test name
Test status
Simulation time 6484043247 ps
CPU time 27.29 seconds
Started Dec 27 01:37:55 PM PST 23
Finished Dec 27 01:38:25 PM PST 23
Peak memory 231512 kb
Host smart-b3728b83-4c97-4378-9635-2a4aad3d16d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231674454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3231674454
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_abort.3885807306
Short name T1501
Test name
Test status
Simulation time 54526537 ps
CPU time 0.74 seconds
Started Dec 27 01:37:38 PM PST 23
Finished Dec 27 01:37:45 PM PST 23
Peak memory 206616 kb
Host smart-a7fb69bd-0d71-4236-86ad-bb8a75554a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885807306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_abort.3885807306
Directory /workspace/47.spi_device_abort/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3365192831
Short name T1079
Test name
Test status
Simulation time 18675936 ps
CPU time 0.71 seconds
Started Dec 27 01:37:49 PM PST 23
Finished Dec 27 01:37:53 PM PST 23
Peak memory 206488 kb
Host smart-a5707c89-d199-43d5-b58d-3285741331f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365192831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3365192831
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_bit_transfer.2434295987
Short name T1216
Test name
Test status
Simulation time 805490365 ps
CPU time 2.32 seconds
Started Dec 27 01:37:59 PM PST 23
Finished Dec 27 01:38:04 PM PST 23
Peak memory 216736 kb
Host smart-82303f75-3856-426f-90ef-6c69a0a15757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434295987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_bit_transfer.2434295987
Directory /workspace/47.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/47.spi_device_byte_transfer.1108128569
Short name T550
Test name
Test status
Simulation time 70794879 ps
CPU time 2.55 seconds
Started Dec 27 01:37:57 PM PST 23
Finished Dec 27 01:38:03 PM PST 23
Peak memory 216696 kb
Host smart-b4b567e5-685f-45c8-a907-1682696f2614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108128569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_byte_transfer.1108128569
Directory /workspace/47.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3513020913
Short name T995
Test name
Test status
Simulation time 627733216 ps
CPU time 3.93 seconds
Started Dec 27 01:37:55 PM PST 23
Finished Dec 27 01:38:02 PM PST 23
Peak memory 220220 kb
Host smart-6e8f8d8a-177b-40a9-b651-4695cbaf7522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513020913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3513020913
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3152218732
Short name T1077
Test name
Test status
Simulation time 20114564 ps
CPU time 0.79 seconds
Started Dec 27 01:38:01 PM PST 23
Finished Dec 27 01:38:03 PM PST 23
Peak memory 207552 kb
Host smart-d9cf5d04-5d13-4bca-881f-9c8fb9f6eeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152218732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3152218732
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_dummy_item_extra_dly.3514805278
Short name T742
Test name
Test status
Simulation time 95539335219 ps
CPU time 158.21 seconds
Started Dec 27 01:39:20 PM PST 23
Finished Dec 27 01:41:59 PM PST 23
Peak memory 271984 kb
Host smart-743e1c21-9cb9-48f6-8275-c8dbc28c37d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514805278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_dummy_item_extra_dly.3514805278
Directory /workspace/47.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/47.spi_device_fifo_full.4231565764
Short name T715
Test name
Test status
Simulation time 64760550564 ps
CPU time 356.22 seconds
Started Dec 27 01:37:45 PM PST 23
Finished Dec 27 01:43:48 PM PST 23
Peak memory 289932 kb
Host smart-8713028d-0c74-4402-8dd6-e4dbebb7025a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231565764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_fifo_full.4231565764
Directory /workspace/47.spi_device_fifo_full/latest

Test location /workspace/coverage/default/47.spi_device_fifo_underflow_overflow.3828047101
Short name T1403
Test name
Test status
Simulation time 233348292968 ps
CPU time 636.97 seconds
Started Dec 27 01:37:57 PM PST 23
Finished Dec 27 01:48:37 PM PST 23
Peak memory 460596 kb
Host smart-423500ba-8275-4fcb-8831-86055ab930f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828047101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_fifo_underflow_overf
low.3828047101
Directory /workspace/47.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.201422738
Short name T245
Test name
Test status
Simulation time 104692542220 ps
CPU time 298.84 seconds
Started Dec 27 01:37:51 PM PST 23
Finished Dec 27 01:42:54 PM PST 23
Peak memory 270424 kb
Host smart-b30f8ba1-8e7b-4fd4-92dc-e191654bb44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201422738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.201422738
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1188690905
Short name T62
Test name
Test status
Simulation time 4862339458 ps
CPU time 44.74 seconds
Started Dec 27 01:37:51 PM PST 23
Finished Dec 27 01:38:38 PM PST 23
Peak memory 224068 kb
Host smart-b4674151-b447-4215-8067-7dc269457b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188690905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1188690905
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2795193452
Short name T942
Test name
Test status
Simulation time 22886375175 ps
CPU time 17.49 seconds
Started Dec 27 01:37:55 PM PST 23
Finished Dec 27 01:38:15 PM PST 23
Peak memory 238224 kb
Host smart-841db30f-e235-4c4a-82bf-b11466535cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795193452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2795193452
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intr.3590717134
Short name T968
Test name
Test status
Simulation time 21392898391 ps
CPU time 22.33 seconds
Started Dec 27 01:39:20 PM PST 23
Finished Dec 27 01:39:43 PM PST 23
Peak memory 219892 kb
Host smart-26b48e91-9f9c-4602-babb-58cd7c6035b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590717134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intr.3590717134
Directory /workspace/47.spi_device_intr/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1924638642
Short name T1032
Test name
Test status
Simulation time 3697340693 ps
CPU time 9.6 seconds
Started Dec 27 01:37:51 PM PST 23
Finished Dec 27 01:38:05 PM PST 23
Peak memory 219376 kb
Host smart-f4750183-d6c5-42c0-a396-efd3d819c03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924638642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1924638642
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2650344799
Short name T12
Test name
Test status
Simulation time 2386038476 ps
CPU time 5.8 seconds
Started Dec 27 01:37:40 PM PST 23
Finished Dec 27 01:37:53 PM PST 23
Peak memory 219048 kb
Host smart-e7c61e61-9d1c-4a58-b416-446e44e56658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650344799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2650344799
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3235358947
Short name T252
Test name
Test status
Simulation time 13078020151 ps
CPU time 30.15 seconds
Started Dec 27 01:37:50 PM PST 23
Finished Dec 27 01:38:23 PM PST 23
Peak memory 249560 kb
Host smart-e637dab7-69d6-4ebf-ab30-b208db0cd1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235358947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3235358947
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_perf.2344885087
Short name T279
Test name
Test status
Simulation time 113849969139 ps
CPU time 1692.69 seconds
Started Dec 27 01:38:01 PM PST 23
Finished Dec 27 02:06:15 PM PST 23
Peak memory 271488 kb
Host smart-5c6838e8-6844-4d4b-93de-04a1f37b678a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344885087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_perf.2344885087
Directory /workspace/47.spi_device_perf/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3803555437
Short name T545
Test name
Test status
Simulation time 321115159 ps
CPU time 4.19 seconds
Started Dec 27 01:37:52 PM PST 23
Finished Dec 27 01:38:01 PM PST 23
Peak memory 234324 kb
Host smart-63d9cf85-e255-422a-a64a-1cfb2d9ee49c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3803555437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3803555437
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_rx_async_fifo_reset.3759997448
Short name T1608
Test name
Test status
Simulation time 84310139 ps
CPU time 0.83 seconds
Started Dec 27 01:37:53 PM PST 23
Finished Dec 27 01:37:58 PM PST 23
Peak memory 208424 kb
Host smart-0043f1b3-ad76-4a52-ad36-41740d8c63a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759997448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_rx_async_fifo_reset.3759997448
Directory /workspace/47.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/47.spi_device_rx_timeout.1535801683
Short name T1530
Test name
Test status
Simulation time 6262807525 ps
CPU time 5.41 seconds
Started Dec 27 01:37:52 PM PST 23
Finished Dec 27 01:38:02 PM PST 23
Peak memory 216936 kb
Host smart-8a0473eb-ba5d-4aab-93e6-88cfc341ae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535801683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_rx_timeout.1535801683
Directory /workspace/47.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/47.spi_device_smoke.2374135179
Short name T603
Test name
Test status
Simulation time 52671013 ps
CPU time 1.18 seconds
Started Dec 27 01:37:50 PM PST 23
Finished Dec 27 01:37:54 PM PST 23
Peak memory 216544 kb
Host smart-03244075-b715-40ec-ad17-296f15fc1fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374135179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_smoke.2374135179
Directory /workspace/47.spi_device_smoke/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3874170060
Short name T76
Test name
Test status
Simulation time 350424514312 ps
CPU time 1268.09 seconds
Started Dec 27 01:37:47 PM PST 23
Finished Dec 27 01:59:00 PM PST 23
Peak memory 384680 kb
Host smart-c683b07e-59c7-4b48-854d-2336d3735c57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874170060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3874170060
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.4225378231
Short name T1113
Test name
Test status
Simulation time 3437713057 ps
CPU time 32.14 seconds
Started Dec 27 01:37:49 PM PST 23
Finished Dec 27 01:38:25 PM PST 23
Peak memory 217044 kb
Host smart-b67d99ca-15d4-4827-a40f-6f3494edb337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225378231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4225378231
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.424742895
Short name T636
Test name
Test status
Simulation time 15145155179 ps
CPU time 12.91 seconds
Started Dec 27 01:37:54 PM PST 23
Finished Dec 27 01:38:10 PM PST 23
Peak memory 216856 kb
Host smart-01af4677-2913-4ea1-a9c9-a81e60f14846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424742895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.424742895
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.779826873
Short name T1265
Test name
Test status
Simulation time 144682739 ps
CPU time 2.98 seconds
Started Dec 27 01:39:15 PM PST 23
Finished Dec 27 01:39:19 PM PST 23
Peak memory 215136 kb
Host smart-70cd190f-bf8b-4b1a-801c-10b784815c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779826873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.779826873
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3217129572
Short name T879
Test name
Test status
Simulation time 216223606 ps
CPU time 0.8 seconds
Started Dec 27 01:39:39 PM PST 23
Finished Dec 27 01:39:40 PM PST 23
Peak memory 206784 kb
Host smart-9fb015aa-ee1e-4ca5-b1cc-734a3e3bbfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217129572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3217129572
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_tx_async_fifo_reset.2523986749
Short name T1640
Test name
Test status
Simulation time 40677205 ps
CPU time 0.74 seconds
Started Dec 27 01:37:35 PM PST 23
Finished Dec 27 01:37:37 PM PST 23
Peak memory 208444 kb
Host smart-4aaa43cd-724e-44cb-9490-5245f77b711e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523986749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tx_async_fifo_reset.2523986749
Directory /workspace/47.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/47.spi_device_txrx.2739136672
Short name T1287
Test name
Test status
Simulation time 32291863142 ps
CPU time 649.84 seconds
Started Dec 27 01:37:45 PM PST 23
Finished Dec 27 01:48:42 PM PST 23
Peak memory 325080 kb
Host smart-86366681-b44e-4de1-ab40-78082cc85aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739136672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_txrx.2739136672
Directory /workspace/47.spi_device_txrx/latest

Test location /workspace/coverage/default/47.spi_device_upload.2802663894
Short name T669
Test name
Test status
Simulation time 4928534249 ps
CPU time 19.55 seconds
Started Dec 27 01:37:53 PM PST 23
Finished Dec 27 01:38:16 PM PST 23
Peak memory 222480 kb
Host smart-caae6f00-cebd-48da-ad85-2aae538d5aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802663894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2802663894
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_abort.2399706921
Short name T1672
Test name
Test status
Simulation time 23123437 ps
CPU time 0.75 seconds
Started Dec 27 01:37:50 PM PST 23
Finished Dec 27 01:37:54 PM PST 23
Peak memory 206528 kb
Host smart-0cdad7af-7a2e-445e-bae5-cf4448d8441f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399706921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_abort.2399706921
Directory /workspace/48.spi_device_abort/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2343651973
Short name T1013
Test name
Test status
Simulation time 14525139 ps
CPU time 0.71 seconds
Started Dec 27 01:37:56 PM PST 23
Finished Dec 27 01:38:00 PM PST 23
Peak memory 206412 kb
Host smart-6092bd14-ef0f-4ef2-a5d2-7cb3fa0b523c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343651973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2343651973
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_bit_transfer.2131011691
Short name T1614
Test name
Test status
Simulation time 1170950286 ps
CPU time 3.22 seconds
Started Dec 27 01:37:54 PM PST 23
Finished Dec 27 01:38:01 PM PST 23
Peak memory 216832 kb
Host smart-f86ad11d-3f00-41fa-a444-151f283535cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131011691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_bit_transfer.2131011691
Directory /workspace/48.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/48.spi_device_byte_transfer.3627682297
Short name T530
Test name
Test status
Simulation time 189589006 ps
CPU time 2.6 seconds
Started Dec 27 01:37:53 PM PST 23
Finished Dec 27 01:37:59 PM PST 23
Peak memory 216892 kb
Host smart-e0c410cf-cf2d-42f3-9fbd-4c7fc45878e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627682297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_byte_transfer.3627682297
Directory /workspace/48.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1211146502
Short name T29
Test name
Test status
Simulation time 2004202815 ps
CPU time 4.56 seconds
Started Dec 27 01:37:53 PM PST 23
Finished Dec 27 01:38:02 PM PST 23
Peak memory 237980 kb
Host smart-b12c874e-e276-4a6e-b10d-dbd95f12b130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211146502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1211146502
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.4256315964
Short name T784
Test name
Test status
Simulation time 18278707 ps
CPU time 0.77 seconds
Started Dec 27 01:37:57 PM PST 23
Finished Dec 27 01:38:01 PM PST 23
Peak memory 207524 kb
Host smart-e222802c-e343-4a0f-b1dd-cf548f1f2f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256315964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.4256315964
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_dummy_item_extra_dly.964199437
Short name T501
Test name
Test status
Simulation time 370943775264 ps
CPU time 1422.69 seconds
Started Dec 27 01:37:53 PM PST 23
Finished Dec 27 02:01:40 PM PST 23
Peak memory 282036 kb
Host smart-4f394ecd-6a3b-409a-80e0-977cf35e5c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964199437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_dummy_item_extra_dly.964199437
Directory /workspace/48.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/48.spi_device_extreme_fifo_size.2234567566
Short name T1572
Test name
Test status
Simulation time 1858012847 ps
CPU time 25.65 seconds
Started Dec 27 01:37:53 PM PST 23
Finished Dec 27 01:38:23 PM PST 23
Peak memory 231996 kb
Host smart-60f0e4d4-9a87-47cb-91db-25823575e87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234567566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_extreme_fifo_size.2234567566
Directory /workspace/48.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/48.spi_device_fifo_full.3565088236
Short name T702
Test name
Test status
Simulation time 17832233999 ps
CPU time 1026.15 seconds
Started Dec 27 01:37:53 PM PST 23
Finished Dec 27 01:55:04 PM PST 23
Peak memory 279304 kb
Host smart-5f0c5bc1-418c-4826-a89b-ba9fc60d1256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565088236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_fifo_full.3565088236
Directory /workspace/48.spi_device_fifo_full/latest

Test location /workspace/coverage/default/48.spi_device_fifo_underflow_overflow.2183633421
Short name T1465
Test name
Test status
Simulation time 62116328245 ps
CPU time 535.1 seconds
Started Dec 27 01:37:51 PM PST 23
Finished Dec 27 01:46:51 PM PST 23
Peak memory 557096 kb
Host smart-45dc8db6-d0cd-48f2-8c80-1cca9ad5c860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183633421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_fifo_underflow_overf
low.2183633421
Directory /workspace/48.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2971926708
Short name T294
Test name
Test status
Simulation time 16583364582 ps
CPU time 93.64 seconds
Started Dec 27 01:37:55 PM PST 23
Finished Dec 27 01:39:33 PM PST 23
Peak memory 241344 kb
Host smart-1f2cef28-5286-4bd5-9d8e-a72b5039ac9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971926708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2971926708
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1417902997
Short name T1385
Test name
Test status
Simulation time 7799830886 ps
CPU time 79.11 seconds
Started Dec 27 01:37:56 PM PST 23
Finished Dec 27 01:39:18 PM PST 23
Peak memory 256384 kb
Host smart-ce616a5d-9c26-46ec-a0bd-ccd8058f66f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417902997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1417902997
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2367072670
Short name T853
Test name
Test status
Simulation time 148621875816 ps
CPU time 265.42 seconds
Started Dec 27 01:37:50 PM PST 23
Finished Dec 27 01:42:18 PM PST 23
Peak memory 250860 kb
Host smart-dc436c37-358b-44de-b275-8e7e6188eff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367072670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2367072670
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.730425791
Short name T1720
Test name
Test status
Simulation time 22859694555 ps
CPU time 21.19 seconds
Started Dec 27 01:37:50 PM PST 23
Finished Dec 27 01:38:14 PM PST 23
Peak memory 229352 kb
Host smart-a2fea2ad-9917-4eca-b054-07ef619b36c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730425791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.730425791
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1385377511
Short name T34
Test name
Test status
Simulation time 2657200022 ps
CPU time 6.5 seconds
Started Dec 27 01:37:56 PM PST 23
Finished Dec 27 01:38:05 PM PST 23
Peak memory 220768 kb
Host smart-ad7b82a7-173a-4963-a276-36a5e0fed4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385377511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1385377511
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_intr.2869260379
Short name T568
Test name
Test status
Simulation time 11796567703 ps
CPU time 38.08 seconds
Started Dec 27 01:37:50 PM PST 23
Finished Dec 27 01:38:31 PM PST 23
Peak memory 232308 kb
Host smart-d17e8bdc-f305-4370-93ac-a0fe1232b866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869260379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intr.2869260379
Directory /workspace/48.spi_device_intr/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2457218022
Short name T296
Test name
Test status
Simulation time 4902866335 ps
CPU time 22.29 seconds
Started Dec 27 01:37:51 PM PST 23
Finished Dec 27 01:38:17 PM PST 23
Peak memory 248952 kb
Host smart-a7996339-a3c9-4e58-a670-f9e7f9bc1478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457218022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2457218022
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3222058645
Short name T1390
Test name
Test status
Simulation time 2559680728 ps
CPU time 10.21 seconds
Started Dec 27 01:37:57 PM PST 23
Finished Dec 27 01:38:11 PM PST 23
Peak memory 238436 kb
Host smart-35ac1a10-e5f3-4ae6-9fbb-51c80475004d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222058645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3222058645
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.131063738
Short name T994
Test name
Test status
Simulation time 1649949396 ps
CPU time 3.93 seconds
Started Dec 27 01:37:58 PM PST 23
Finished Dec 27 01:38:05 PM PST 23
Peak memory 238324 kb
Host smart-94f96ce4-8369-4182-8250-0100a6cd12f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131063738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.131063738
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_perf.2065372623
Short name T598
Test name
Test status
Simulation time 21691100300 ps
CPU time 156.49 seconds
Started Dec 27 01:37:51 PM PST 23
Finished Dec 27 01:40:31 PM PST 23
Peak memory 257444 kb
Host smart-22656fc1-bfca-4680-a2e4-89f4bb07a03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065372623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_perf.2065372623
Directory /workspace/48.spi_device_perf/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1115660899
Short name T555
Test name
Test status
Simulation time 1162092619 ps
CPU time 6.95 seconds
Started Dec 27 01:37:56 PM PST 23
Finished Dec 27 01:38:06 PM PST 23
Peak memory 234252 kb
Host smart-648def53-3907-47db-b5b8-7144db6bd090
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1115660899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1115660899
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_rx_async_fifo_reset.654653562
Short name T946
Test name
Test status
Simulation time 307767501 ps
CPU time 0.9 seconds
Started Dec 27 01:37:56 PM PST 23
Finished Dec 27 01:38:00 PM PST 23
Peak memory 208408 kb
Host smart-77604c66-7850-472a-a2c5-46309bfba612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654653562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_rx_async_fifo_reset.654653562
Directory /workspace/48.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/48.spi_device_rx_timeout.3128043964
Short name T1259
Test name
Test status
Simulation time 2714683596 ps
CPU time 4.99 seconds
Started Dec 27 01:37:53 PM PST 23
Finished Dec 27 01:38:02 PM PST 23
Peak memory 216868 kb
Host smart-5c58fb87-2165-4cd3-afb6-d4d32ad33e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128043964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_rx_timeout.3128043964
Directory /workspace/48.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/48.spi_device_smoke.2701468755
Short name T686
Test name
Test status
Simulation time 65446078 ps
CPU time 1.23 seconds
Started Dec 27 01:37:53 PM PST 23
Finished Dec 27 01:37:58 PM PST 23
Peak memory 216596 kb
Host smart-6d68d307-ff8c-4322-83e6-bd8942dcfd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701468755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_smoke.2701468755
Directory /workspace/48.spi_device_smoke/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.540905856
Short name T1005
Test name
Test status
Simulation time 676340769970 ps
CPU time 769.49 seconds
Started Dec 27 01:37:57 PM PST 23
Finished Dec 27 01:50:50 PM PST 23
Peak memory 422888 kb
Host smart-09f51bb9-d3c4-4c11-a842-032d3bd490fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540905856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.540905856
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.933067786
Short name T681
Test name
Test status
Simulation time 41353398093 ps
CPU time 93.11 seconds
Started Dec 27 01:37:52 PM PST 23
Finished Dec 27 01:39:29 PM PST 23
Peak memory 216944 kb
Host smart-8bb0ab29-8faf-41d3-ae0f-82fa35fc3821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933067786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.933067786
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.494522896
Short name T1029
Test name
Test status
Simulation time 12373984834 ps
CPU time 12.48 seconds
Started Dec 27 01:37:54 PM PST 23
Finished Dec 27 01:38:10 PM PST 23
Peak memory 216868 kb
Host smart-242c19e6-7db0-47cd-8259-e19c4ad10340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494522896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.494522896
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.385787797
Short name T1456
Test name
Test status
Simulation time 36618676 ps
CPU time 1.26 seconds
Started Dec 27 01:37:55 PM PST 23
Finished Dec 27 01:37:59 PM PST 23
Peak memory 216904 kb
Host smart-20d988b9-ded1-4926-a902-4af3ec8ab421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385787797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.385787797
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2061600810
Short name T485
Test name
Test status
Simulation time 203924370 ps
CPU time 1 seconds
Started Dec 27 01:37:56 PM PST 23
Finished Dec 27 01:38:00 PM PST 23
Peak memory 206856 kb
Host smart-769d6229-85f2-4c94-8daa-0b46bc3720c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061600810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2061600810
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_tx_async_fifo_reset.3732469262
Short name T614
Test name
Test status
Simulation time 42844596 ps
CPU time 0.78 seconds
Started Dec 27 01:37:53 PM PST 23
Finished Dec 27 01:37:58 PM PST 23
Peak memory 208452 kb
Host smart-7cb0fb48-34ab-4567-9fb4-51a4199e79c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732469262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tx_async_fifo_reset.3732469262
Directory /workspace/48.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/48.spi_device_txrx.2744536411
Short name T1666
Test name
Test status
Simulation time 23588568777 ps
CPU time 230.92 seconds
Started Dec 27 01:37:54 PM PST 23
Finished Dec 27 01:41:48 PM PST 23
Peak memory 241284 kb
Host smart-059d1596-6867-4296-8f92-37ba9c5710a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744536411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_txrx.2744536411
Directory /workspace/48.spi_device_txrx/latest

Test location /workspace/coverage/default/48.spi_device_upload.3481596740
Short name T1523
Test name
Test status
Simulation time 487864383 ps
CPU time 2.54 seconds
Started Dec 27 01:38:25 PM PST 23
Finished Dec 27 01:38:28 PM PST 23
Peak memory 219076 kb
Host smart-40a4afdf-11d5-4f40-92ae-f3a490285933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481596740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3481596740
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_abort.1654734942
Short name T576
Test name
Test status
Simulation time 51839701 ps
CPU time 0.76 seconds
Started Dec 27 01:37:55 PM PST 23
Finished Dec 27 01:38:03 PM PST 23
Peak memory 206672 kb
Host smart-d4aefc78-6d9f-4349-a2c4-7c3a63b76cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654734942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_abort.1654734942
Directory /workspace/49.spi_device_abort/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3825408259
Short name T637
Test name
Test status
Simulation time 68318008 ps
CPU time 0.75 seconds
Started Dec 27 01:38:20 PM PST 23
Finished Dec 27 01:38:23 PM PST 23
Peak memory 206392 kb
Host smart-799fe527-862e-4c3e-9e3e-fecc809f6e20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825408259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3825408259
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_bit_transfer.906609988
Short name T1229
Test name
Test status
Simulation time 155809030 ps
CPU time 2.16 seconds
Started Dec 27 01:38:31 PM PST 23
Finished Dec 27 01:38:35 PM PST 23
Peak memory 216784 kb
Host smart-58ee7e90-e765-4abe-9b09-28093bbff261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906609988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_bit_transfer.906609988
Directory /workspace/49.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/49.spi_device_byte_transfer.752961719
Short name T947
Test name
Test status
Simulation time 648692906 ps
CPU time 2.6 seconds
Started Dec 27 01:38:32 PM PST 23
Finished Dec 27 01:38:35 PM PST 23
Peak memory 216800 kb
Host smart-ecd8be34-5fbf-452e-9a59-0fc8373b3398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752961719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_byte_transfer.752961719
Directory /workspace/49.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1175929686
Short name T500
Test name
Test status
Simulation time 25045169 ps
CPU time 0.74 seconds
Started Dec 27 01:38:26 PM PST 23
Finished Dec 27 01:38:28 PM PST 23
Peak memory 206600 kb
Host smart-df9904d3-9a9c-4c18-8e26-bd1ab7ef3be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175929686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1175929686
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_fifo_full.1908237596
Short name T697
Test name
Test status
Simulation time 26415385357 ps
CPU time 202.16 seconds
Started Dec 27 01:37:54 PM PST 23
Finished Dec 27 01:41:20 PM PST 23
Peak memory 266200 kb
Host smart-34d1f793-c4c2-4485-9c50-2b8a3a6d2ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908237596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_fifo_full.1908237596
Directory /workspace/49.spi_device_fifo_full/latest

Test location /workspace/coverage/default/49.spi_device_fifo_underflow_overflow.3749896376
Short name T916
Test name
Test status
Simulation time 122879685122 ps
CPU time 570.59 seconds
Started Dec 27 01:38:29 PM PST 23
Finished Dec 27 01:48:02 PM PST 23
Peak memory 432680 kb
Host smart-8d481a5b-cb30-4073-90f0-1ae1fd6ce279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749896376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_fifo_underflow_overf
low.3749896376
Directory /workspace/49.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3232480703
Short name T1656
Test name
Test status
Simulation time 49503537029 ps
CPU time 30.19 seconds
Started Dec 27 01:38:21 PM PST 23
Finished Dec 27 01:38:53 PM PST 23
Peak memory 225208 kb
Host smart-51963be0-b010-4192-be60-74e281b857c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232480703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3232480703
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.4032486583
Short name T1144
Test name
Test status
Simulation time 11921733060 ps
CPU time 42.79 seconds
Started Dec 27 01:38:28 PM PST 23
Finished Dec 27 01:39:13 PM PST 23
Peak memory 250676 kb
Host smart-6df8c11c-e4c3-4ad7-a2ee-96bd4948a66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032486583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.4032486583
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.514586818
Short name T1125
Test name
Test status
Simulation time 2666401746 ps
CPU time 6.74 seconds
Started Dec 27 01:37:58 PM PST 23
Finished Dec 27 01:38:08 PM PST 23
Peak memory 238568 kb
Host smart-77949f64-6491-454e-bb5d-eb146adf0e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514586818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.514586818
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_intr.3934374918
Short name T993
Test name
Test status
Simulation time 45060198866 ps
CPU time 95.32 seconds
Started Dec 27 01:38:33 PM PST 23
Finished Dec 27 01:40:10 PM PST 23
Peak memory 233212 kb
Host smart-aa0e43fc-7313-420f-ac18-b46ce3a0e2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934374918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intr.3934374918
Directory /workspace/49.spi_device_intr/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1183736919
Short name T1586
Test name
Test status
Simulation time 222601039518 ps
CPU time 60.96 seconds
Started Dec 27 01:37:57 PM PST 23
Finished Dec 27 01:39:01 PM PST 23
Peak memory 220352 kb
Host smart-05155508-391b-4092-a39b-545347e0ed5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183736919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1183736919
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2439928544
Short name T1705
Test name
Test status
Simulation time 174161857106 ps
CPU time 44.86 seconds
Started Dec 27 01:38:26 PM PST 23
Finished Dec 27 01:39:13 PM PST 23
Peak memory 225104 kb
Host smart-e6542d62-1ae4-4448-bbc1-1a4f60117673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439928544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2439928544
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1380169718
Short name T1650
Test name
Test status
Simulation time 665444442 ps
CPU time 4.56 seconds
Started Dec 27 01:38:29 PM PST 23
Finished Dec 27 01:38:36 PM PST 23
Peak memory 218476 kb
Host smart-3313a486-622b-4a8a-95a0-2d8d5019a323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380169718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1380169718
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_perf.436323899
Short name T809
Test name
Test status
Simulation time 273736251168 ps
CPU time 714.45 seconds
Started Dec 27 01:38:33 PM PST 23
Finished Dec 27 01:50:28 PM PST 23
Peak memory 273720 kb
Host smart-5380a104-07ab-4010-8364-fc432708840f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436323899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_perf.436323899
Directory /workspace/49.spi_device_perf/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2362911063
Short name T877
Test name
Test status
Simulation time 750415422 ps
CPU time 5.3 seconds
Started Dec 27 01:38:09 PM PST 23
Finished Dec 27 01:38:15 PM PST 23
Peak memory 220188 kb
Host smart-5e11c446-af89-43a8-8264-7213f70f59af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2362911063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2362911063
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_rx_async_fifo_reset.159663730
Short name T1550
Test name
Test status
Simulation time 64570872 ps
CPU time 0.83 seconds
Started Dec 27 01:37:55 PM PST 23
Finished Dec 27 01:37:59 PM PST 23
Peak memory 208416 kb
Host smart-cbb4362e-5d33-4b9b-8fa3-e8d74584c715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159663730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_rx_async_fifo_reset.159663730
Directory /workspace/49.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/49.spi_device_rx_timeout.639791922
Short name T1155
Test name
Test status
Simulation time 9322701921 ps
CPU time 5.35 seconds
Started Dec 27 01:38:32 PM PST 23
Finished Dec 27 01:38:38 PM PST 23
Peak memory 216872 kb
Host smart-c7120581-5196-4b57-951a-01c8d7f35945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639791922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_rx_timeout.639791922
Directory /workspace/49.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/49.spi_device_smoke.134603031
Short name T849
Test name
Test status
Simulation time 137797190 ps
CPU time 1.24 seconds
Started Dec 27 01:38:32 PM PST 23
Finished Dec 27 01:38:34 PM PST 23
Peak memory 216860 kb
Host smart-6dedbfaa-d00e-4b90-958a-4cbd4582d1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134603031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_smoke.134603031
Directory /workspace/49.spi_device_smoke/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2738243597
Short name T88
Test name
Test status
Simulation time 123445726624 ps
CPU time 1301.22 seconds
Started Dec 27 01:38:38 PM PST 23
Finished Dec 27 02:00:21 PM PST 23
Peak memory 389336 kb
Host smart-41c3d0b6-eafc-4e88-a222-cb04b290b551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738243597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2738243597
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.874184625
Short name T1612
Test name
Test status
Simulation time 2453633554 ps
CPU time 10.03 seconds
Started Dec 27 01:38:49 PM PST 23
Finished Dec 27 01:39:00 PM PST 23
Peak memory 220712 kb
Host smart-00980b02-1164-437b-bfd2-deb5970d789b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874184625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.874184625
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.218386958
Short name T1204
Test name
Test status
Simulation time 18973737908 ps
CPU time 29.47 seconds
Started Dec 27 01:38:28 PM PST 23
Finished Dec 27 01:38:59 PM PST 23
Peak memory 216932 kb
Host smart-f957c992-8433-4bac-9fda-49f909c5be76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218386958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.218386958
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2660077873
Short name T735
Test name
Test status
Simulation time 21661966 ps
CPU time 0.77 seconds
Started Dec 27 01:37:55 PM PST 23
Finished Dec 27 01:37:59 PM PST 23
Peak memory 206948 kb
Host smart-8cfe7747-dc5d-4ff6-aa18-0e870adfc080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660077873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2660077873
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.4102039878
Short name T1025
Test name
Test status
Simulation time 136157863 ps
CPU time 0.76 seconds
Started Dec 27 01:37:56 PM PST 23
Finished Dec 27 01:38:00 PM PST 23
Peak memory 206924 kb
Host smart-0cae0255-db26-4f4a-abac-e797ef0a6220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102039878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.4102039878
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_tx_async_fifo_reset.1908503750
Short name T996
Test name
Test status
Simulation time 16858256 ps
CPU time 0.81 seconds
Started Dec 27 01:37:57 PM PST 23
Finished Dec 27 01:38:01 PM PST 23
Peak memory 208492 kb
Host smart-59be70b2-8045-46d9-881b-5d8bbd9b493a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908503750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tx_async_fifo_reset.1908503750
Directory /workspace/49.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/49.spi_device_txrx.1849705819
Short name T1026
Test name
Test status
Simulation time 326245009596 ps
CPU time 1210.61 seconds
Started Dec 27 01:37:58 PM PST 23
Finished Dec 27 01:58:12 PM PST 23
Peak memory 243632 kb
Host smart-9e1e3b21-e9d6-4c8e-bd8a-7e7d53237b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849705819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_txrx.1849705819
Directory /workspace/49.spi_device_txrx/latest

Test location /workspace/coverage/default/49.spi_device_upload.3038722401
Short name T232
Test name
Test status
Simulation time 7680009011 ps
CPU time 30.29 seconds
Started Dec 27 01:38:33 PM PST 23
Finished Dec 27 01:39:04 PM PST 23
Peak memory 241428 kb
Host smart-ed83e049-3ed9-44be-ad91-6ebf545f7d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038722401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3038722401
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_abort.4119961117
Short name T1598
Test name
Test status
Simulation time 46434612 ps
CPU time 0.72 seconds
Started Dec 27 01:30:37 PM PST 23
Finished Dec 27 01:30:39 PM PST 23
Peak memory 206548 kb
Host smart-b43c2f61-2ebf-4b9f-8138-e6dbe3abbbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119961117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_abort.4119961117
Directory /workspace/5.spi_device_abort/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.176530072
Short name T764
Test name
Test status
Simulation time 11488422 ps
CPU time 0.69 seconds
Started Dec 27 01:30:10 PM PST 23
Finished Dec 27 01:30:14 PM PST 23
Peak memory 206444 kb
Host smart-1a16d927-715f-41bd-84fb-d6fae9f3da22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176530072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.176530072
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_bit_transfer.1246989546
Short name T866
Test name
Test status
Simulation time 169682910 ps
CPU time 2.4 seconds
Started Dec 27 01:30:38 PM PST 23
Finished Dec 27 01:30:41 PM PST 23
Peak memory 216820 kb
Host smart-f22ec3c3-4a04-47c3-8469-1dceeef2d164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246989546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_bit_transfer.1246989546
Directory /workspace/5.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/5.spi_device_byte_transfer.4153792587
Short name T1258
Test name
Test status
Simulation time 1236605101 ps
CPU time 3.4 seconds
Started Dec 27 01:30:15 PM PST 23
Finished Dec 27 01:30:22 PM PST 23
Peak memory 216848 kb
Host smart-99ea95bf-7369-4b02-aa96-af2d8c96fe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153792587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_byte_transfer.4153792587
Directory /workspace/5.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.989887619
Short name T297
Test name
Test status
Simulation time 379201074 ps
CPU time 3.17 seconds
Started Dec 27 01:30:23 PM PST 23
Finished Dec 27 01:30:28 PM PST 23
Peak memory 239384 kb
Host smart-4dd202d1-6d96-46d6-add3-9345b24169bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989887619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.989887619
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3144020708
Short name T745
Test name
Test status
Simulation time 36643864 ps
CPU time 0.76 seconds
Started Dec 27 01:30:27 PM PST 23
Finished Dec 27 01:30:30 PM PST 23
Peak memory 207620 kb
Host smart-add0c333-6022-4f36-be5f-9cc444eb4772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144020708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3144020708
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_dummy_item_extra_dly.879596742
Short name T206
Test name
Test status
Simulation time 71712224779 ps
CPU time 120.08 seconds
Started Dec 27 01:30:13 PM PST 23
Finished Dec 27 01:32:18 PM PST 23
Peak memory 270548 kb
Host smart-7f9b1311-9277-4bc9-9092-c129365cf050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879596742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_dummy_item_extra_dly.879596742
Directory /workspace/5.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/5.spi_device_extreme_fifo_size.3160612078
Short name T276
Test name
Test status
Simulation time 42317770030 ps
CPU time 57.69 seconds
Started Dec 27 01:30:04 PM PST 23
Finished Dec 27 01:31:03 PM PST 23
Peak memory 234900 kb
Host smart-1bd8858b-0bb4-420c-9c66-fb8feb3f91d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160612078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_extreme_fifo_size.3160612078
Directory /workspace/5.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/5.spi_device_fifo_full.146921394
Short name T1521
Test name
Test status
Simulation time 45027086618 ps
CPU time 276.15 seconds
Started Dec 27 01:30:17 PM PST 23
Finished Dec 27 01:34:56 PM PST 23
Peak memory 272560 kb
Host smart-f570644a-2e1d-48e5-ba82-5ceb9c5ee112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146921394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_fifo_full.146921394
Directory /workspace/5.spi_device_fifo_full/latest

Test location /workspace/coverage/default/5.spi_device_fifo_underflow_overflow.1965770557
Short name T928
Test name
Test status
Simulation time 11652285355 ps
CPU time 124.35 seconds
Started Dec 27 01:30:33 PM PST 23
Finished Dec 27 01:32:38 PM PST 23
Peak memory 273696 kb
Host smart-b844ca47-6466-494f-8969-5e8e36d1687d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965770557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_fifo_underflow_overfl
ow.1965770557
Directory /workspace/5.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1876311866
Short name T1433
Test name
Test status
Simulation time 363472417 ps
CPU time 6.32 seconds
Started Dec 27 01:30:26 PM PST 23
Finished Dec 27 01:30:34 PM PST 23
Peak memory 241464 kb
Host smart-a5335122-edfa-4cd9-825f-90d7d026c3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876311866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1876311866
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2449992300
Short name T254
Test name
Test status
Simulation time 11081815257 ps
CPU time 53.13 seconds
Started Dec 27 01:30:39 PM PST 23
Finished Dec 27 01:31:33 PM PST 23
Peak memory 249804 kb
Host smart-e4a33604-0a74-4caf-ad3b-80a03a4b6ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449992300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2449992300
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4035580004
Short name T286
Test name
Test status
Simulation time 27401919477 ps
CPU time 96.51 seconds
Started Dec 27 01:30:59 PM PST 23
Finished Dec 27 01:32:36 PM PST 23
Peak memory 249876 kb
Host smart-f1d7acd1-177e-49ee-8375-15c2fbabd41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035580004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.4035580004
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.923245908
Short name T194
Test name
Test status
Simulation time 23915400305 ps
CPU time 19.06 seconds
Started Dec 27 01:30:46 PM PST 23
Finished Dec 27 01:31:06 PM PST 23
Peak memory 241340 kb
Host smart-f1f3a01e-a79f-4a35-9548-9556c67958b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923245908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.923245908
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.920658990
Short name T1092
Test name
Test status
Simulation time 8503230004 ps
CPU time 13.49 seconds
Started Dec 27 01:30:35 PM PST 23
Finished Dec 27 01:30:50 PM PST 23
Peak memory 220828 kb
Host smart-13535c83-0722-466c-9a39-8f81529af219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920658990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.920658990
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_intr.4077981987
Short name T868
Test name
Test status
Simulation time 80120818252 ps
CPU time 19.9 seconds
Started Dec 27 01:30:16 PM PST 23
Finished Dec 27 01:30:39 PM PST 23
Peak memory 219880 kb
Host smart-697a3961-e321-42c1-b636-c9aed047798e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077981987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intr.4077981987
Directory /workspace/5.spi_device_intr/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3864363041
Short name T1319
Test name
Test status
Simulation time 3977479374 ps
CPU time 16.07 seconds
Started Dec 27 01:30:32 PM PST 23
Finished Dec 27 01:30:49 PM PST 23
Peak memory 249672 kb
Host smart-21a387b0-8694-4feb-9f3f-a6237e1feeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864363041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3864363041
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1944921396
Short name T936
Test name
Test status
Simulation time 33946285 ps
CPU time 1.12 seconds
Started Dec 27 01:30:34 PM PST 23
Finished Dec 27 01:30:36 PM PST 23
Peak memory 218816 kb
Host smart-632f78c2-3a9e-4626-9ae2-0100a0b80c59
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944921396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1944921396
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1917145301
Short name T344
Test name
Test status
Simulation time 8067482280 ps
CPU time 9.2 seconds
Started Dec 27 01:30:25 PM PST 23
Finished Dec 27 01:30:36 PM PST 23
Peak memory 240444 kb
Host smart-243ab9d7-cf91-4a31-80cf-823359d8b16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917145301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1917145301
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.575608750
Short name T1078
Test name
Test status
Simulation time 7896367285 ps
CPU time 10.01 seconds
Started Dec 27 01:30:29 PM PST 23
Finished Dec 27 01:30:40 PM PST 23
Peak memory 249712 kb
Host smart-06ad9e5f-bbe4-4fd6-945d-0577101ee0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575608750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.575608750
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_perf.3705161449
Short name T1499
Test name
Test status
Simulation time 36067342975 ps
CPU time 372.08 seconds
Started Dec 27 01:30:34 PM PST 23
Finished Dec 27 01:36:47 PM PST 23
Peak memory 254132 kb
Host smart-dab91ce1-2d23-4ec1-b47e-5832ba78eaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705161449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_perf.3705161449
Directory /workspace/5.spi_device_perf/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.2430453559
Short name T1291
Test name
Test status
Simulation time 58624243 ps
CPU time 0.81 seconds
Started Dec 27 01:30:40 PM PST 23
Finished Dec 27 01:30:42 PM PST 23
Peak memory 216692 kb
Host smart-45e6a57a-bd0d-4769-9525-b5945f2850d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430453559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.2430453559
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1023124306
Short name T978
Test name
Test status
Simulation time 198854793 ps
CPU time 3.96 seconds
Started Dec 27 01:30:57 PM PST 23
Finished Dec 27 01:31:02 PM PST 23
Peak memory 234344 kb
Host smart-66fbd475-6430-4059-bbbc-57ddabefbd34
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1023124306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1023124306
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_rx_async_fifo_reset.1202283893
Short name T1464
Test name
Test status
Simulation time 56602420 ps
CPU time 0.92 seconds
Started Dec 27 01:30:48 PM PST 23
Finished Dec 27 01:30:49 PM PST 23
Peak memory 208436 kb
Host smart-45a03a54-ccc4-41c6-ba37-3fe2c1bb8c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202283893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_rx_async_fifo_reset.1202283893
Directory /workspace/5.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/5.spi_device_rx_timeout.1183213490
Short name T733
Test name
Test status
Simulation time 803675996 ps
CPU time 6.21 seconds
Started Dec 27 01:30:45 PM PST 23
Finished Dec 27 01:30:52 PM PST 23
Peak memory 216744 kb
Host smart-6e3e1df1-c678-43d3-a949-9622f100b1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183213490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_rx_timeout.1183213490
Directory /workspace/5.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2179839127
Short name T689
Test name
Test status
Simulation time 121584910233 ps
CPU time 959.3 seconds
Started Dec 27 01:30:27 PM PST 23
Finished Dec 27 01:46:28 PM PST 23
Peak memory 338184 kb
Host smart-899eb74e-261e-44ab-a451-58b1e2ac6de8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179839127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2179839127
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3728577835
Short name T351
Test name
Test status
Simulation time 10200368221 ps
CPU time 39.22 seconds
Started Dec 27 01:30:25 PM PST 23
Finished Dec 27 01:31:06 PM PST 23
Peak memory 217172 kb
Host smart-2ff9ebdf-05a4-4c07-93ef-d52466f34c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728577835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3728577835
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3842577004
Short name T1497
Test name
Test status
Simulation time 2432318576 ps
CPU time 10.39 seconds
Started Dec 27 01:30:22 PM PST 23
Finished Dec 27 01:30:34 PM PST 23
Peak memory 216880 kb
Host smart-c1d24e31-9479-4f67-a24a-4eca05c7218b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842577004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3842577004
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.4201516697
Short name T1699
Test name
Test status
Simulation time 79426071 ps
CPU time 3.22 seconds
Started Dec 27 01:30:39 PM PST 23
Finished Dec 27 01:30:43 PM PST 23
Peak memory 216804 kb
Host smart-caff3014-9577-47ed-9af3-ba990a887eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201516697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.4201516697
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1699406346
Short name T1667
Test name
Test status
Simulation time 81424863 ps
CPU time 0.93 seconds
Started Dec 27 01:30:37 PM PST 23
Finished Dec 27 01:30:39 PM PST 23
Peak memory 206800 kb
Host smart-b0902389-ed4c-439c-bfbc-a08918bb95c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699406346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1699406346
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_tx_async_fifo_reset.649683527
Short name T940
Test name
Test status
Simulation time 121863057 ps
CPU time 0.8 seconds
Started Dec 27 01:30:16 PM PST 23
Finished Dec 27 01:30:20 PM PST 23
Peak memory 208476 kb
Host smart-15e10c33-a5c6-4293-9647-257924b2a358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649683527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tx_async_fifo_reset.649683527
Directory /workspace/5.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/5.spi_device_txrx.29274028
Short name T1399
Test name
Test status
Simulation time 42689021799 ps
CPU time 376.02 seconds
Started Dec 27 01:30:41 PM PST 23
Finished Dec 27 01:36:58 PM PST 23
Peak memory 268292 kb
Host smart-f6af3f4d-f8ca-4fad-b1d7-202f2d1e75dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29274028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_txrx.29274028
Directory /workspace/5.spi_device_txrx/latest

Test location /workspace/coverage/default/5.spi_device_upload.4147784384
Short name T1340
Test name
Test status
Simulation time 973781051 ps
CPU time 5.26 seconds
Started Dec 27 01:30:23 PM PST 23
Finished Dec 27 01:30:30 PM PST 23
Peak memory 218964 kb
Host smart-6d845d76-b3c6-4755-9c50-d1ff271dbb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147784384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.4147784384
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_abort.1364327039
Short name T535
Test name
Test status
Simulation time 45410763 ps
CPU time 0.74 seconds
Started Dec 27 01:30:58 PM PST 23
Finished Dec 27 01:30:59 PM PST 23
Peak memory 206608 kb
Host smart-c0f811a4-f4bf-4500-a484-046b177c6095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364327039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_abort.1364327039
Directory /workspace/6.spi_device_abort/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3733398229
Short name T931
Test name
Test status
Simulation time 33220967 ps
CPU time 0.76 seconds
Started Dec 27 01:30:54 PM PST 23
Finished Dec 27 01:30:56 PM PST 23
Peak memory 206448 kb
Host smart-fdbf42cb-6cf5-40ef-81ea-6bd612b0fb9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733398229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
733398229
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_bit_transfer.3213592135
Short name T1411
Test name
Test status
Simulation time 180644572 ps
CPU time 2.12 seconds
Started Dec 27 01:30:50 PM PST 23
Finished Dec 27 01:30:52 PM PST 23
Peak memory 216880 kb
Host smart-4cda22ac-413a-4cf0-b3cb-7bd4d75e0b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213592135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_bit_transfer.3213592135
Directory /workspace/6.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/6.spi_device_byte_transfer.3629507079
Short name T682
Test name
Test status
Simulation time 102085679 ps
CPU time 2.43 seconds
Started Dec 27 01:30:54 PM PST 23
Finished Dec 27 01:30:57 PM PST 23
Peak memory 216720 kb
Host smart-8c74a886-0bcf-46aa-9d08-470662e6cce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629507079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_byte_transfer.3629507079
Directory /workspace/6.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3448592841
Short name T951
Test name
Test status
Simulation time 221379048 ps
CPU time 5.29 seconds
Started Dec 27 01:30:36 PM PST 23
Finished Dec 27 01:30:42 PM PST 23
Peak memory 240508 kb
Host smart-e99f2099-4f8a-4c31-885f-4c8ded2f505b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448592841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3448592841
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3916108783
Short name T1127
Test name
Test status
Simulation time 188488982 ps
CPU time 0.75 seconds
Started Dec 27 01:30:49 PM PST 23
Finished Dec 27 01:30:50 PM PST 23
Peak memory 206608 kb
Host smart-ef7bfc28-01e8-422d-9751-fcda034ba7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916108783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3916108783
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_dummy_item_extra_dly.2241418522
Short name T1059
Test name
Test status
Simulation time 50850960030 ps
CPU time 792.83 seconds
Started Dec 27 01:30:39 PM PST 23
Finished Dec 27 01:43:58 PM PST 23
Peak memory 306132 kb
Host smart-c539ab91-6e52-47cb-b5d3-77176eab3da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241418522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_dummy_item_extra_dly.2241418522
Directory /workspace/6.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/6.spi_device_extreme_fifo_size.3191970249
Short name T204
Test name
Test status
Simulation time 139431867092 ps
CPU time 2732.15 seconds
Started Dec 27 01:30:42 PM PST 23
Finished Dec 27 02:16:15 PM PST 23
Peak memory 219268 kb
Host smart-0aeac8aa-3609-4727-a396-d73ce2634e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191970249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_extreme_fifo_size.3191970249
Directory /workspace/6.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/6.spi_device_fifo_full.1639097849
Short name T1395
Test name
Test status
Simulation time 37938301276 ps
CPU time 532.25 seconds
Started Dec 27 01:30:33 PM PST 23
Finished Dec 27 01:39:27 PM PST 23
Peak memory 307444 kb
Host smart-27471da8-717b-43a2-98d1-f839f5409b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639097849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_fifo_full.1639097849
Directory /workspace/6.spi_device_fifo_full/latest

Test location /workspace/coverage/default/6.spi_device_fifo_underflow_overflow.3077689638
Short name T1462
Test name
Test status
Simulation time 16737170306 ps
CPU time 273.52 seconds
Started Dec 27 01:30:39 PM PST 23
Finished Dec 27 01:35:13 PM PST 23
Peak memory 352084 kb
Host smart-4fe840b8-0a4c-4a58-8f1e-5e74a3274ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077689638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_fifo_underflow_overfl
ow.3077689638
Directory /workspace/6.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.90470218
Short name T328
Test name
Test status
Simulation time 2533770684 ps
CPU time 26.1 seconds
Started Dec 27 01:30:37 PM PST 23
Finished Dec 27 01:31:04 PM PST 23
Peak memory 250732 kb
Host smart-3c6bd4d8-e60b-4dc7-9074-e5745cbe57f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90470218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.90470218
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3304187494
Short name T1476
Test name
Test status
Simulation time 21417192938 ps
CPU time 31.28 seconds
Started Dec 27 01:30:56 PM PST 23
Finished Dec 27 01:31:28 PM PST 23
Peak memory 241588 kb
Host smart-cc9a440a-ce87-4708-b615-02ef9ce7ab69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304187494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3304187494
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2151064014
Short name T1627
Test name
Test status
Simulation time 130220485 ps
CPU time 2.53 seconds
Started Dec 27 01:30:53 PM PST 23
Finished Dec 27 01:30:56 PM PST 23
Peak memory 218416 kb
Host smart-bf60e079-c135-4bfa-b850-fedb7f0ebd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151064014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2151064014
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_intr.2503928581
Short name T1320
Test name
Test status
Simulation time 94807779361 ps
CPU time 109.63 seconds
Started Dec 27 01:30:40 PM PST 23
Finished Dec 27 01:32:30 PM PST 23
Peak memory 247732 kb
Host smart-f7587a07-ec55-4d95-aff0-1f1bdaa2e264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503928581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intr.2503928581
Directory /workspace/6.spi_device_intr/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2361680230
Short name T272
Test name
Test status
Simulation time 16240303175 ps
CPU time 29.01 seconds
Started Dec 27 01:30:36 PM PST 23
Finished Dec 27 01:31:06 PM PST 23
Peak memory 228940 kb
Host smart-1cdb247a-f057-46bc-80f0-1b7200e4ef8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361680230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2361680230
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2343640861
Short name T1474
Test name
Test status
Simulation time 26220590 ps
CPU time 1.04 seconds
Started Dec 27 01:30:40 PM PST 23
Finished Dec 27 01:30:42 PM PST 23
Peak memory 218748 kb
Host smart-b32f24f1-8d23-47db-9220-2154ea51a223
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343640861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2343640861
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.401996356
Short name T1425
Test name
Test status
Simulation time 399674674 ps
CPU time 3.85 seconds
Started Dec 27 01:30:55 PM PST 23
Finished Dec 27 01:30:59 PM PST 23
Peak memory 238608 kb
Host smart-aac2b9f0-220c-4a48-b682-4f3670a880a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401996356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
401996356
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2123630503
Short name T1741
Test name
Test status
Simulation time 252565626 ps
CPU time 4.71 seconds
Started Dec 27 01:30:50 PM PST 23
Finished Dec 27 01:30:55 PM PST 23
Peak memory 220012 kb
Host smart-f55681d5-dc5f-45ee-9ccc-a3ce32c7638e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123630503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2123630503
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_perf.1892374869
Short name T1174
Test name
Test status
Simulation time 123925282013 ps
CPU time 263.24 seconds
Started Dec 27 01:30:35 PM PST 23
Finished Dec 27 01:34:59 PM PST 23
Peak memory 232144 kb
Host smart-bc4febe3-782f-4663-90a7-29c4393845e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892374869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_perf.1892374869
Directory /workspace/6.spi_device_perf/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.2817551021
Short name T1232
Test name
Test status
Simulation time 30993626 ps
CPU time 0.76 seconds
Started Dec 27 01:30:58 PM PST 23
Finished Dec 27 01:31:00 PM PST 23
Peak memory 216736 kb
Host smart-61f46bc9-57f7-4f9c-b04f-9f7c385c3098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817551021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.2817551021
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2547924681
Short name T1729
Test name
Test status
Simulation time 571769874 ps
CPU time 3.64 seconds
Started Dec 27 01:31:00 PM PST 23
Finished Dec 27 01:31:05 PM PST 23
Peak memory 221100 kb
Host smart-a477d35c-29a5-43da-83af-c79fade0a798
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2547924681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2547924681
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_rx_async_fifo_reset.4222794888
Short name T687
Test name
Test status
Simulation time 42111410 ps
CPU time 0.93 seconds
Started Dec 27 01:30:39 PM PST 23
Finished Dec 27 01:30:40 PM PST 23
Peak memory 208448 kb
Host smart-fd47606e-c30d-4fdc-87d7-3e7db1481b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222794888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_rx_async_fifo_reset.4222794888
Directory /workspace/6.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/6.spi_device_rx_timeout.1458229493
Short name T583
Test name
Test status
Simulation time 2845043966 ps
CPU time 6.14 seconds
Started Dec 27 01:30:51 PM PST 23
Finished Dec 27 01:30:58 PM PST 23
Peak memory 216848 kb
Host smart-9a4ef9b4-a6de-4d6b-ab7b-8515d3d4c97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458229493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_rx_timeout.1458229493
Directory /workspace/6.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/6.spi_device_smoke.3863107785
Short name T905
Test name
Test status
Simulation time 21870942 ps
CPU time 1.09 seconds
Started Dec 27 01:30:34 PM PST 23
Finished Dec 27 01:30:36 PM PST 23
Peak memory 216572 kb
Host smart-657922f8-f055-4469-8e0b-cabe3ceadb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863107785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_smoke.3863107785
Directory /workspace/6.spi_device_smoke/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1624119953
Short name T325
Test name
Test status
Simulation time 743911908312 ps
CPU time 1865.16 seconds
Started Dec 27 01:30:58 PM PST 23
Finished Dec 27 02:02:04 PM PST 23
Peak memory 348996 kb
Host smart-38717727-3e9d-4c23-a960-038862fb7fc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624119953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1624119953
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.600210182
Short name T353
Test name
Test status
Simulation time 4071751519 ps
CPU time 23.74 seconds
Started Dec 27 01:30:57 PM PST 23
Finished Dec 27 01:31:21 PM PST 23
Peak memory 216976 kb
Host smart-69a22390-bcfc-45b8-bc83-012e25714b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600210182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.600210182
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2407299471
Short name T1479
Test name
Test status
Simulation time 3844684074 ps
CPU time 3.94 seconds
Started Dec 27 01:30:44 PM PST 23
Finished Dec 27 01:30:49 PM PST 23
Peak memory 216928 kb
Host smart-4e01ef2c-58e7-47bb-b70d-8031a5edb320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407299471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2407299471
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2130504060
Short name T952
Test name
Test status
Simulation time 1219411519 ps
CPU time 2.95 seconds
Started Dec 27 01:30:51 PM PST 23
Finished Dec 27 01:30:55 PM PST 23
Peak memory 216748 kb
Host smart-26019200-f0f2-4818-ad98-23f8ccc587a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130504060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2130504060
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1611641636
Short name T1597
Test name
Test status
Simulation time 50123674 ps
CPU time 0.8 seconds
Started Dec 27 01:30:57 PM PST 23
Finished Dec 27 01:30:58 PM PST 23
Peak memory 206944 kb
Host smart-d45d98d3-d9bd-4b81-92cd-559fa06121df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611641636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1611641636
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_tx_async_fifo_reset.1783800536
Short name T651
Test name
Test status
Simulation time 50748069 ps
CPU time 0.82 seconds
Started Dec 27 01:31:02 PM PST 23
Finished Dec 27 01:31:04 PM PST 23
Peak memory 208420 kb
Host smart-d05f17be-f042-4c55-b68e-3b579ef8af48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783800536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tx_async_fifo_reset.1783800536
Directory /workspace/6.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/6.spi_device_txrx.1584169588
Short name T1228
Test name
Test status
Simulation time 358320935535 ps
CPU time 506.23 seconds
Started Dec 27 01:30:45 PM PST 23
Finished Dec 27 01:39:12 PM PST 23
Peak memory 277704 kb
Host smart-b9449153-9485-4127-8700-9a758ff3310b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584169588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_txrx.1584169588
Directory /workspace/6.spi_device_txrx/latest

Test location /workspace/coverage/default/6.spi_device_upload.492082363
Short name T729
Test name
Test status
Simulation time 1097163116 ps
CPU time 10.9 seconds
Started Dec 27 01:31:03 PM PST 23
Finished Dec 27 01:31:14 PM PST 23
Peak memory 231860 kb
Host smart-8cbdca17-d575-4ae3-9701-cc83ad5d4d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492082363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.492082363
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_abort.1697774603
Short name T766
Test name
Test status
Simulation time 79565694 ps
CPU time 0.73 seconds
Started Dec 27 01:30:57 PM PST 23
Finished Dec 27 01:30:59 PM PST 23
Peak memory 206548 kb
Host smart-ab656f70-af6a-47d9-82cf-3fa1176d3b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697774603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_abort.1697774603
Directory /workspace/7.spi_device_abort/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2267965775
Short name T629
Test name
Test status
Simulation time 41005492 ps
CPU time 0.7 seconds
Started Dec 27 01:31:02 PM PST 23
Finished Dec 27 01:31:03 PM PST 23
Peak memory 206496 kb
Host smart-72e9beea-bdbd-4c5d-b733-a209aa3a7e91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267965775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
267965775
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_bit_transfer.1945199817
Short name T1011
Test name
Test status
Simulation time 286907086 ps
CPU time 2.83 seconds
Started Dec 27 01:31:18 PM PST 23
Finished Dec 27 01:31:21 PM PST 23
Peak memory 216752 kb
Host smart-20337c5a-9cea-48bf-936d-80e8ed5483fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945199817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_bit_transfer.1945199817
Directory /workspace/7.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/7.spi_device_byte_transfer.238492566
Short name T1240
Test name
Test status
Simulation time 257174347 ps
CPU time 3.5 seconds
Started Dec 27 01:31:07 PM PST 23
Finished Dec 27 01:31:11 PM PST 23
Peak memory 216808 kb
Host smart-7a72e95d-4813-4a22-bde5-75e45da2bfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238492566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_byte_transfer.238492566
Directory /workspace/7.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1280055693
Short name T1018
Test name
Test status
Simulation time 15925368837 ps
CPU time 5.62 seconds
Started Dec 27 01:31:30 PM PST 23
Finished Dec 27 01:31:36 PM PST 23
Peak memory 222656 kb
Host smart-3ec982f0-bdfc-4d07-8d41-0b28627e49db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280055693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1280055693
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2266223721
Short name T532
Test name
Test status
Simulation time 30629983 ps
CPU time 0.79 seconds
Started Dec 27 01:31:06 PM PST 23
Finished Dec 27 01:31:08 PM PST 23
Peak memory 207572 kb
Host smart-ef18ecac-965c-41ed-8b4c-a106b53413ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266223721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2266223721
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_dummy_item_extra_dly.3477136381
Short name T633
Test name
Test status
Simulation time 97458531632 ps
CPU time 278.92 seconds
Started Dec 27 01:30:59 PM PST 23
Finished Dec 27 01:35:39 PM PST 23
Peak memory 257588 kb
Host smart-319b2846-69e3-4fae-8909-ab7dcb16c94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477136381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_dummy_item_extra_dly.3477136381
Directory /workspace/7.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/7.spi_device_extreme_fifo_size.503570686
Short name T788
Test name
Test status
Simulation time 43958610250 ps
CPU time 49.28 seconds
Started Dec 27 01:31:10 PM PST 23
Finished Dec 27 01:32:00 PM PST 23
Peak memory 232256 kb
Host smart-b267f8da-88d7-42b0-913c-52e990b55759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503570686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_extreme_fifo_size.503570686
Directory /workspace/7.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/7.spi_device_fifo_full.1738432294
Short name T865
Test name
Test status
Simulation time 337188105665 ps
CPU time 1090.77 seconds
Started Dec 27 01:30:55 PM PST 23
Finished Dec 27 01:49:07 PM PST 23
Peak memory 290492 kb
Host smart-0e50ed79-19a4-4660-8bc3-eac1faba49de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738432294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_fifo_full.1738432294
Directory /workspace/7.spi_device_fifo_full/latest

Test location /workspace/coverage/default/7.spi_device_fifo_underflow_overflow.3023488463
Short name T1066
Test name
Test status
Simulation time 62034364620 ps
CPU time 338.66 seconds
Started Dec 27 01:31:06 PM PST 23
Finished Dec 27 01:36:46 PM PST 23
Peak memory 361300 kb
Host smart-f69c155b-1e89-4bec-99ed-785e33a84803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023488463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_fifo_underflow_overfl
ow.3023488463
Directory /workspace/7.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1562425528
Short name T8
Test name
Test status
Simulation time 93467651962 ps
CPU time 131.07 seconds
Started Dec 27 01:31:10 PM PST 23
Finished Dec 27 01:33:21 PM PST 23
Peak memory 254532 kb
Host smart-d02d49b8-669f-4a99-9b9b-41d3145e1e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562425528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1562425528
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2315725440
Short name T1677
Test name
Test status
Simulation time 33860613083 ps
CPU time 66.28 seconds
Started Dec 27 01:31:08 PM PST 23
Finished Dec 27 01:32:15 PM PST 23
Peak memory 258016 kb
Host smart-e6c7ab56-f07c-4437-bc4e-55b3899cb12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315725440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2315725440
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1654090815
Short name T1378
Test name
Test status
Simulation time 3010328375 ps
CPU time 5.99 seconds
Started Dec 27 01:31:04 PM PST 23
Finished Dec 27 01:31:11 PM PST 23
Peak memory 239956 kb
Host smart-47eddb82-a6bd-4480-95c6-68025f430c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654090815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1654090815
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4237770309
Short name T1100
Test name
Test status
Simulation time 153798718 ps
CPU time 3.02 seconds
Started Dec 27 01:31:10 PM PST 23
Finished Dec 27 01:31:14 PM PST 23
Peak memory 226116 kb
Host smart-9a6d506e-e581-4c00-8587-ab61baf7b979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237770309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4237770309
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_intr.1841137093
Short name T1694
Test name
Test status
Simulation time 29548082774 ps
CPU time 113.74 seconds
Started Dec 27 01:31:14 PM PST 23
Finished Dec 27 01:33:08 PM PST 23
Peak memory 248948 kb
Host smart-857d7f1c-222d-443a-9ea4-297e888cc269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841137093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intr.1841137093
Directory /workspace/7.spi_device_intr/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3353690183
Short name T1283
Test name
Test status
Simulation time 3397050984 ps
CPU time 17.78 seconds
Started Dec 27 01:31:13 PM PST 23
Finished Dec 27 01:31:31 PM PST 23
Peak memory 229468 kb
Host smart-ff4cc5b7-265f-4959-b3e0-ac148d89267f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353690183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3353690183
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.619380673
Short name T1324
Test name
Test status
Simulation time 30444695 ps
CPU time 1.01 seconds
Started Dec 27 01:31:03 PM PST 23
Finished Dec 27 01:31:05 PM PST 23
Peak memory 218892 kb
Host smart-12836b2d-8b90-4d06-b74f-6159c17fd98a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619380673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.619380673
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3389427124
Short name T1165
Test name
Test status
Simulation time 46121680485 ps
CPU time 13.23 seconds
Started Dec 27 01:31:14 PM PST 23
Finished Dec 27 01:31:28 PM PST 23
Peak memory 219416 kb
Host smart-d87aa5a5-e009-4a1a-b72c-a2be5ea3822b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389427124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3389427124
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.646645205
Short name T1112
Test name
Test status
Simulation time 876397813 ps
CPU time 5.87 seconds
Started Dec 27 01:31:11 PM PST 23
Finished Dec 27 01:31:17 PM PST 23
Peak memory 220360 kb
Host smart-3b785ed9-ba5a-454f-be3c-568a7feb0d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646645205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.646645205
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_perf.3906625032
Short name T581
Test name
Test status
Simulation time 120443963242 ps
CPU time 1725.01 seconds
Started Dec 27 01:31:04 PM PST 23
Finished Dec 27 01:59:50 PM PST 23
Peak memory 282528 kb
Host smart-b3ef25f3-d877-4ff5-95f0-7a7300bac56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906625032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_perf.3906625032
Directory /workspace/7.spi_device_perf/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.1127374191
Short name T1314
Test name
Test status
Simulation time 33046974 ps
CPU time 0.72 seconds
Started Dec 27 01:30:47 PM PST 23
Finished Dec 27 01:30:53 PM PST 23
Peak memory 216728 kb
Host smart-8b599dbb-eb69-4763-a03d-a984c22c2bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127374191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.1127374191
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1095280324
Short name T527
Test name
Test status
Simulation time 1250851303 ps
CPU time 5.79 seconds
Started Dec 27 01:31:06 PM PST 23
Finished Dec 27 01:31:13 PM PST 23
Peak memory 234404 kb
Host smart-e3540969-ec8e-48be-b01f-e2db74968bb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1095280324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1095280324
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_rx_async_fifo_reset.1598897887
Short name T645
Test name
Test status
Simulation time 49517601 ps
CPU time 0.9 seconds
Started Dec 27 01:31:14 PM PST 23
Finished Dec 27 01:31:15 PM PST 23
Peak memory 208444 kb
Host smart-b4de440a-0194-468c-ae8d-ac312323d09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598897887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_rx_async_fifo_reset.1598897887
Directory /workspace/7.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/7.spi_device_rx_timeout.1853901026
Short name T1375
Test name
Test status
Simulation time 1207182984 ps
CPU time 4.71 seconds
Started Dec 27 01:30:54 PM PST 23
Finished Dec 27 01:30:59 PM PST 23
Peak memory 216864 kb
Host smart-0654e596-7540-4682-9aaa-e705ec70d263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853901026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_rx_timeout.1853901026
Directory /workspace/7.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/7.spi_device_smoke.1710811438
Short name T1684
Test name
Test status
Simulation time 14751094 ps
CPU time 0.97 seconds
Started Dec 27 01:30:40 PM PST 23
Finished Dec 27 01:30:42 PM PST 23
Peak memory 208092 kb
Host smart-ad7d5a25-26de-4534-bdc9-653dbbdddc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710811438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_smoke.1710811438
Directory /workspace/7.spi_device_smoke/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3802033037
Short name T1115
Test name
Test status
Simulation time 135845125510 ps
CPU time 568.94 seconds
Started Dec 27 01:30:51 PM PST 23
Finished Dec 27 01:40:21 PM PST 23
Peak memory 348752 kb
Host smart-83a7ae4b-f1f6-4ba1-a4c1-7ece3f83b98d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802033037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3802033037
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.69886455
Short name T1551
Test name
Test status
Simulation time 1966390547 ps
CPU time 9.62 seconds
Started Dec 27 01:31:07 PM PST 23
Finished Dec 27 01:31:18 PM PST 23
Peak memory 216936 kb
Host smart-1b73f651-b455-41c5-8465-a4a3d16f9fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69886455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.69886455
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3144327676
Short name T549
Test name
Test status
Simulation time 29291323607 ps
CPU time 24.1 seconds
Started Dec 27 01:30:48 PM PST 23
Finished Dec 27 01:31:13 PM PST 23
Peak memory 216812 kb
Host smart-a32138ac-ae71-48dc-9575-7fd82e3c1f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144327676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3144327676
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3183048640
Short name T1644
Test name
Test status
Simulation time 655239040 ps
CPU time 4.28 seconds
Started Dec 27 01:31:11 PM PST 23
Finished Dec 27 01:31:16 PM PST 23
Peak memory 216876 kb
Host smart-0570eb22-cc11-4b4c-8384-6cd662bccbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183048640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3183048640
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.411075789
Short name T1548
Test name
Test status
Simulation time 83043688 ps
CPU time 0.79 seconds
Started Dec 27 01:31:05 PM PST 23
Finished Dec 27 01:31:06 PM PST 23
Peak memory 206944 kb
Host smart-85e7f101-0983-47c6-ab6b-650fe204a538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411075789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.411075789
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_txrx.3546993780
Short name T19
Test name
Test status
Simulation time 113889172510 ps
CPU time 535.47 seconds
Started Dec 27 01:31:13 PM PST 23
Finished Dec 27 01:40:09 PM PST 23
Peak memory 258484 kb
Host smart-007c93c8-85a6-4bca-b150-1e144525ea35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546993780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_txrx.3546993780
Directory /workspace/7.spi_device_txrx/latest

Test location /workspace/coverage/default/7.spi_device_upload.3816037864
Short name T793
Test name
Test status
Simulation time 131689178 ps
CPU time 2.69 seconds
Started Dec 27 01:31:10 PM PST 23
Finished Dec 27 01:31:13 PM PST 23
Peak memory 234280 kb
Host smart-3a0ec65c-520e-4911-8748-1f8b7983323c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816037864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3816037864
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_abort.4259451783
Short name T95
Test name
Test status
Simulation time 28687741 ps
CPU time 0.77 seconds
Started Dec 27 01:31:12 PM PST 23
Finished Dec 27 01:31:13 PM PST 23
Peak memory 206536 kb
Host smart-07e9d047-c862-4904-900d-c40b20b982cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259451783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_abort.4259451783
Directory /workspace/8.spi_device_abort/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.338263356
Short name T1599
Test name
Test status
Simulation time 20570234 ps
CPU time 0.71 seconds
Started Dec 27 01:31:24 PM PST 23
Finished Dec 27 01:31:25 PM PST 23
Peak memory 206520 kb
Host smart-518b722b-2055-4f2c-8b87-cc75259a23bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338263356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.338263356
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_bit_transfer.2299142759
Short name T1680
Test name
Test status
Simulation time 1055741252 ps
CPU time 2.76 seconds
Started Dec 27 01:32:39 PM PST 23
Finished Dec 27 01:32:48 PM PST 23
Peak memory 216832 kb
Host smart-0ff64eb4-69e6-484d-ae98-422779e9b718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299142759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_bit_transfer.2299142759
Directory /workspace/8.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/8.spi_device_byte_transfer.1740865810
Short name T768
Test name
Test status
Simulation time 116767785 ps
CPU time 2.69 seconds
Started Dec 27 01:31:55 PM PST 23
Finished Dec 27 01:31:59 PM PST 23
Peak memory 216712 kb
Host smart-4f1a2906-4b56-47c2-b794-d4cff4e72547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740865810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_byte_transfer.1740865810
Directory /workspace/8.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1765924766
Short name T1366
Test name
Test status
Simulation time 2085422365 ps
CPU time 6.46 seconds
Started Dec 27 01:31:34 PM PST 23
Finished Dec 27 01:31:41 PM PST 23
Peak memory 241452 kb
Host smart-7a2e02c6-ab6d-4143-81a7-8cc74feeeb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765924766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1765924766
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2446991762
Short name T1457
Test name
Test status
Simulation time 93775348 ps
CPU time 0.76 seconds
Started Dec 27 01:31:34 PM PST 23
Finished Dec 27 01:31:35 PM PST 23
Peak memory 207572 kb
Host smart-7952503d-679a-4bf3-8924-0b82c3ddc5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446991762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2446991762
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_dummy_item_extra_dly.1193098318
Short name T970
Test name
Test status
Simulation time 24979256178 ps
CPU time 203.48 seconds
Started Dec 27 01:32:14 PM PST 23
Finished Dec 27 01:35:52 PM PST 23
Peak memory 273500 kb
Host smart-646abc9b-dda3-4452-837d-26d1b212df73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193098318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_dummy_item_extra_dly.1193098318
Directory /workspace/8.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/8.spi_device_extreme_fifo_size.3898871917
Short name T999
Test name
Test status
Simulation time 13422137941 ps
CPU time 37.73 seconds
Started Dec 27 01:31:28 PM PST 23
Finished Dec 27 01:32:06 PM PST 23
Peak memory 240656 kb
Host smart-aeb1ca58-2d7a-464b-b0aa-46bfdfcd6772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898871917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_extreme_fifo_size.3898871917
Directory /workspace/8.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/8.spi_device_fifo_full.1311752119
Short name T1377
Test name
Test status
Simulation time 66421030590 ps
CPU time 755.51 seconds
Started Dec 27 01:32:14 PM PST 23
Finished Dec 27 01:44:58 PM PST 23
Peak memory 322636 kb
Host smart-c7e4951b-8e44-415e-88de-bd731df15df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311752119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_fifo_full.1311752119
Directory /workspace/8.spi_device_fifo_full/latest

Test location /workspace/coverage/default/8.spi_device_fifo_underflow_overflow.1954556260
Short name T812
Test name
Test status
Simulation time 47800082890 ps
CPU time 300.69 seconds
Started Dec 27 01:32:04 PM PST 23
Finished Dec 27 01:37:05 PM PST 23
Peak memory 332800 kb
Host smart-40e9f39e-3a72-4aca-8673-cefd00dd1415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954556260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_fifo_underflow_overfl
ow.1954556260
Directory /workspace/8.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1214957233
Short name T120
Test name
Test status
Simulation time 114387985572 ps
CPU time 146.72 seconds
Started Dec 27 01:32:09 PM PST 23
Finished Dec 27 01:34:37 PM PST 23
Peak memory 264932 kb
Host smart-1441712f-42e3-4b19-a9a9-137bf740359d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214957233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1214957233
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1629170300
Short name T1202
Test name
Test status
Simulation time 47043818942 ps
CPU time 279.23 seconds
Started Dec 27 01:31:53 PM PST 23
Finished Dec 27 01:36:32 PM PST 23
Peak memory 250132 kb
Host smart-d7a39f3b-c308-4da6-baab-e730d3035da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629170300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1629170300
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3034530274
Short name T228
Test name
Test status
Simulation time 68007452060 ps
CPU time 511.4 seconds
Started Dec 27 01:32:10 PM PST 23
Finished Dec 27 01:40:43 PM PST 23
Peak memory 274356 kb
Host smart-39f98134-8273-40ff-9fbb-6f99f1b29cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034530274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3034530274
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3616381427
Short name T754
Test name
Test status
Simulation time 770255145 ps
CPU time 13.98 seconds
Started Dec 27 01:31:29 PM PST 23
Finished Dec 27 01:31:43 PM PST 23
Peak memory 238232 kb
Host smart-208f6287-a417-407b-9736-2e88de19e855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616381427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3616381427
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1797968251
Short name T1345
Test name
Test status
Simulation time 19818582767 ps
CPU time 16.4 seconds
Started Dec 27 01:31:09 PM PST 23
Finished Dec 27 01:31:26 PM PST 23
Peak memory 221004 kb
Host smart-c01976a6-a03e-465a-826e-ed0e3e1e6db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797968251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1797968251
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3576311227
Short name T959
Test name
Test status
Simulation time 8292880927 ps
CPU time 11.87 seconds
Started Dec 27 01:31:51 PM PST 23
Finished Dec 27 01:32:03 PM PST 23
Peak memory 219444 kb
Host smart-263dba9c-9b3c-4934-810c-1bc46a03f75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576311227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3576311227
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.942368800
Short name T1170
Test name
Test status
Simulation time 46815085 ps
CPU time 1 seconds
Started Dec 27 01:32:12 PM PST 23
Finished Dec 27 01:32:15 PM PST 23
Peak memory 218840 kb
Host smart-c359b377-6440-40ed-b52a-86276ae42518
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942368800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.942368800
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4021296950
Short name T269
Test name
Test status
Simulation time 905537915 ps
CPU time 5.01 seconds
Started Dec 27 01:31:04 PM PST 23
Finished Dec 27 01:31:10 PM PST 23
Peak memory 247432 kb
Host smart-06359801-e75f-4a94-996b-aa5150ed049a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021296950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4021296950
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2040941008
Short name T1271
Test name
Test status
Simulation time 1254040156 ps
CPU time 8.2 seconds
Started Dec 27 01:31:02 PM PST 23
Finished Dec 27 01:31:11 PM PST 23
Peak memory 226784 kb
Host smart-d6779f09-c0d8-4d8d-a155-8de56aedd209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040941008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2040941008
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_perf.2626373204
Short name T73
Test name
Test status
Simulation time 6065515610 ps
CPU time 136.4 seconds
Started Dec 27 01:32:02 PM PST 23
Finished Dec 27 01:34:19 PM PST 23
Peak memory 240884 kb
Host smart-26fb6417-a7b2-40c9-9fbb-06bc35304526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626373204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_perf.2626373204
Directory /workspace/8.spi_device_perf/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.3989908025
Short name T4
Test name
Test status
Simulation time 47413373 ps
CPU time 0.72 seconds
Started Dec 27 01:32:00 PM PST 23
Finished Dec 27 01:32:02 PM PST 23
Peak memory 216724 kb
Host smart-aaf66a95-8fe1-4870-89c0-d7f1ee9815cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989908025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.3989908025
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.4007737998
Short name T674
Test name
Test status
Simulation time 4332323966 ps
CPU time 4.74 seconds
Started Dec 27 01:31:21 PM PST 23
Finished Dec 27 01:31:26 PM PST 23
Peak memory 218552 kb
Host smart-ae56b85f-8473-4783-a6d3-a78540ce5924
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4007737998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.4007737998
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_rx_async_fifo_reset.735752566
Short name T1423
Test name
Test status
Simulation time 163585790 ps
CPU time 0.94 seconds
Started Dec 27 01:31:10 PM PST 23
Finished Dec 27 01:31:11 PM PST 23
Peak memory 208512 kb
Host smart-fe8ffc31-dbaf-4f18-a545-fa91f69d169e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735752566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_rx_async_fifo_reset.735752566
Directory /workspace/8.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/8.spi_device_rx_timeout.2652129890
Short name T513
Test name
Test status
Simulation time 3095250527 ps
CPU time 5.86 seconds
Started Dec 27 01:31:34 PM PST 23
Finished Dec 27 01:31:41 PM PST 23
Peak memory 216892 kb
Host smart-33879ad6-3c7a-4dfd-8531-d5cd704b0e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652129890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_rx_timeout.2652129890
Directory /workspace/8.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/8.spi_device_smoke.102960544
Short name T933
Test name
Test status
Simulation time 858081502 ps
CPU time 1.26 seconds
Started Dec 27 01:30:59 PM PST 23
Finished Dec 27 01:31:01 PM PST 23
Peak memory 216464 kb
Host smart-b2224321-9f4b-4844-8a72-f965500f82fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102960544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_smoke.102960544
Directory /workspace/8.spi_device_smoke/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3991019140
Short name T1333
Test name
Test status
Simulation time 28958517481 ps
CPU time 321.84 seconds
Started Dec 27 01:31:24 PM PST 23
Finished Dec 27 01:36:47 PM PST 23
Peak memory 449580 kb
Host smart-2bef5205-40f8-4c72-bdd3-426e027c6e4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991019140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3991019140
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1062819681
Short name T357
Test name
Test status
Simulation time 5086505643 ps
CPU time 33.06 seconds
Started Dec 27 01:32:28 PM PST 23
Finished Dec 27 01:33:07 PM PST 23
Peak memory 217080 kb
Host smart-3effcffe-a449-48a7-bb4b-2487d432faf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062819681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1062819681
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3040274666
Short name T845
Test name
Test status
Simulation time 21874941067 ps
CPU time 21.96 seconds
Started Dec 27 01:30:45 PM PST 23
Finished Dec 27 01:31:07 PM PST 23
Peak memory 216900 kb
Host smart-f492be50-2edf-4b5d-ac8a-9ad8b42b5703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040274666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3040274666
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.926660678
Short name T522
Test name
Test status
Simulation time 850775443 ps
CPU time 1.82 seconds
Started Dec 27 01:30:47 PM PST 23
Finished Dec 27 01:30:49 PM PST 23
Peak memory 216896 kb
Host smart-00b191ec-5a4d-4e36-a2b9-25dd8aac3083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926660678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.926660678
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3463772106
Short name T599
Test name
Test status
Simulation time 56532315 ps
CPU time 0.87 seconds
Started Dec 27 01:31:05 PM PST 23
Finished Dec 27 01:31:07 PM PST 23
Peak memory 206872 kb
Host smart-be34a6c4-8e5f-4bb2-aa4b-760beab9e6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463772106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3463772106
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_tx_async_fifo_reset.2115425933
Short name T1379
Test name
Test status
Simulation time 219475920 ps
CPU time 0.75 seconds
Started Dec 27 01:30:54 PM PST 23
Finished Dec 27 01:30:55 PM PST 23
Peak memory 208508 kb
Host smart-174f4591-1d78-47dc-b559-730c82f024f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115425933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tx_async_fifo_reset.2115425933
Directory /workspace/8.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/8.spi_device_txrx.1897222213
Short name T663
Test name
Test status
Simulation time 11078219518 ps
CPU time 130.86 seconds
Started Dec 27 01:31:55 PM PST 23
Finished Dec 27 01:34:07 PM PST 23
Peak memory 284720 kb
Host smart-7cdb38fb-2223-458e-866d-030a56999517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897222213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_txrx.1897222213
Directory /workspace/8.spi_device_txrx/latest

Test location /workspace/coverage/default/8.spi_device_upload.2165134095
Short name T1282
Test name
Test status
Simulation time 9050607821 ps
CPU time 10.37 seconds
Started Dec 27 01:31:46 PM PST 23
Finished Dec 27 01:31:57 PM PST 23
Peak memory 223728 kb
Host smart-249caa27-1d3a-4ef8-89f2-3027724c92d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165134095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2165134095
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_abort.2049595480
Short name T841
Test name
Test status
Simulation time 106906506 ps
CPU time 0.75 seconds
Started Dec 27 01:31:06 PM PST 23
Finished Dec 27 01:31:08 PM PST 23
Peak memory 206652 kb
Host smart-455dc5dc-9f7a-4325-8ce5-f64056e6d9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049595480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_abort.2049595480
Directory /workspace/9.spi_device_abort/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1198514249
Short name T1016
Test name
Test status
Simulation time 18613004 ps
CPU time 0.75 seconds
Started Dec 27 01:31:09 PM PST 23
Finished Dec 27 01:31:10 PM PST 23
Peak memory 206536 kb
Host smart-0ac20138-2c40-4d69-9e16-6279a8babe39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198514249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
198514249
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_bit_transfer.3243712143
Short name T1295
Test name
Test status
Simulation time 300535309 ps
CPU time 2.07 seconds
Started Dec 27 01:31:02 PM PST 23
Finished Dec 27 01:31:04 PM PST 23
Peak memory 216824 kb
Host smart-f0c4d68d-7f60-4a79-ad91-97c168c01046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243712143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_bit_transfer.3243712143
Directory /workspace/9.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/9.spi_device_byte_transfer.2866381854
Short name T531
Test name
Test status
Simulation time 271459623 ps
CPU time 3.41 seconds
Started Dec 27 01:31:00 PM PST 23
Finished Dec 27 01:31:04 PM PST 23
Peak memory 216820 kb
Host smart-b95e487b-2a39-4d2a-9b14-0cf36cb553a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866381854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_byte_transfer.2866381854
Directory /workspace/9.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3952349376
Short name T315
Test name
Test status
Simulation time 4038434742 ps
CPU time 5.47 seconds
Started Dec 27 01:31:26 PM PST 23
Finished Dec 27 01:31:32 PM PST 23
Peak memory 225116 kb
Host smart-fa6155f8-f2fb-4226-a6bc-e60884f57aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952349376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3952349376
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3382414330
Short name T1273
Test name
Test status
Simulation time 52277048 ps
CPU time 0.78 seconds
Started Dec 27 01:31:14 PM PST 23
Finished Dec 27 01:31:15 PM PST 23
Peak memory 207484 kb
Host smart-eaa88540-513b-4598-bb9a-eb8bd1f935fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382414330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3382414330
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_dummy_item_extra_dly.3037721425
Short name T1534
Test name
Test status
Simulation time 74064459710 ps
CPU time 281.11 seconds
Started Dec 27 01:31:16 PM PST 23
Finished Dec 27 01:35:57 PM PST 23
Peak memory 290612 kb
Host smart-3ff77f0d-a8ff-4136-aaa1-297499824564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037721425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_dummy_item_extra_dly.3037721425
Directory /workspace/9.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/9.spi_device_extreme_fifo_size.1039127847
Short name T982
Test name
Test status
Simulation time 196671048625 ps
CPU time 896.51 seconds
Started Dec 27 01:31:13 PM PST 23
Finished Dec 27 01:46:10 PM PST 23
Peak memory 219000 kb
Host smart-0aab4ef7-bbd7-4ab4-93f7-91c487d49fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039127847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_extreme_fifo_size.1039127847
Directory /workspace/9.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/9.spi_device_fifo_full.3966903217
Short name T587
Test name
Test status
Simulation time 39596367733 ps
CPU time 626.53 seconds
Started Dec 27 01:31:00 PM PST 23
Finished Dec 27 01:41:27 PM PST 23
Peak memory 249740 kb
Host smart-1fb30d95-9636-4027-9fd8-e4c52f0ca00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966903217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_fifo_full.3966903217
Directory /workspace/9.spi_device_fifo_full/latest

Test location /workspace/coverage/default/9.spi_device_fifo_underflow_overflow.2364563110
Short name T1575
Test name
Test status
Simulation time 158969814790 ps
CPU time 242.85 seconds
Started Dec 27 01:30:55 PM PST 23
Finished Dec 27 01:34:59 PM PST 23
Peak memory 314948 kb
Host smart-8ea18091-ccf9-4f95-b673-90b4c69b1942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364563110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_fifo_underflow_overfl
ow.2364563110
Directory /workspace/9.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2647884211
Short name T225
Test name
Test status
Simulation time 12185934056 ps
CPU time 30.34 seconds
Started Dec 27 01:31:24 PM PST 23
Finished Dec 27 01:31:55 PM PST 23
Peak memory 249652 kb
Host smart-85c6c8a9-b6ac-4610-a97b-73f84825d387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647884211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2647884211
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2892391496
Short name T1543
Test name
Test status
Simulation time 38591092742 ps
CPU time 109.85 seconds
Started Dec 27 01:31:50 PM PST 23
Finished Dec 27 01:33:40 PM PST 23
Peak memory 255456 kb
Host smart-f17b4d83-bdcf-4e22-bca5-61f766fa7c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892391496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2892391496
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.672102577
Short name T1727
Test name
Test status
Simulation time 595926860 ps
CPU time 9.22 seconds
Started Dec 27 01:31:29 PM PST 23
Finished Dec 27 01:31:39 PM PST 23
Peak memory 235780 kb
Host smart-fb883523-66d5-49f2-b79d-a754b1430b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672102577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.672102577
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3236822861
Short name T1451
Test name
Test status
Simulation time 17244195798 ps
CPU time 15.44 seconds
Started Dec 27 01:31:08 PM PST 23
Finished Dec 27 01:31:24 PM PST 23
Peak memory 238440 kb
Host smart-120adfd3-a601-44ae-ae07-d4ab7c80c01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236822861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3236822861
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_intr.961526719
Short name T525
Test name
Test status
Simulation time 12559499114 ps
CPU time 26.01 seconds
Started Dec 27 01:31:11 PM PST 23
Finished Dec 27 01:31:38 PM PST 23
Peak memory 232168 kb
Host smart-9c43bb29-c621-4d56-9682-7e3e7d3e6009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961526719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intr.961526719
Directory /workspace/9.spi_device_intr/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.4180311498
Short name T1509
Test name
Test status
Simulation time 785508215 ps
CPU time 7.25 seconds
Started Dec 27 01:31:26 PM PST 23
Finished Dec 27 01:31:34 PM PST 23
Peak memory 249192 kb
Host smart-75a6c380-d10f-4e37-91f2-adc00ed3a789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180311498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4180311498
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2163968417
Short name T1706
Test name
Test status
Simulation time 114951127 ps
CPU time 1.08 seconds
Started Dec 27 01:31:08 PM PST 23
Finished Dec 27 01:31:10 PM PST 23
Peak memory 218832 kb
Host smart-20c99b18-f17e-4a95-8fcc-43d1b539e532
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163968417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2163968417
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.326596044
Short name T1702
Test name
Test status
Simulation time 9759185820 ps
CPU time 12.72 seconds
Started Dec 27 01:31:56 PM PST 23
Finished Dec 27 01:32:10 PM PST 23
Peak memory 238572 kb
Host smart-d42ffb0b-fb31-4327-ace5-7d902f6f3aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326596044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
326596044
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.407503344
Short name T1102
Test name
Test status
Simulation time 49272612433 ps
CPU time 68.54 seconds
Started Dec 27 01:31:05 PM PST 23
Finished Dec 27 01:32:14 PM PST 23
Peak memory 257228 kb
Host smart-7a2c4376-4328-42e6-ae13-8d650e2b5cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407503344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.407503344
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_perf.2696755460
Short name T932
Test name
Test status
Simulation time 82569862851 ps
CPU time 1128.87 seconds
Started Dec 27 01:30:56 PM PST 23
Finished Dec 27 01:49:46 PM PST 23
Peak memory 273732 kb
Host smart-b939b06d-55db-4c48-ac4f-dddc5761e714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696755460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_perf.2696755460
Directory /workspace/9.spi_device_perf/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.4012694497
Short name T1131
Test name
Test status
Simulation time 18028179 ps
CPU time 0.73 seconds
Started Dec 27 01:31:11 PM PST 23
Finished Dec 27 01:31:12 PM PST 23
Peak memory 216660 kb
Host smart-289328c5-c8da-4d01-bc4e-b19d499f4ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012694497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.4012694497
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1398669295
Short name T1193
Test name
Test status
Simulation time 2090426222 ps
CPU time 5.92 seconds
Started Dec 27 01:31:23 PM PST 23
Finished Dec 27 01:31:34 PM PST 23
Peak memory 218792 kb
Host smart-1f2b11e3-0088-4eec-b6eb-a3d5720686b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1398669295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1398669295
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_rx_async_fifo_reset.401653779
Short name T1664
Test name
Test status
Simulation time 53255467 ps
CPU time 0.88 seconds
Started Dec 27 01:31:20 PM PST 23
Finished Dec 27 01:31:22 PM PST 23
Peak memory 208520 kb
Host smart-ba268eaa-7fd5-4ce9-85fc-a40b41a374bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401653779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_rx_async_fifo_reset.401653779
Directory /workspace/9.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/9.spi_device_rx_timeout.2060224634
Short name T1205
Test name
Test status
Simulation time 3484624197 ps
CPU time 5.7 seconds
Started Dec 27 01:31:10 PM PST 23
Finished Dec 27 01:31:17 PM PST 23
Peak memory 216964 kb
Host smart-eab709c5-0f07-4300-99d9-60b563c09f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060224634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_rx_timeout.2060224634
Directory /workspace/9.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/9.spi_device_smoke.3909743798
Short name T1693
Test name
Test status
Simulation time 16811808 ps
CPU time 0.88 seconds
Started Dec 27 01:31:29 PM PST 23
Finished Dec 27 01:31:30 PM PST 23
Peak memory 207780 kb
Host smart-fbcf667d-dbf0-4770-8b59-75cdd0855904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909743798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_smoke.3909743798
Directory /workspace/9.spi_device_smoke/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1840175129
Short name T771
Test name
Test status
Simulation time 2638481066 ps
CPU time 7.83 seconds
Started Dec 27 01:31:10 PM PST 23
Finished Dec 27 01:31:18 PM PST 23
Peak memory 216852 kb
Host smart-44166c1e-8e41-43cc-ac7f-1cf4c3cb2e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840175129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1840175129
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1370106334
Short name T1309
Test name
Test status
Simulation time 311078598 ps
CPU time 4.46 seconds
Started Dec 27 01:31:13 PM PST 23
Finished Dec 27 01:31:18 PM PST 23
Peak memory 216692 kb
Host smart-c26bb09e-6cb9-45a6-abe4-9dfea7ea32ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370106334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1370106334
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.409451107
Short name T1288
Test name
Test status
Simulation time 146736908 ps
CPU time 0.93 seconds
Started Dec 27 01:32:20 PM PST 23
Finished Dec 27 01:32:31 PM PST 23
Peak memory 208416 kb
Host smart-fc98e237-5754-4a5b-99ca-42ea63190127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409451107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.409451107
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_tx_async_fifo_reset.655848812
Short name T796
Test name
Test status
Simulation time 106153249 ps
CPU time 0.77 seconds
Started Dec 27 01:31:14 PM PST 23
Finished Dec 27 01:31:15 PM PST 23
Peak memory 208356 kb
Host smart-6f94d585-1175-4cd7-a42f-332f74ad92b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655848812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tx_async_fifo_reset.655848812
Directory /workspace/9.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/9.spi_device_txrx.1387968572
Short name T665
Test name
Test status
Simulation time 112350174520 ps
CPU time 195.11 seconds
Started Dec 27 01:31:15 PM PST 23
Finished Dec 27 01:34:31 PM PST 23
Peak memory 265536 kb
Host smart-3afb2a4c-0dfe-44bf-8e4e-d06835943189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387968572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_txrx.1387968572
Directory /workspace/9.spi_device_txrx/latest

Test location /workspace/coverage/default/9.spi_device_upload.1027063382
Short name T1376
Test name
Test status
Simulation time 10341074908 ps
CPU time 31.7 seconds
Started Dec 27 01:31:22 PM PST 23
Finished Dec 27 01:31:54 PM PST 23
Peak memory 219800 kb
Host smart-773a8045-5370-4c27-98b9-d8f0a931f46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027063382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1027063382
Directory /workspace/9.spi_device_upload/latest
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