Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	172087056	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

19695336

1

T4

1100

T1

3251

T5

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	179280320	1			T4	17		T1	8058		T5	1
values[0x0]	6249460	1			T4	540		T1	839		T5	12
values[0x1]	6252612	1			T4	558		T1	879		T5	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	87608338	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

104174054

1

T4

1105

T1

6616

T5

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	691730	1			T4	14		T1	39		T27	3
valid_sources[0x01]	763913	1			T4	5		T1	52		T3	42
valid_sources[0x02]	739182	1			T1	30		T6	103		T11	8813
valid_sources[0x03]	753903	1			T4	8		T1	32		T6	99
valid_sources[0x04]	778064	1			T1	47		T6	122		T11	9225
valid_sources[0x05]	707481	1			T4	6		T1	34		T6	105
valid_sources[0x06]	737064	1			T4	5		T1	44		T6	146
valid_sources[0x07]	778461	1			T4	5		T1	34		T6	97
valid_sources[0x08]	780410	1			T4	2		T1	31		T6	118
valid_sources[0x09]	746395	1			T4	6		T1	44		T6	128
valid_sources[0x0a]	704928	1			T4	2		T1	38		T3	7
valid_sources[0x0b]	761009	1			T4	7		T1	34		T6	135
valid_sources[0x0c]	763873	1			T1	47		T6	122		T11	9008
valid_sources[0x0d]	741229	1			T1	44		T6	104		T11	8908
valid_sources[0x0e]	768636	1			T4	7		T1	49		T27	1
valid_sources[0x0f]	725020	1			T1	47		T6	132		T11	8457
valid_sources[0x10]	687402	1			T4	2		T1	23		T27	1
valid_sources[0x11]	740688	1			T4	4		T1	46		T10	570
valid_sources[0x12]	724613	1			T4	6		T1	43		T6	118
valid_sources[0x13]	758698	1			T4	5		T1	48		T6	106
valid_sources[0x14]	712427	1			T4	1		T1	34		T3	7
valid_sources[0x15]	703400	1			T4	2		T1	36		T6	85
valid_sources[0x16]	995604	1			T4	2		T1	41		T6	128
valid_sources[0x17]	730322	1			T4	7		T1	36		T6	122
valid_sources[0x18]	857508	1			T4	2		T1	22		T6	139
valid_sources[0x19]	724398	1			T4	4		T1	42		T3	15
valid_sources[0x1a]	789522	1			T1	42		T6	96		T11	9078
valid_sources[0x1b]	766333	1			T4	3		T1	30		T6	124
valid_sources[0x1c]	740008	1			T4	2		T1	37		T6	102
valid_sources[0x1d]	732034	1			T4	6		T1	38		T6	107
valid_sources[0x1e]	692952	1			T4	6		T1	39		T6	119
valid_sources[0x1f]	728411	1			T1	42		T6	126		T11	9238
valid_sources[0x20]	730716	1			T1	28		T3	7		T6	95
valid_sources[0x21]	732463	1			T1	27		T6	136		T11	9622
valid_sources[0x22]	705647	1			T1	37		T6	116		T11	9658
valid_sources[0x23]	706340	1			T4	2		T1	27		T6	131
valid_sources[0x24]	734415	1			T4	9		T1	26		T27	1
valid_sources[0x25]	746570	1			T4	8		T1	40		T6	125
valid_sources[0x26]	749993	1			T4	6		T1	40		T6	115
valid_sources[0x27]	749267	1			T4	17		T1	30		T6	113
valid_sources[0x28]	745393	1			T1	34		T6	111		T11	8862
valid_sources[0x29]	736732	1			T4	5		T1	41		T5	1
valid_sources[0x2a]	732616	1			T4	8		T1	36		T6	100
valid_sources[0x2b]	800480	1			T4	8		T1	36		T6	111
valid_sources[0x2c]	777001	1			T4	6		T1	24		T6	98
valid_sources[0x2d]	759448	1			T4	2		T1	34		T6	109
valid_sources[0x2e]	738276	1			T4	2		T1	42		T6	114
valid_sources[0x2f]	745252	1			T4	5		T1	31		T6	149
valid_sources[0x30]	733727	1			T4	1		T1	36		T6	110
valid_sources[0x31]	739230	1			T1	31		T6	93		T11	8783
valid_sources[0x32]	715686	1			T4	4		T1	46		T6	119
valid_sources[0x33]	716734	1			T4	1		T1	38		T27	6
valid_sources[0x34]	751420	1			T4	5		T1	64		T6	136
valid_sources[0x35]	742578	1			T4	4		T1	34		T3	3
valid_sources[0x36]	729271	1			T4	10		T1	30		T6	116
valid_sources[0x37]	734044	1			T4	3		T1	48		T6	132
valid_sources[0x38]	750755	1			T4	1		T1	34		T3	17
valid_sources[0x39]	713458	1			T4	3		T1	34		T6	110
valid_sources[0x3a]	710284	1			T4	2		T1	40		T6	120
valid_sources[0x3b]	760729	1			T1	36		T6	116		T11	8917
valid_sources[0x3c]	745355	1			T4	10		T1	25		T6	115
valid_sources[0x3d]	733590	1			T4	4		T1	39		T6	107
valid_sources[0x3e]	1004871	1			T4	3		T1	38		T6	125
valid_sources[0x3f]	820196	1			T4	12		T1	51		T6	120
valid_sources[0x40]	712558	1			T4	3		T1	34		T6	113
valid_sources[0x41]	781003	1			T4	5		T1	26		T2	39
valid_sources[0x42]	763225	1			T4	2		T1	22		T6	112
valid_sources[0x43]	706353	1			T4	2		T1	40		T3	6
valid_sources[0x44]	800844	1			T4	1		T1	31		T6	96
valid_sources[0x45]	743617	1			T4	9		T1	39		T6	111
valid_sources[0x46]	753281	1			T4	5		T1	48		T27	2
valid_sources[0x47]	710860	1			T4	1		T1	36		T6	141
valid_sources[0x48]	754241	1			T4	1		T1	33		T6	97
valid_sources[0x49]	765468	1			T4	4		T1	51		T6	112
valid_sources[0x4a]	724061	1			T1	44		T27	5		T6	115
valid_sources[0x4b]	730192	1			T4	3		T1	39		T3	8
valid_sources[0x4c]	691885	1			T4	15		T1	34		T6	113
valid_sources[0x4d]	946131	1			T4	8		T1	34		T6	109
valid_sources[0x4e]	716903	1			T4	3		T1	44		T6	123
valid_sources[0x4f]	733866	1			T4	12		T1	49		T6	116
valid_sources[0x50]	939110	1			T4	7		T1	40		T6	136
valid_sources[0x51]	739582	1			T1	37		T3	33		T27	5
valid_sources[0x52]	700631	1			T4	2		T1	41		T3	30
valid_sources[0x53]	715555	1			T4	1		T1	31		T6	107
valid_sources[0x54]	702020	1			T4	3		T1	38		T6	89
valid_sources[0x55]	751510	1			T4	4		T1	37		T3	2
valid_sources[0x56]	726895	1			T1	43		T6	112		T11	8908
valid_sources[0x57]	799715	1			T1	43		T3	22		T6	148
valid_sources[0x58]	800552	1			T4	8		T1	52		T6	131
valid_sources[0x59]	751099	1			T4	2		T1	46		T6	108
valid_sources[0x5a]	768135	1			T1	45		T6	120		T11	9255
valid_sources[0x5b]	715552	1			T4	10		T1	42		T6	112
valid_sources[0x5c]	754698	1			T4	9		T1	28		T3	24
valid_sources[0x5d]	759279	1			T1	52		T6	117		T11	9301
valid_sources[0x5e]	775258	1			T4	2		T1	48		T6	116
valid_sources[0x5f]	730605	1			T4	2		T1	49		T6	99
valid_sources[0x60]	751897	1			T4	6		T1	38		T6	123
valid_sources[0x61]	719043	1			T4	5		T1	41		T3	5
valid_sources[0x62]	725687	1			T4	2		T1	38		T27	1
valid_sources[0x63]	683820	1			T4	5		T1	44		T6	108
valid_sources[0x64]	763258	1			T4	3		T1	68		T6	116
valid_sources[0x65]	704558	1			T4	3		T1	50		T6	123
valid_sources[0x66]	752554	1			T4	10		T1	32		T6	112
valid_sources[0x67]	753799	1			T4	12		T1	44		T6	100
valid_sources[0x68]	1156440	1			T4	6		T1	32		T6	107
valid_sources[0x69]	720901	1			T4	5		T1	36		T27	1
valid_sources[0x6a]	738865	1			T4	1		T1	40		T6	92
valid_sources[0x6b]	768517	1			T4	2		T1	38		T6	122
valid_sources[0x6c]	747170	1			T4	11		T1	31		T6	124
valid_sources[0x6d]	732153	1			T4	6		T1	40		T6	117
valid_sources[0x6e]	744645	1			T4	1		T1	39		T6	107
valid_sources[0x6f]	702142	1			T4	7		T1	44		T6	124
valid_sources[0x70]	753423	1			T4	1		T1	35		T6	119
valid_sources[0x71]	746338	1			T4	2		T1	45		T3	11
valid_sources[0x72]	722634	1			T4	9		T1	37		T6	110
valid_sources[0x73]	772367	1			T4	1		T1	23		T6	123
valid_sources[0x74]	777971	1			T4	8		T1	28		T6	112
valid_sources[0x75]	750654	1			T4	14		T1	36		T6	109
valid_sources[0x76]	758818	1			T4	5		T1	28		T6	118
valid_sources[0x77]	752766	1			T4	10		T1	48		T27	2
valid_sources[0x78]	747982	1			T4	5		T1	46		T6	135
valid_sources[0x79]	738860	1			T4	3		T1	50		T6	102
valid_sources[0x7a]	726509	1			T4	5		T1	42		T6	111
valid_sources[0x7b]	747596	1			T4	3		T1	26		T6	110
valid_sources[0x7c]	744994	1			T4	9		T1	26		T6	110
valid_sources[0x7d]	740344	1			T4	5		T1	34		T6	116
valid_sources[0x7e]	745323	1			T4	7		T1	30		T3	2
valid_sources[0x7f]	734167	1			T1	36		T3	4		T27	2
valid_sources[0x80]	700318	1			T4	3		T1	40		T6	95

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7494620

1

T4

8

T1

1535

T2

2

values[0x0]

all_enables

biggest_size

6109022

1

T4

539

T1

838

T5

4

values[0x1]

all_enables

biggest_size

6091694

1

T4

553

T1

878

T5

4